US2404047A - Electronic computing device - Google Patents

Description

July l5, 1946. L. E. FLORY ET AL 2,404,047

ELECTRONIC COMPUTNG DEVICE Filed Jan. 21, 1943 3 Sheets-Sheet l 4a 44 4g' 45 5M Summers 'ZF-fj GORGC Q TIOR-ron Juny 1e, 1946.

L E- FLORY ET AL.

ELECTRONIC COMPUTING DEVICE Filed Jan. 21, 1945 3 Sheets-Sheet 2 5L/0EBACK TYPE i i a'/ V L@ I l I l l l i: i: q g i 5&7? I H /l l 7@ l i I i i e i N @L J D75 L 'L I T *www1/55u ses.

,9 eoRGe F1. mom-on Le/Lfl QFLORL Summers my E46- L. E. FLORY ET AL ELECTRONIC COMPUTING DEVICE Filed Jan. 2l, 1943 f5 Sheets-Sheet 5 m Tm, R n nu n .L G MF AFE E E E E. R lm( 32:4 E Ew; VEL

Psrented July 1s, i946 2,404,047 ELECTRONIC COMPUTING DEVICE Leslie E. Flory and George A. Morton, Princeton,

N. J., assignors to 7 claims. 1

This invention relates generally to electronic computers and particularly to electronic apparatus for counting voltage pulses, and for deriving the product, or solving quadratic functions of quantities represented by groups of such pulses.

The basic circuit utilized in adapting the invention to the various circuits to be described is the well known trigger circuit of the general type described in Theory and Application of Vacuum Tubes," by Herbert J. Reich. In one of its simplest forms, this trigger circuit includes two triodes in which the grid of the first triode is coupled to the anode of the second triode through a network comprising a parallel connected resistor and capacitor, and the grid of the second triode is similarly coupled to the anode of the first triode through a similar coupling network. The cathodes of both triodes are grounded, either directly, or through suitable cathode resistors. Grid and anode potentials are applied to the respective electrodes through separate resistors. If desired, a gaseous discharge tube may be connected across one of the anode resistors to indicate circuit operation.

In operation, if a negative voltage is applied to the grid of the first triode, the anode current of the triode will be reduced and the anode potential will become more positive. Due to the connection through the coupling resistor, the grid potential of the second triode will become more positive, causing an increase in the anode-current of the second triode, with a resultant decrease in the second triode anode potential. This decrease in anode potential will, in turn, cause the grid potential of the first triode to become more negative. This action will continue until the anode current of the iirst triode is cut off. The first triode will remain cut off, and the second triode will remain conducting, until a positive potential is applied to the grid of the first triode or a negative potential is applied to the grid of the second triode.v In either latter instance, the tube operating conditions will be reversed and the first triode will become conducting and the anode current of the second triode will be cut ofi.

One of the features of the instant invention is the utilization of such trigger circuits in cascade arrangement, whereby a predetermined change in the polarization or activization of one triode of the trigger circuit will generate a pulse to trigger or activate a succeeding trigger circuit in the cascade arrangement. As many trigger circuits as desired may be connected in cascade. The in- Radio Corporation of America, a corporatlonof Delaware Application January 21, 1943, serial No. 413,146

` along a counter comprising a stant invention is an improvement on the copending U, S. application of Leslie E, Flory, Serial No. 467,229, iiled November 28, 1942, which describes a device for multiplying two or more binary numbers.

In the copending application, multiplication is accomplished by deriving the binary sum of a binary multiplicand added tothe same multiplicand once for each occurrence of a binary l in the multiplier, and in which successively added numbers are stepped along one step on. the intermediate product for each term in the multiplier.

The binary system of computation is particularly suited to electronic .computers since a complete binary term of a binary number may be expressed in terms of the conducting or cut-off condition oi the anode circuit of a conventional vacuum tube. vA saving in the number of tubes required for a given number is also possible in a ratio of 3 to 1 over a numerical system utilizing a radix of l0. A description of the binary system of computation may be found in Elementary Number` Theory, by Uspenski and Heaslet.

In order to operate a counter utilizing the binary system, it is necessary to adapt the conventional trigger circuit described heretofore to effect a reversal in polarization or activization by succeeding applied pulses of a similar nature. Some of the circuits, described hereinafter, are adapted to this purpose by applyingin a symmetrical manner negative operating pulses to the anode circuits of the trigger tubes. Other trigger circuits utilized herein include grid resistors of different values in the two tubes of the trigger circuit. When a control pulse or potential is applied to the symmetrical point in the trigger circuit anode circuit, temporary unbalance occurs, the polarization of the trigger tubes is reversed, and then, after some predetermined time interval, the trigger circuit returns to its original stable condition. The instant invention utilizes slideback" trigger circuits of this typefor stepping the product along a product counter which comprises a plurality of symmetrical 'trigger circuits of the type rst described. Ilie fslideback trigger circuits also provide the carryover pulses to the next succeeding product trigger circuits as the individual product terms change from binary l to binary 0.

Among the objects of the invention are to provide a new and improved means for counting voltage pulses. Another object is to provide a new and improved means for stepping a number plurality of trigger circuits. Another object of the invention is to provide improved means for utilizing trigger circuits in a novel cascade arrangement for deriving the product of quantities represented by the numbers of pulses in successive series of voltage pulses. Still another object is to provide an improved means for connecting trigger circuits in cascade arrangement to provide a continuous counter. A further object is to provide improved means for clearing the counter after each operation thereof, for conditioning the circuit for counting succeeding applied pulses. Another object is to provide a new and improved means for deriving the bi- 3 nary product of successive series of pulses applied to a thermionic tube trigger circuit. Still another object is to provide a new and improved means for deriving the binary product of the lbinary sums of succeeding series of voltage pulses wherein the multiplicand and multiplier are applied as binary numbers to separate series of cascaded trigger circuits. Another object is to provide new and improved means for generating a predetermined number of voltage pulses in response to a single actuation of said means.

The invention will be described by reference to the accompanying drawings of which Fig. 1 is a schematic circuit diagram of a trigger circuit which forms part of the computer; Fig. 2 is a block circuit diagram of the invention; Fig. 3 is a partial schematic circuit diagram of the invention; Fig. 4 is a graph showing a typical multiplier pulse train utilized in one embodiment thereof; Fig. 5 is a block diagram' of a stepping pulse circuit; and Fig. 6 is a schematic circuit diagram of a preferred embodiment of the circuit of Fig. 5. Similar reference numerals are applied to similar elements throughout the draw- 1118s'.

Referring to the drawings, Figure 1 comprises a trigger circuit of the general type described heretofore. The grid al of a ilrst triode I is connected to the anode p2 o1' a second triode 2 through a network comprising the parallel connected resistor 3 and capacitor 4. 'I'he anode pI of the nrst triode I is connected to the grid g2 of the second triode 2 through a second network comprising the parallel connected resistor 5 and capacitor 6. The cathodes of the rst and second triodes. I, 2 are grounded. A source of negative bias potential c is connected to the grid gI of the rst tube I through a grid resistor 1, and to the grid g2 of the second triode 2 through a second grid resistor 8. The positive terminal oi the bias source c is grounded. Anode potential from a source B is applied to the anode pI of the ilrst tube I through an anode coupling resistor 9, and to the -anode p2 of the second tube 2 through a second anode coupling resistor I0. The negative terminal of the anode potential source B is grounded. A gaseous indicator tube I3, which may be a conventional neon tube, is connected across the second anode resistor I to indicate when the anode current exceeds a predetermined value, characteristic of the anode current conducting condition of the second tube 2. A choking resistor I4 is connected in series with the positive anode power supply lead to the common terminals of the anode resistors 9 and III. Negative input control pulses are applied to the input terminals I between ground and the common terminal of the anode resistors 9 and I0. through an input coupling capacitor I6. Any other desired input coupling arrangement may be utilized to equal advantage.

In operation, if it is assumed that the ilrst tube I initially is drawing anode current. the second tube 2 will be biased off. A negative pulse applied to the input terminals I5, will appear on the anode p2 of the tube 2 and on the grid gl of the first tube I which will in turn make the potential on the anode pI of the rst tube I more positive, and degenerate simultaneously any of the original negative pulse applied at pI. A positive pulse will be applied to the grid g2 of the tube 2 causing the tube 2 to become conducting. This eect will increase and continue, because of the difference in the potential charges on the capacitors 4 and 8, until the first tube I is olli? Oil',

and the second tube 2 becomes completely conducting. A subsequent negative pulse applied to the input terminals I5 will cause the stable conditions of the trigger tubes I, 2 to 'be reversed since the circuit is completely symmetrical.

The indicator tube I3 will be illuminated when the second tube 2 is conducting, since only under this condition is there an appreciable voltage drop across the anode coupling resistor I0. If it is assumed that the conducting condition of the first tube pI represents zero, and the conducting condition oi the second tube 2 represents I, the result is a binary counter in which zero is indicated on the indicator tube I3 when the tube is extinguished, and I is indicated when the tube is illuminated. The second pulse applied to the input terminals I5 will cut of! the second trigger .tube 2 and cause the ilrst tube I to again become conducting. In order to indicate that two pulses have occurred instead oi' none, it is essential that a carryover system be employed which will provide a second indication representative of the second term of the binary total. This feature will be described hereinafter in connection with the totalizer circuit included in Figs. 2 and 3. If a carryover circuit is desired for the multiplicand set-up device. it may be of the type described in the copending application mentioned heretofore. However, to simplify the present description, it is assumed that a binary multiplicand is directly set up on the multiplicand set-up device. through the separate input terminals I5, I5', I5", I5'" of Fig. 2.

Figure 2 comprises a block diagram of an electronic multiplying system wherein a multiplicand is set up as a binary number on a series of trigger circuits of the general type described heretofore. 'I'he binary multiplicand is then transferred to a second binary counter upon which the binary product is to be established. The circuits to be described hereinafter accomplish both the direct transfer of the multiplicand to the totalizer and the carryover operation required as each element of the totalizer changes from one to zero in the binary system.

Each of the trigger circuits I, II, III, and IV, oi' the multiplicand set-up device is connected to a corresponding transfer amplifier 30, 3|, 32 and 33, respectively, in such a manner that when the counter trigger circuit is in the binary zero condition, the amplifier tube is beyond cutoff or inoperative, and when the counter is in the binary I condition, the corresponding amplifier is biased to the anode current cutoi condition. Pulses or potentials corresponding to the binary multiplicand, are applied, as described heretofore. to the input terminals I5, I5', I5", I5"' of the multiplicand binary set-up device to establish the multiplicand thereon as a binary quantity on the trigger circuits I, II, IlI and IV. Pulses 49, 50, which correspond to the presence of binary I terms of the kbinary multiplier are successively applied simultaneously to al1 of the respectiveV grid circuits oi' the transfer amplifiers 30, 3|, 32 and 33. Means for deriving the pulses 49, 5II from a binary multiplier will be described hereinafter. The multiplier pulses will therefore be transmitted by only the transfer amplifiers which are connected to the corresponding multiplicand trigger circuits which are in the binary I condition.

The pulses transmitted by the respective trans-y fer amplifiers are next applied directly to the trigger circuits XV. XVI, XVII and XVIII, respectively, of the totalizer which includes the trigger circuits XI, XII, XIII, XIV, XV XVI, XVII and XVIII, which are also of the type ilrst described in Fig. 1. The number of trigger circuits required in the totalizer will be at least one more than the sum of the number of binary terms in the multiplicand and multiplier, respectively. The precise number of trigger circuits will depend upon the particular multiplication process which the circuit is required to perform. Indicator lamps may be connected in the anode circuits of the individual trigger circuits of the product counter in the same manner as described heretofore in Figure 1 for the individual trigger circuits of the multiplicand set-up device. Likewise, the anode circuits of the totalizer may be connected to apply the binary product directly to other utilization circuits.

The product carryover operation, necessary when a product term changes from binary I to binary 0; and the product shifting which is necessary after each term of the multiplier is applied to the circuit, are accomplished, as mentioned heretofore. by slideback type trigger circuits 40, 4I, 42, 43, 44, 45 and 46. One of these slideback circuits is connected between each of the product trigger circuits XI, XII, XIII, XIV, XV, XVI, XVII and XVIII.

The essential difference between the slideback or carry-over trigger circuits and the `multiplicand and product trigger circuits described in Fig. 1, is that in the slideback" circuit the grid resistor 8 has considerably higher resistance than the grid resistor 1, whereby an applied input pulse effects a change in circuit polarization for a predetermined time interval. such as for example, ve microseconds, and then the circuit resumes its original stable condition. The time interval will be determined by the values of the circuit components. In either type of trigger circuit the input control pulses may be applied to grid circuits instead of to the symmetrical point of the anode circuits, to provide more positive operation.

The carryover trigger circuits sequentially perform both product carryover and product stepping operations as the multiplier pulses are applied to the circuit. Two methods of setting up the multiplier and applying the multiplier pulses to the circuit are:

Method I If the multiplier is available as a pulse train having low amplitude pulses corresponding to binary 0 terms and relatively high amplitude pulses corresponding to binary I terms, this pulse train may be utilized to accomplish the transfer of the multiplicand to the totalizer, and also the carryover and shifting operations in the product counter during the intervals between the application of successive terms, or pulses, of the multiplier to the circuit. Such a pulse trainl is illustrated in Fig. 4 by the graph 4'I, in which .the highest term of the binary multiplier corresponds to the first large pulse 49, and successive multiplier terms are represented by the pulses 48 and 50. The pulse train may be derived from an electronic switch of the,general type described in the copending application heretofore mentioned, by applying different potentials, corresponding to binary I) and binary I terms of the multiplier, to separate target electrodes which are sequentially scanned once by the electron beam from an electron gun.

The pulse train 41 is applied to the multiplier input terminals 54 which are connected to the input circuits of a limiter-phase inverter circuit 5I and a delay circuit 52. The limiter circuit 5I clips the amplitude of all of the multiplier pulses to equal amplitudes, and reverses their polarity, as indicated by the pulses 49', 48 and 50. These equal amplitude pulses are connected to all of the product trigger circuits, through the switch s2, by means of the lead a. The pulses transmitted by the delay circuit 52 are'` applied to the input of a peak amplier 53, which amplifies only the peaks of pulses having greater amplitudes than the pulse 48, which corresponds to a binary zero in the multiplier pulse train. The

peak pulses 49 and 50 are connected to the common input circuits of the transfer amplifiers 30. 3|, 32 and 33 by means of the lead b. It will therefore be seen that pulses for each term of the Ibinary multiplier will be applied to the totalizer trigger circuits, while pulses corresponding to only binary I terms of the multiplier will be applied to key the input circuits of the transfer amplifiers 30, 3l, 32 and 33 for transferring the multiplicand from the set-up trigger circuits I, II, III and, IV to the corresponding portion of the totalizer counter which includes the trigger circuits XV, XVI, XVII and XVIII.

Each time the product trigger circuit XVIII changes from binary I to binary zero, a pulse is applied to key the carryover trigger circuit 46, which is of the slideback type. The carryover trigger circuit 46, in turn, delivers' a keying pulse to the next product trigger circuit XVII which changes its polarization by one binary value. Similar operation, occurs between the totalizer trigger circuit XVII and the next totalizer circuit XVI because of the action of the next interconnected carryover trigger circuit 45 and the remaining carryover trigger circuits 40, 4I, 42, 43 and 44 operate similarly on the remaining totalizer trigger circuits XI, XII, XIII, XIV and XV. Therefore, if a pulse is aplied to the product trigger circuit XVIII such as always to change its polarization to correspond to binary zero. a binary I will be transferred to the next product trigger circuit XVII if the'trigger circuit XVIII was orig inally in a binary I condition, but if the circuit XVIII was originally in a binary zero condition, no transfer pulse will be transmitted to the totalizer trigger circuit XVII. The effect of this circuit operation is to shift the binary product one position to the left for each application of a multiplier pulse to the line a which is connected directly to each of the product trigger circuits, since this pulse initially changes all of these circuits to binary zero and then transfers any binary I terms to the next succeeding trigger circuit by means of the carryover circuits 40 to 46, inclusive.

The pulse train 41 is delayed an amount equal to approximately half the time interval between the successive pulses 49, 48 and 50 of the train 4'I by means of the delay circuit 52. The pulse peaks 49 and 59 amplified by the peak amplifier 53 are thence applied through the lead b to key the transfer amplifier 3U, 3|, 32 and 33 to transfer the binary multiplicand from the multiplicand set`up device to the trigger circuits XV, XVI, XVII and XVIII of the totalizer. It will -be seen that the multiplicand will be transferred to the totalizer once for each pulse on the line b while the intermediate product will be stepped one position to the left for each of the shifting pulses 49', 48, 50' on the line a. The nal product will appear on the totalizer after all shifting and transfer pulses have been transmitted1 -by`the A second method of applying the binary mul-l tiplier to the circuit described heretofore is to establish directly the binary multiplier on the totalizer trigger circuits XI, XII, and XIII in the same manner as the multiplicand is established on the multiplicand set-up device which includes the trigger circuits I, II, III and IV. If now a predetermined number of keying pulses are applied to the line a, by connecting the movable element of the switch s2 to the xed switch contact 54a, the binary multiplier will be stepped ofi' the last product trigger circuit 1U.

Pulses derived from the trigger circuit XI are applied to the input of a second delay circuit 62, each time the circuit is in the binary I condition. These derived binary i pulses are then applied to key the transfer ampliers 3D, 3l, 32

and 33, when the switch si is closed to connect the delay circuit thereto. Thus. as the binary multiplier is stepped oil the totalizer, the multiplicand is transferred to the totalizer foreach binary i term in the multiplier and the successively transferred multiplicand quantities are added to the intermediate product as the product is stepped along the product counter for each term of the multiplier, irrespective-of the -binary value of that term.

This rarrangement also permits the evaluation of quadratic expressions, such as a+(b+c.r) z, by applying the multiplier a second time to the product counter and repeating the multiplication process just described. As a result of the thus repeated multiplication process, the square of the multiplicand will be multiplied by the multiplier, and the nal product will be indicated directly on the totalizer. To simplify the circuit design, the intermediate products should preferably be added on a separate counter, not shown.

.Any well known means of providing the desired number of stepping pulses may be utilized for stepping the binary multiplier oif the product counter. For example, a desired number oi' pulses corresponding to the number of terms in the multiplier may be applied to a modied linear electronic counter of the cathode ray type described in the copending U. S. application of applicants, Serial No. 456,012, filed August 25, 1942. Then the linear counter may be uncounted" to deliver the required number of stepping pulses in rapid succession. Similarly, an electronic switch,

of the type described heretofore, may be utilized,

except that a limiter or clipping circuit should preferably be inserted between the switch and the line a to provide similar amplitude stepping pulses for binary terms of all values.

Figure 3 is a schematic circuit diagram of that tablished on the various multiplicand trigger circuits in the` manner described in the copending application to which referencehas previously been made. Positivepulses on the lead b corresponding to binary i terms of the multiplier are applied through' the capacitor-s 63 and Se to the control electrodes of the transfer 'ampliers 32 and 33. respectively. A Ibias potential is derived from the cathode of the second tube of the trigger circuit III and applied through a grid resistor to the control electrode of the transfer amplifier 32. A second bias potential is derived from the cathode of the second tube of the trigger circuit IV and applied through a second grid resistor B8 to the control electrode of the transfer amplifier 33.

The anode of the transfer amplifier 32 is coni nected to the symmetrical point 81 of the anode circuits of the trigger tubes of the totalizer trisger circuit XVII. The anode of the transfer amplifier 33 is similarly connected to the symmetrical point 68 of the anode circuits of the tubes of the totalizer trigger circuit XVIII.

The anode of the second tube of the totalizer trigger circuit XVII is connected through a capacitor 69 and a resistor 10 to the control electrode of the second tube of the carryover transfer trigger circuit 45. Similarly, the anode of the second tube of the totalizer trigger circuit XVIII is connected through a capacitor 1I and a resistor 12 to the control electrode of the second tube of the carryover trigger circuit 48. The anode of the second tube of the carryover trigger circuit 46 is connected through a coupling capacitor 13 to the symmetrical point in the anode circuits of the totalizer trigger circuit XVII. Similarly, the anode of the second tube of the carryover trigger circuit 45 is connected to the symmetrical point in the anode circuits of the next succeeding totalizer trigger circuit XVI, not shown.

Negative stepping pulses, derived as described heretofore, or in the manner of Figs. 5 and 6. are applied through a capacitor 14 and an isolating resistor 18 to the control electrode of the first tube of the totalizer trigger circuit XVII. Similarly, the negative stepping pulses `are applied through a capacitor 15 and an isolating resistor 11 to the control electrode of the first tube of the totalizer trigger circuit XVIII. It should be kunderstood that the multiplicand set-up device trigger circuits III and IV, and the totalizer trigger circuits XVII and XVIII are of the herein rst described type which utilizes symmetrical control electrode circuits having substantially equal values of grid resistance. The carryover trigger circuits 45 and 46 differ from the multiplicand and product trigger circuits only in that the grid circuits are unsymmetrical, since they include grid resistors of different values to provide the slideback operation described heretofore, and the control pulses are applied to the grid circuits instead of to the symmetrical points in the anode circuits.

It should be understood that the speciiic methods of coupling the various trigger circuits and transfer amplifiers may be varied according to vaccepted engineering practice, providing the proper'voltage and phase requirements are maintained. While some of the trigger circuits described herein utilize triodes, it should also be understood that multi-grid tubes may be employed throughout to advantage, since the additional gain, of such tubes may be desirable from the standpoints of stability and tolerances of the trigger circuit components.

Figure provides a general means for deriving a predetermined number of stepping pulses in rapid succession upon application thereto of an initial starting voltage.

A source of oscillations 88, of waveform 8l, is connected through a pulse shaping circuit 82 to provide sharply defined negative pulses 83. These negative pulses are then applied simultaneously, through a switch s4, to a delay circuit 84 and a-switching circuit 85, such as a multivibrator. The switching circuit, in response to the initial negative pulse applied thereto, provides a positive bias potential to unblock an amplifier 86. After the amplifier 88 is unblocked, the delayed pulses are also applied to the amplifler input circuit. The output circuit of the ampliiler is next applied to an electronic counter 81, which may be of the general type described in the copending U. S. application of Leslie E. Flory, Serial No. 467,032, filed November 28, 1942, in which any predetermined number of pulses applied thereto will provide a control potential when the counter is lled. When the desired number of pulses are counted, the control potential derived from the counter is applied to the amplifier to bias off the amplifier anode current.

Thus a predetermined number of pulses may be delivered to a load circuit connected to the amplier output circuit. 'Ihe number of pulses may be controlled by changing the electronic counter as described in the copending Flory application. The circuit may be cleared for a succeeding operation by disconnecting, or stopping the oscillation source, and by returning the counter to its initial operating condition.

Figure 6 provides a specific circuit for the operation generally described in Fig. 5. The oscillator 80 is of the conventional R.C. type. Its output circuit is connected through the conventional pulse shaping circuit 82 to provide the discrete negative pulses 83. The negative pulses are then simultaneously applied to key the switching multivibrator 85 which is a symmetrical trigger circuit of the type described heretofore, and to key the slideback trigger circuit 84 which provides the required delay for the pulses applied to the second control electrode of the amplifier tube 88. A positive bias potential is derived from the cathode circuit of the switching multivibrator 85, in response to actuation thereof by the initial negative pulse, and is applied to the rst control electrode of the amplifier tube 86 to unblock the tube for amplification of the delayed pulses. The anode circuit of the amplifier 86 is connected to the electronic counter 8l which includes the trigger circuits 88, 89, 80, 9|, 92 connected to provide a control potential when a predetermined number of pulses have been counted. In the particular circuit disclosed, operation of the switch s3 will provide a control pulse for either six or fourteen applied pulses from the amplifier 86. The control potential is derived from the movable element of the switch s3 and applied to the first control electrode of the amplier 8G to block the tube anode current. The number of pulses required for the control potential depends upon the particular trigger circuit connected to the movable element of the switch s3. The predetermined number of pulses are then derived from the amplifier anode circuit and applied as stepping pulses to the product counter of the circuit described in Fig. 2.

The pulse generator may be cleared by opening the switches s4 and s5. Opening the switch s4 removes the source of oscillations from the countl0 ing circuit, while opening the switch si changes the bias on all trigger circuits of the electronic counter, to restore the counter to any predetermined initial count. It should be understood that the essential difference between the counter of Fig. 6 and the counter circuit disclosed in the copending Flory U. S. application referred to heretofore, is that in the instant device the initial count is provided by reversed bias means in one or more predetermined trigger circuits, (in this instance, trigger circuit 89) while feedback means are provided in the copending application.

All trigger circuits may be cleared, after each multiplying operation is completed, by applying a high negative control electrode bias simultaneously to all binary I tubes in the manner which is described, for example, in the copending application mentioned heretofore, or by removing the grid bias from the binary 0 tubes.

Thus the invention described comprises an electronic multiplying device in which a multiplicand is applied to a binary set-up device, and transferred to totalizer a number of timesY corresponding to the occurrence of binary I terms in the multiplier, while simultaneously the intermediate product is shifting a number of times equal to the number of terms in the multiplier. Provision may be made in both the multiplicand set-up device and totalizer to accomplish carryover operations where required, and to segregate the carryover operations from the direct applications of the multiplicand to the product counter.

It should be understood that the particular circuits described are merely illustrative of one means for accomplishing the invention. Many of the individual circuits may be modified, and the coupling and control circuits varied in accordance with accepted engineering practice, without deviating from the spirit and scope of the invention.

We claim as our invention:

l. A binary multiplying device for two quantities including a first binary counter circuit having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a second `binary counter circuit having a plurality of trigger circuits, means for transferring said multiplicand to said second counter, means for repeating said transfer a number of times corresponding to the occurrence of binary I terms in said other quantity as a multiplier, means including a plurality of normally stable trigger circuits each adapted to polarization reversals for predetermined small time intervals for shifting the count on said second counter circuit one binary place a number of times corresponding to the number of binary terms in said multiplier, and means including said second counter and said normally stable trigger circuits for deriving the binary sum of said repeated multiplicands.

2. A binary multiplying device including a plurality of cascaded trigger circuits, means for polarizing said trigger circuits to represent a binary multiplicand, a first source of pulses the number of which is representative of the number of binary terms of a multiplier, a second source of pulses the number and occurrence of which correspond to binary I terms of said multiplier, a plurality of transfer amplifiers, means including predetermined polarization of said trigger circuits for unblocking predetermined ones of said-amplifiers, a plurality of second trigger circuits, means for applying said second pulses to all of saidampiifiers for transferring said multiplicand to predetermined ones of said second trigger circuits for each occurrence of said second pulses, means including a plurality of normally stable trigger circuits each adapted to polarization reversals for predetermined small time intervals, means for applying said first pulses to shirt the count on said second trigger circuits one binary place a number of times corresponding to the number of binary terms in said multiplier, and means including said second trigger circuits and said normally stable trigger circuits for deriving the binary sum of said repeated multiplicands.

3. A binary multiplying device for two quantities including a rst binary counter circuit having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a, second binary counter circuit having a plurality o1 trigger circuits, a plurality of blocking amplifiers, means interposing one of said amplifiers between corresponding trigger circuits of said first and said second counters, means including said first counter for unblocking said amplifiers for transferring -said multiplicand to said second counter to derive a product thereon, means for repeating said transfer a number of times corresponding to the occurrence of binary 1 terms in said other quantity as a multiplier, means including a plurality of normally stable trigger circuits each adapted to polarization reversals for predetermined small time intervals for shifting said product on said second counter a number of times corresponding to the number of binary terms in said multiplier, and means including said second counter and said normally stable trigger circuits for deriving the binary sum of said repeated multiplicands.

4. A binary multiplying device for two quantities including a rst binary counter circuit having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a second binary counter circuit having a plurality of trigger circuits. a plurality of blocking ampliiiers, means interposing one of said ampliers between corresponding trigger circuits of said iirst and said second counters, means including said iirst counter for unblocking said amplifiers for transferring said multiplicand to said second counter to establish a product thereon, means for repeating said transfer a number of times corresponding to the occurrence of binary l terms in said other quantity as a multiplier, a plurality of normally stable trigger circuits each adapted to polarization reversals for predetermined small time intervals, means including said normally stable trigger circuits for shifting said product on said second counter a number of times corresponding to the number of binary terms in said multiplier, and means including said normally stable trigger circuits responsive to predetermined polarization of each of said trigger circuits of said second counter for changing the polariaztion of succeeding trigger circuits ofsaid second counter for deriving the binary sum of said repeated multiplicands and said shifted products.

5. A binary multiplying device for two quantities including a iirst binary counter circuitr having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a second binary counter circult having a plurality of trigger circuits. a plurality of blocking amplifiers, means interposing one of said ampliiiers between corresponding trigger circuits of said nrst and said second counters, means including said first counter for unblocking said ampliiiers for transferring said multiplicand to said second counter to establish a product thereon, a source of pulses ci substantially square wave form, means for applying saidl pulses to all o1' said blocking ampliiiers, means including a predetermined number of said pulses for repeating said transfer a number 0f times corresponding to the occurrence of binary l terms in said other quantity as a multiplier, a, plurality of normally stable trigger circuits each adapted to polarization reversals for predetermined small time intervals, means including said normally stable trigger circuits for shifting said product on said second counter a number of times corresponding to the number of binary terms in said multiplier, and means including said normally stable trigger circuits responsive to predetermined polarization of each of said trigger circuits of said second counter for changing the polarization o! succeeding trigger circuits of said second counter for deriving the binary sum of said repeated multiplicands and said shift ed products.

6. The combination of iirst and second groups of trigger circuits each operable to either of two stable conditions, a third group of trigger circuits each operable to stable and unstable oper ating conditions, means interconnecting each trigger circuit of said ilrst group with a different trigger circuit of said second group for transmitting an electrical pulse to the trigger circuit of said second group only when the trigger circuit of said first group is in a predetermined one of said stable conditions, and means connecting each trigger circuit of said third group between a different pair of the trigger circuits of said f second group for transmitting an electrical pulse from a first to a second trigger circuit of said second group only when a pulseis applied to said ilrst trigger circuit while it is in a predetermined one of said stable conditions.

7. The combination of iirst and second groupsy of trigger circuits each operable to either of two stable conditions, a third group of trigger circuits each operable to stable and unstable operating conditions, means interconnecting each trigger circuit of said first group with a different trigger circuit of said second group for transmitting an electrical pulse to the trigger circuit of said second group only when the trigger circuit of said first group is in a predetermined one of said stable conditions, means connecting each trigger circuit of said third group between a different pair ofthe trigger circuits of said second ygroup for transmitting an electrical pulse from a ilrst to a second trigger circuit of said second group only when a pulse is applied to said iirst trigger circuit while it is in a predetermined one of said stable conditions, means for applying stepping pulses to the trigger circuits of said second group, and means for applying to said interconnecting means signal pulses having a predetermined relation to said stepping pulses.

LESLIE E. FLORY. GEORGE A. MORTON.

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