CN1964593B - A system to acquire and control data for radiation imaging - Google Patents
A system to acquire and control data for radiation imaging Download PDFInfo
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- CN1964593B CN1964593B CN 200510086817 CN200510086817A CN1964593B CN 1964593 B CN1964593 B CN 1964593B CN 200510086817 CN200510086817 CN 200510086817 CN 200510086817 A CN200510086817 A CN 200510086817A CN 1964593 B CN1964593 B CN 1964593B
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Abstract
The related data acquisition and control system for radiation imaging comprises: an image checkup subsystem, an accelerator, a module circuit for digital detector, the Ethernet, and a module circuit for data acquisition and control. Wherein, the last module circuit includes a differential circuit, a buffer circuit, a generation circuit for data storage and control time sequence, a data storage circuit, a network SCM, an accelerator CP isolation drive circuit, a process circuit for accelerator beam strength information, and a constant voltage power circuit.
Description
Technical field
The present invention relates to the radiation checking technical field, be specifically related to a kind of data of utilizing and obtain the system that controls detector in the radiant image with the control module circuit.
Background technology
Parts such as radiation image-forming system comprises that radiographic source, detector, data are obtained and control, image inspection, machinery are automatically controlled, safety interlocking.The prior art detector module is output as simulating signal, and the control corresponding system also adopts simulating signal, the obtaining and transmit inconvenience of its signal poor anti jamming capability, system architecture complexity, data.The appearance of technical progress and new digitizing chip, the detector module digitizing can be finished cheaply, and the use of digital detector module obtains with control module to come it is controlled with regard to the corresponding data of needs.So needing the new data of development obtains and control module.
Summary of the invention
(1) technical matters that will solve
The purpose of this invention is to provide that a kind of signal antijamming capability is strong, simple in structure, the obtaining and transmit the system that radiant image easily obtains and controls with data of data.
(2) technical scheme
In order to achieve the above object, the present invention takes following technical scheme:
Comprise image inspection subsystem, being used to obtain data obtains and the data-signal of control module circuit output and the image that is converted into convenient demonstration and checks, show in the image inspection post, obtain with the control module circuit by signal hop and data detector be connected, and control data obtain with the control module circuit to detector and accelerator; Data are obtained with the control module circuit and are linked to each other with digital detector module circuit with control signal and power lead by data, check that by Ethernet and image subsystem links to each other, and transmitted beam intensity of flow signal wire links to each other with accelerator with the synchronous triggering signal line; Accelerator is used to produce the required x ray signal of imaging; Digital detector module circuit, can be a plurality of modules form arrays, be used for that signal to detector or detector array output amplifies, AD changes, and be converted into the convenient RS485 differential signal that transmits, the RS485 differential signal is generated by the RS485 difference channel; The signal hop is used for transmission of digital signals.
Wherein, described data are obtained and the control module circuit, comprising:
---data and control signal difference channel are used to finish reception or transmission to the data and the control signal of digital detector modular circuit;
---data and control signal buffer circuit, the shaping and the driving that are used to finish data and control signal strengthen;
---data storage and control timing produce circuit, are used to finish to the string and the conversion of input data and produce corresponding storage signal, sequential, the control data memory circuit; Finish required signal, the sequential of digital detector modular circuit control; Produce the required synchronizing pulse of accelerator; Finish mutual control, receive the order that network and singlechip computer sends, produce the required synchronous triggering pulse of accelerator, receive the accelerator intensity signal and be sent to network and singlechip computer network and singlechip computer and data storage circuitry;
---data storage circuitry, the data that convert through the programming device in data storage and the control timing generation circuit are stored, and the data of storage are delivered to network and singlechip computer;
---network and singlechip computer, be used for receiving picture check subsystem command signal by Ethernet, and be sent to data storage and control timing and produce programming device in the circuit, receive the data of the dual port RAM storer in the data storage circuitry and data are delivered to the picture check system with the form of Ethernet;
---accelerator synchronizing pulse isolated drive circuit is used to finish the isolation drive of accelerator synchronizing pulse;
---the accelerator intensity information-processing circuit, be used for finishing to the simulating signal of expression accelerator intensity follow, modulus changes and data-signal is delivered to the programming device that data storage and control timing produce circuit handle;
---voltage-stabilized power supply circuit is used to provide direct supply.
Wherein, in the system that described radiant image obtains and controls with data, the signal hop is an Ethernet.
Wherein, described data and control signal difference channel comprise some difference chips, and the difference chip can be controlled several digital geochemical exploration simultaneously and survey the device module.
Wherein, described data storage and control timing produce circuit and comprise programming device U2, offer the chip U19 of programming device U2 configuration information, the clock Z1 that shakes, filter capacitor C21-C37, pull-up resistor R4-R7, wherein, model is the data signal line D0L-D7L of the programming device U2 of EP1K30, address signal line A0L-A13L, read-write control line, address signal line A0R-A13R and output enable line OER link to each other with data storage circuitry, the pin CLK1 of programming device U2, CONV1, DXMIT1, DVALID1, DCLK1, DIN1, TEST1, ACC1 links to each other with the control signal buffer circuit with data, the pin TMS of programming device U2, TD, DATA0 links to each other with the chip U19 of configuration information, the TCK of programming device U2, TDO, TMS, the TDI signal can make programming device be configured by outside line, the control signal wire REG0-REG7 of programming device U2, INT, RD, RET, DSEL is connected to network and singlechip computer, the pin SDO of programming device U2, SCK, CNV links to each other with the accelerator intensity information-processing circuit, obtains beam intensity information.
Wherein, accelerator synchronizing pulse isolated drive circuit comprises insulating power supply chip U21, photoelectricity coupling chip U12, pull-up resistor, filter capacitor, wherein, power supply is isolated by insulating power supply chip U21, synchronous triggering signal ACC isolates by photoelectricity coupling chip U12, selects suitable output current by pull-up resistor, offers accelerator and data and obtains the synchronous triggering pulse signal of isolating fully with the control module circuit.
Wherein, described accelerator intensity information-processing circuit comprises operational amplifier U16, analog to digital converter U17, the chip U15 of reference voltage, the capacitor C 38-C48 that strobes, resistance R 9, R10 is provided, wherein, the input end of operational amplifier U16 receives the analog level signal of representing accelerator intensity from accelerator, model is that pin SCK, SDO, the CNV of the analog to digital converter U17 of AD7685 links to each other with programming device U2, and intensity digital signal after the AD conversion is delivered to programming device U2.
(3) beneficial effect
1) owing to take above scheme, data and control are imported, are output as differential signal, have improved antijamming capability greatly, and can transmit at a distance; 2) owing to select the difference connected mode for use, a transmitter can be with and carry 128 or more receiver, makes things convenient for data to obtain with the control module circuit and controls tens detector modules simultaneously; 3) owing to use the dual port RAM storer, solved the single-chip microcomputer reading of data and write the different conflicts that cause of data speed with programming device, as when programming device deposits the first row detector module assigned address 1 of dual port RAM in, single-chip microcomputer can read the data that deposit dual port RAM assigned address 2 in simultaneously; 4) accelerator is a heavy current installation, owing to adopt accelerator synchronizing pulse isolated drive circuit, reduces the electromagnetic interference (EMI) between accelerator and this module greatly; 5) owing to adopt network and singlechip computer, very easily data-signal is transported to image with the form of Ethernet and checks subsystem, convenient these data are obtained with the control module circuit controlled; 6) owing to adopt programming device, finish the generation of various control signals, sequential easily and data-signal is gone here and there and transformed and store, simplified circuit greatly.
Description of drawings
Fig. 1 is a principle of work block diagram of the present invention;
Fig. 2 is data and control signal RS485 difference channel figure;
Fig. 3 is data and control signal buffer circuit figure;
Fig. 4 is that data storage and control timing produce circuit diagram;
Fig. 5 is data storage circuitry figure;
Fig. 6 is the network and singlechip computer circuit diagram;
Fig. 7 is accelerator synchronizing pulse isolated drive circuit figure;
Fig. 8 is accelerator intensity information-processing circuit figure;
Fig. 9 is voltage-stabilized power supply circuit figure;
Figure 10 is a use block diagram of the present invention.
Among the figure: U1-U15, U17-U21, integrated chip; U16, operational amplifier; C1-C61, electric capacity; R1-R13, resistance; L1, inductance; L2, ferrite; F1, the fuse of can resetting; D0L-D7L, TMS, TD, DATA0, TCK, TDO, TDI, SDO), SCK, CN V, data signal line; A0L-A13L, A0R-A13R, address signal line; OER, output enable line; CLK1, CONV1, DXMIT1, DVALID1, DCLK1, DIN1, TEST1, ACC1, data or control signal wire; R/WL, CEL, OEL, SEML, SEMR, R/WR, M/S, CER, data signal line; RD, INT, RET, DSEL, control signal wire; ACC, synchronous triggering signal; DGND1, ground connection; SCK, SDO, CNV, data signal line; The analog level signal of VACC, accelerator intensity; FPGA, programming device U2; 1, network and singlechip computer; 2, data storage and control timing produce circuit; 3, data and control signal buffer circuit; 4, data and control signal RS485 difference channel; 5, accelerator synchronizing pulse isolated drive circuit; 6, data storage circuitry; 7, accelerator intensity information-processing circuit; 8, voltage-stabilized power supply circuit; 9, data are obtained and the control module circuit; 10, image is checked subsystem; 11, accelerator; 12, low-tension supply; 13, digital detector module circuit.
Embodiment
Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
Referring to Fig. 1 and Figure 10, realize that circuit of the present invention comprises: the RS485 data of pick-up probe signal and reception or transmission and control signal difference channel 4, the data and the control signal that receive or send are carried out shaping and driven the buffer circuit 3 that strengthens, the data and the control signal timing sequence generating circuit 2 that receive network and singlechip computer 1 order and remaining circuit is controlled, quicken its beam intensity information-processing circuit 5, accelerator synchronizing pulse isolated drive circuit 7, receiving data information also is sent to the next stage image with it by Ethernet and checks subsystem 10 and receive image and check the subsystem order and send it to data and the network and singlechip computer of control signal timing sequence generating circuit 1, and the voltage-stabilized power supply circuit 8 of various power supplys is provided.
Its course of work is as follows, after network and singlechip computer 1 receives the enabled instruction of image inspection subsystem 10, log-on data storage and control signal timing sequence generating circuit 2 produce control signal corresponding, send the required synchronous triggering pulse of accelerator 11 by buffer circuit 3 and difference channel 4, be sent to accelerator 11 by isolated drive circuit 7, the signal from detector module circuit 13 is obtained in control then, detector module circuit 13 signals enter data storage and control signal timing sequence generating circuit 2 through difference and buffering circuit, after going here and there the view data of serial input and transform, this circuit stores data storage circuitry 6 into, network and singlechip computer obtains the previous column view data of storing at another assigned address simultaneously, after having stored these row detector data, interrupt to network and singlechip computer 1, network and singlechip computer obtains this column data again, form with Ethernet sends the previous column view data simultaneously, alternately back and forth, row are sent to image once the view data that is listed as and check that subsystem 10 is handled and imaging.
Referring to Figure 10, data are obtained with control module circuit 9 and are linked to each other with digital detector module circuit 13 with control signal and power cable by data, check that by Ethernet and image subsystem 10 links to each other, link to each other with accelerator 11 with synchronous triggering signal cable shielding twisted-pair feeder by the two concentric cable of beam intensity signal.Image inspection subsystem 10 just can be obtained with control module circuit 9 by data and carry out image data acquisition and handled.
Enforcement to physical circuit of the present invention is further described below.
Referring to Fig. 2, data and control signal RS485 difference input or output circuit 4 and comprise that model is the RS485 chip U5-U11 of MAX3468 and the filter capacitor C14-C20 of each chip, and the build-out resistor R1, the R2 that fall reflection, the signal of required long-distance transmissions is converted into the RS485 differential signal, strengthens antijamming capability greatly.
Referring to Fig. 3, data and control signal buffer circuit 3 are the eight road ternary buffer chip U4 formations of 74 (54) LS244 by model, because time stagnant function and the strong driving force of U4 itself can be carried out shaping and strengthen driving force data-signal and control.
Referring to Fig. 4, data storage and control timing produce circuit 2 and comprise that model is the programming device U2 of EP1K30, and the model that offers the U2 configuration information is the chip U19 of EPC2, and clock shake Z1 and filter capacitor C21-C37, pull-up resistor R4-R7.Data signal line D0L-D7L links to each other with the U3 of data storage circuitry 6 with address signal line A0L-A13L and read-write control line, and data-signal is write U3.Address signal line A0R-A13R and output enable line OER also link to each other with U3.CLK1, CONV1, DXMIT1, DVALID1, DCLK1, DIN1, TEST1, data such as ACC1 or control signal wire link to each other with the U4 of buffer circuit 3.TMS, TD, signals such as DATA0 link to each other with U19, and signals such as TCK, TDO, TMS, TDI can make FPGA be configured by outside line.Control signal wires such as REG0-REG7 and INT, RD, RET, DSEL are connected to network and singlechip computer 1.SDO, SCK, CNV link to each other with the U17 of accelerator intensity information-processing circuit 5, obtain beam intensity information.R3 and R13 play buffer action, reduce clock and shake to the interference of other circuit.Clock shake Z1 frequency should 20MHz or more than.
Referring to Fig. 5, data storage circuitry 6 comprises that model is filter capacitors such as the dual port RAM chip U3 of IDT70V06 and C49-C51.A0L-A13L, A0R-A13R, D0R-D7R, OER, addresses such as R/WL, data line are linked U2, and D0L-D7L links network and singlechip computer U1.CEL ground connection OEL, SEML etc. connect power supply makes network and singlechip computer 1 read signal by the R/WL signal that U2 produces at any time.SEMR, R/WR, M/S etc. connect power supply and CER ground connection makes U2 write data at any time by the OER signal.
Referring to Fig. 6, network and singlechip computer 1 comprises that model is the single-chip microcomputer U1 of RCM3200, and the C54-C57 filter capacitor, pull-up resistor R13, reset switch S1.Signal wire REG0-REG7, control line RD, INT, RET, DSEL etc. are connected to U2, and the D0R-D7R data line is connected to U3.Single-chip microcomputer is used for controlling U2 (FPGA) by REG0-REG7 and RD signal, obtains the data of dual port RAM by control lines such as D0R-D7R data line and DSEL, RD, INT.S1 is used for single-chip microcomputer is resetted, and single-chip microcomputer is by the RET signal U2 (FPGA) that resets.
Referring to Fig. 7, accelerator synchronizing pulse isolated drive circuit 7 comprises that model is that photoelectricity coupling chip U12 and the model of 6N137 is the DC-DC low pressure insulating power supply U21 of B0505S, and filter capacitor C52, C53, pull-up resistor R12 etc.Power supply is by U21, and synchronous triggering signal ACC isolates by optocoupler 12, selects suitable output current by pull-up resistor, just offers synchronous triggering pulse signal TRIG-ACC and ground DGND1 that accelerator and this module are isolated fully.
Referring to Fig. 8, accelerator intensity information-processing circuit 5 comprises that model is AD8605 operational amplifier U16, and model is the analog to digital converter U17 of AD7685, and it is the chip U15 of ADR435 that the reference voltage model is provided, and capacitor C 38-C48 that strobes and resistance R 9, R10.The analog level signal of accelerator intensity is represented from accelerator in the VACC position, and SCK, SDO, CNV signal link to each other with U2, and intensity digital signal after the AD conversion is delivered to U2.
Referring to Fig. 9, voltage-stabilized power supply circuit 8 comprises that model is 7805 regulator block U14, and model is the regulator block U18 of LM1117-2.5, model is the regulator block U20 of LM1117-3.3, model is the regulator block U13 of LM1117-3.3, the fuse F1 that can reset, and filter inductance L1 at different levels, ferrite L2, capacitor C 1-C13 and C58-C61 provide required various power supply+3.3V respectively, C3.3V, + 2.5V ,+5V etc.Use ferrite L2 digitally with to couple together with simulating.
Claims (6)
1. system that radiant image obtains and controls with data is characterized in that: comprise that image checks subsystem (10), obtain with control module circuit (9) by signal hop and data and be connected; Data are obtained with control module circuit (9) and are linked to each other with digital detector module circuit (13) with control signal and power lead by data, and transmitted beam intensity of flow signal wire links to each other with accelerator (11) with the synchronous triggering signal line; Accelerator (11) is used to produce the required x ray signal of imaging; Digital detector module circuit (13), be used for that signal to detector output amplifies, AD changes, and be converted into the convenient RS485 differential signal that transmits, the RS485 differential signal is generated by the RS485 difference channel, data are obtained and control module circuit (9), comprising:
---data and control signal difference channel (4) are used to finish reception or transmission to the data and the control signal of digital detector modular circuit;
---data and control signal buffer circuit (3), the shaping and the driving that are used to finish data and control signal strengthen;
---data storage and control timing produce circuit (2), are used to finish to the string and the conversion of input data and produce corresponding storage signal, sequential, the control data memory circuit; Finish required signal, the sequential of digital detector modular circuit control; Produce the required synchronizing pulse of accelerator; Finish mutual control, receive the order that network and singlechip computer sends, produce the required synchronous triggering pulse of accelerator, receive the accelerator intensity signal and be sent to network and singlechip computer network and singlechip computer and data storage circuitry;
---data storage circuitry (6), the data that convert through the programming device in data storage and the control timing generation circuit are stored, maybe the data of storage are delivered to network and singlechip computer;
---network and singlechip computer (1), be used for receiving picture check subsystem command signal by Ethernet, and be sent to data storage and control timing and produce programming device in the circuit, receive the data of the dual port RAM storer in the data storage circuitry and data are delivered to the picture check system with the form of Ethernet;
---accelerator synchronizing pulse isolated drive circuit (7) is used to finish the isolation drive of accelerator synchronizing pulse;
---accelerator intensity information-processing circuit (5), be used for finishing to the simulating signal of expression accelerator intensity follow, modulus changes and data-signal is delivered to the programming device that data storage and control timing produce circuit handle;
---voltage-stabilized power supply circuit (8) is used to provide direct supply.
2. the system that a kind of radiant image as claimed in claim 1 obtains and controls with data is characterized in that, the signal hop is the transmission system of Ethernet.
3. the system that a kind of radiant image as claimed in claim 2 obtains and controls with data is characterized in that: described data and control signal difference channel (4) comprise some difference chips, and the difference chip can be controlled several digital geochemical exploration simultaneously and survey the device module.
4. the system that a kind of radiant image as claimed in claim 2 obtains and controls with data, it is characterized in that: described data storage and control timing produce circuit (2) and comprise programming device U2, offer the chip U19 of programming device U2 configuration information, the clock Z1 that shakes, filter capacitor C21-C37, pull-up resistor R4-R7, wherein, model is the data signal line D0L-D7L of the programming device U2 of EP1K30, address signal line A0L-A13L, read-write control line, address signal line A0R-A13R and output enable line OER link to each other with data storage circuitry (6), the pin CLK1 of programming device U2, CONV1, DXMIT1, DVALID1, DCLK1, DIN1, TEST1, ACC1 links to each other with control signal buffer circuit (3) with data, the pin TMS of programming device U2, TD, DATA0 links to each other with the chip U19 of configuration information, the TCK of programming device U2, TDO, TMS, the TDI signal can make programming device be configured by outside line, the control signal wire REG0-REG7 of programming device U2, INT, RD, RET, DSEL is connected to network and singlechip computer, the pin SDO of programming device U2, SCK, CNV links to each other with accelerator intensity information-processing circuit (5), obtains beam intensity information.
5. the system that a kind of radiant image as claimed in claim 2 obtains and controls with data, it is characterized in that: accelerator synchronizing pulse isolated drive circuit (7) comprises insulating power supply chip U21, photoelectricity coupling chip U12, pull-up resistor, filter capacitor, wherein, power supply is isolated by insulating power supply chip U21, synchronous triggering signal ACC isolates by photoelectricity coupling chip U12, select suitable output current by pull-up resistor, offer accelerator and data and obtain the synchronous triggering pulse signal of isolating fully with the control module circuit.
6. the system that a kind of radiant image as claimed in claim 2 obtains and controls with data, it is characterized in that: described accelerator intensity information-processing circuit (5) comprises operational amplifier U16, analog to digital converter U17, the chip U15 of reference voltage is provided, the capacitor C 38-C48 that strobes, resistance R 9, R10, wherein, the input end of operational amplifier U16 receives the analog level signal of representing accelerator intensity from accelerator, model is the pin SCK of the analog to digital converter U17 of AD7685, SDO, CNV links to each other with programming device U2, and intensity digital signal after the AD conversion is delivered to programming device U2.
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| CN 200510086817 CN1964593B (en) | 2005-11-09 | 2005-11-09 | A system to acquire and control data for radiation imaging |
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| CN 200510086817 CN1964593B (en) | 2005-11-09 | 2005-11-09 | A system to acquire and control data for radiation imaging |
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| CN1964593A CN1964593A (en) | 2007-05-16 |
| CN1964593B true CN1964593B (en) | 2011-02-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101198206B (en) * | 2006-12-08 | 2012-07-11 | 清华大学 | Data acquiring and control circuit for radiation imaging and method thereof |
| CN102824182B (en) * | 2011-06-14 | 2014-10-29 | 北京中科美伦科技有限公司 | Differential interface device for CCD (Charge Coupled Device) detector of medical DR (Digital Radiography) system |
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| US5627367A (en) * | 1995-10-10 | 1997-05-06 | Sofield Science Services, Inc. | Radiation beam calibrater |
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