CN102389593B - Differential flow signal processing device and method - Google Patents
Differential flow signal processing device and method Download PDFInfo
- Publication number
- CN102389593B CN102389593B CN 201110191205 CN201110191205A CN102389593B CN 102389593 B CN102389593 B CN 102389593B CN 201110191205 CN201110191205 CN 201110191205 CN 201110191205 A CN201110191205 A CN 201110191205A CN 102389593 B CN102389593 B CN 102389593B
- Authority
- CN
- China
- Prior art keywords
- signal
- flow
- circuit
- microprocessor
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000012545 processing Methods 0.000 title claims abstract description 24
- 238000000605 extraction Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 20
- 238000006243 chemical reaction Methods 0.000 claims description 38
- 239000003990 capacitor Substances 0.000 claims description 34
- 238000007599 discharging Methods 0.000 claims description 33
- 238000001514 detection method Methods 0.000 claims description 6
- 238000003672 processing method Methods 0.000 claims description 6
- 238000005086 pumping Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 230000003321 amplification Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000009466 transformation Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 239000012530 fluid Substances 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 230000003044 adaptive effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000001631 haemodialysis Methods 0.000 description 1
- 230000000322 hemodialysis Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
- 238000000108 ultra-filtration Methods 0.000 description 1
Images
Abstract
The invention discloses a differential flow signal processing device and method, which belong to the field of signal processing. A driving signal is used as a calibrating signal for calibrating and amplifying the acquired flow signal; a phase extraction circuit converts the flow signal into a first flow digital signal and a second flow digital signal including phase information; and the flow signal is processed and calculated by a microprocessor. In the process of processing and calculating the flow signal difference by the microprocessor, if a signal instantaneous value is greater than a reference value after the first flow digital signal and the second flow digital signal are filtered by a microprocessor software, the microprocessor sends an exciting signal to an adjusting circuit, and the adjusting circuit controls and adjusts driving signal waveform output by a driving signal generator. By the device and the method, the accuracy of acquiring the flow signal is ensured, and accurate acquisition of the flow signal difference is realized by the phase extraction circuit and the microprocessor.
Description
Technical field
The present invention relates to a kind of flow signal processing device, especially a kind of differential flow signal processing device and method.
Background technology
The occasions such as flux modification of the measurement of ultrafiltration, many fluid pipelines in hemodialysis, need to measure the flow difference of two-way liquid (or fluid), but the flow difference measuring method of using now is to measure respectively the flow value of different pipelines, again two flow values are compared, thereby draw flow difference.
In addition, even collected the flow signal of two kinds of fluids by differential flow signal collector, can not realize the processing of flow signal difference, obtain accurate flow signal difference.
Summary of the invention
The purpose of this invention is to provide a kind of differential flow signal processing device, difference that can the accurate Calculation differential flow signal; Another object of the present invention is to provide a kind of differential flow signal processing method, the further difference of accurate Calculation differential flow signal.
The technical solution used in the present invention is such: according to an aspect of the present invention, the invention provides a kind of differential flow signal processing device, comprise power-switching circuit, for power supply is provided, it is characterized in that: also comprise first signal calibration amplifying circuit and secondary signal calibration amplifying circuit, phase extraction circuit, microprocessor and adjustment circuit that drive signal generator, driving power amplifying circuit, structure are identical, the outfan of wherein said drive signal generator is connected with the input of described driving signal power amplifying circuit;
The outfan of described drive signal generator is connected with the input of secondary signal calibration amplifying circuit with described first signal calibration amplifying circuit respectively, described first signal calibration amplifying circuit is connected with first input end, second input of described phase extraction circuit respectively with the outfan of secondary signal calibration amplifying circuit, and the outfan of described phase extraction circuit is connected with the input of described microprocessor;
The second outfan of described microprocessor is connected with the input of described adjustment circuit, and the first outfan of described adjustment circuit, the second outfan are connected with first input end, second input of described drive signal generator respectively;
Drive signal to send to the driving power amplifying circuit to amplify output by described drive signal generator, for controlling first flow signal, the second flow signal;
Drive signal to send to respectively described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit as calibrating signal by described drive signal generator, first flow signal and the second flow signal input to respectively described first signal calibration amplifying circuit and the calibration of secondary signal calibration amplifying circuit, amplify, become to comprise first flow digital signal, the second flow digital signal of phase information by described phase extraction circuit conversion, through described microprocessor processes, calculate again, by its first outfan output flow signal difference;
Described microprocessor is in the process of processing the calculated flow rate signal difference, if described first flow digital signal, the second flow digital signal are after described microprocessor software filtering, sample is greater than reference value, described microprocessor sends pumping signal to described adjustment circuit, is controlled the drive signal waveform of adjusting described drive signal generator output by described adjustment circuit.
The first outfan of described microprocessor is connected with the input of output conversion circuit, by described output conversion circuit, described first flow digital signal, the second flow digital signal is carried out to digital-to-analogue conversion and amplification.
Described first signal calibration amplifying circuit is by integrated amplifier OP1A, OP2A, OP2B and OP1B form, and described secondary signal calibration amplifying circuit is by integrated amplifier OP4A, OP5A, OP5B and OP4B form, and wherein said driving signal sends to respectively described integrated amplifier OP1A, the forward end of OP4A, input integrated transporting discharging OP2A after amplifying, the forward end of OP5A is as calibrating signal, and described first flow signal, the negative-going signal of the second flow signal is inputted respectively integrated transporting discharging OP2B, the forward end of OP5B, input integrated transporting discharging OP2A after amplifying, the negative end of OP5A, by integrated transporting discharging OP2A, OP5A is to described first flow signal, the second flow signal is calibrated, and exports to integrated transporting discharging OP1B, the forward end of OP4B, and described first flow signal, the forward signal input integrated transporting discharging OP1B of the second flow signal, the forward end of OP4B, described first flow signal, in the second flow signal through negative end signal and the forward end signal plus and respectively through integrated transporting discharging OP1B of calibration, output after OP4B amplifies, complete described first flow signal, the calibration of the second flow signal is amplified.
Described phase extraction circuit is comprised of the first identical branch circuit and the second branch circuit, modulus conversion chip, the first branch circuit is comprised of bridge rectifier VB1, resistance R 97, resistance R 98, polar capacitor C16, Zener diode D8, resistance R 99, resistance R 100 and polar capacitor C17, bridge rectifier VB1 is by resistance R 97 and resistance R 98, polar capacitor C16 and the Zener diode D8 connected and resistance R 99 parallel connections, then it is in parallel with polar capacitor C17 to pass through resistance R 100;
The second branch circuit is comprised of bridge rectifier VB2, resistance R 108, resistance R 109, polar capacitor C53, Zener diode D9, resistance R 110, resistance R 111 and polar capacitor C54, bridge rectifier VB2 is by resistance R 108 and resistance R 109, polar capacitor C53 and the Zener diode D9 connected and resistance R 110 parallel connections, then it is in parallel with polar capacitor C54 to pass through resistance R 111;
In the first branch circuit, resistance R 100 is connected with the first input end of modulus conversion chip with the node between polar capacitor C17, in the second branch circuit, resistance R 111 is connected with the second input of modulus conversion chip with the node between polar capacitor C54, and the outfan of described modulus conversion chip is connected with the input of described microprocessor.
Described adjustment circuit comprises two voltage comparator integrated circuits, the second a reference source module and adjustable resistance, wherein said the second a reference source module provides reference power supply to described pair of voltage comparator integrated circuit, the second outfan of described microprocessor is connected with the first input end of described pair of voltage comparator integrated circuit, described variable resistance is connected with the second input of described pair of voltage comparator integrated circuit, the first outfan of described pair of voltage comparator integrated circuit, the second outfan respectively with the first input end of described drive signal generator, the second input connects.
Described output conversion circuit is comprised of analog-digital chip, the first a reference source module, integrated transporting discharging OPA, OPB, the flow signal difference is amplified through described analog-digital chip, integrated transporting discharging OPA and OPB conversion, obtain the flow signal difference of analog form, wherein said the first a reference source module provides a reference source to analog-digital chip.
According to a further aspect in the invention, the invention provides a kind of differential flow signal processing method, comprise the following steps:
(01) drive signal to send to and drive the signal power amplifying circuit to amplify by drive signal generator, differential flow signal collector gathers first flow signal, the second flow signal under the effect of described driving signal, and the first flow signal and the second flow signal that collect are transferred to respectively to first signal calibration amplifying circuit, secondary signal calibration amplifying circuit;
(02) drive signal to send described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit to as calibrating signal by drive signal generator, and described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit amplify described first flow signal, the second flow signal calibration respectively according to described calibrating signal, be transferred to the phase extraction circuit conversion and become to comprise first flow digital signal and the second flow digital signal of phase information, then be transferred to microprocessor;
(03) described microprocessor is after to described first flow digital signal, the second flow digital signal software filtering, whether the detection signal instantaneous value is greater than reference value: if the reference value of being less than or equal to, the duty that means differential flow signal collector is normal, do not need by the waveform of the described driving signal of adjustment the regulation of electrical circuit drive signal generator output, and then adjust differential flow signal collector;
(04) described microprocessor is obtained respectively described first flow digital signal, the first phase signal of the second flow digital signal, the second phase signal by phase extraction algorithms, again described the first phase signal, the second phase signal are calculated after by Fourier transformation, asked for the phase signal difference;
(05) described microprocessor judges whether described phase signal difference reaches stationary value: if reach stationary value described microprocessor is contrasted described phase signal difference and described driving signal, draw the flow signal difference and by described microprocessor output.
In described step (03) if in described microprocessor detection signal instantaneous value be greater than reference value, the working state abnormal that means differential flow signal, need by the drive signal waveform of adjustment the regulation of electrical circuit drive signal generator output, thereby adjustment differential flow signal collector, further judge whether described sample is greater than setting value: if be greater than setting value, described microprocessor output negative incentive signal is to the adjustment circuit, and the drive signal waveform of being exported by the described drive signal generator of described adjustment the regulation of electrical circuit changes to negative sense;
If be less than or equal to setting value, described microprocessor output positive incentive signal is given described adjustment circuit, the drive signal waveform waveform that increases described drive signal generator output by described adjustment the regulation of electrical circuit is to positive change, and wherein said setting value means the degree of deviation of described first flow digital signal and the second flow digital signal;
Described microprocessor detects described sample and whether is greater than reference value, until be less than or equal to described reference value, stops adjusting.
In described step (05) if in described microprocessor judge that described phase signal difference does not reach stationary value, by non-linear amplitude control method, be adjusted at the parameter in phase signal difference computational process, make and recalculate the described phase signal difference drawn and reach stationary value.
In sum, owing to having adopted technique scheme, the invention has the beneficial effects as follows:
1, the present invention adopts and drives signal to be calibrated flow signal, has guaranteed the accuracy of flow signal acquisition, and has realized the accurate collection of flow signal difference by phase extraction circuit, microprocessor;
2, in the process of microprocessor calculated flow rate signal difference, microprocessor detects in real time flow signal and Sudden Anomalies whether occurs, when Sudden Anomalies occurring, microprocessor drives signal by the adjustment the regulation of electrical circuit in time, realize the real-time processing of flow signal acquisition process, thereby further improved the accuracy of the flow signal difference calculated;
3, after microprocessor calculates the flow signal difference, stability to the flow difference signal is judged, at the inner parameter of unstable timing adjustment microprocessor, comprising the various parameters that relate in calculating of flow signal difference, thereby guaranteed the stability of flow signal difference.
The accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is circuit frame principle figure of the present invention;
Fig. 2 is the front view of differential flow signal collector;
Fig. 3 is the cutaway view of differential flow signal collector along the G-G line;
Fig. 4 is the circuit diagram of power-switching circuit;
Fig. 5 is the circuit diagram of drive signal generator, signal calibration amplifying circuit and phase extraction circuit;
Fig. 6 is the circuit diagram of driving power amplifying circuit;
Fig. 7 is the circuit diagram of microprocessor;
Fig. 8 is the circuit diagram of output conversion circuit;
Fig. 9 is the circuit diagram of adjustment circuit;
Figure 10 is method flow diagram of the present invention;
Figure 11 is the adjustment schematic diagram of drive signal waveform.
The specific embodiment
Disclosed all features in this description, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Disclosed arbitrary feature in this description (comprising any accessory claim, summary and accompanying drawing), unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is,, unless special narration, each feature is an example in a series of equivalences or similar characteristics.
As shown in Figure 1, this differential flow signal processing device comprises power-switching circuit, drive signal generator, the driving power amplifying circuit, the identical first signal calibration amplifying circuit of structure and secondary signal calibration amplifying circuit, the phase extraction circuit, microprocessor, adjustment circuit and output conversion circuit, wherein the outfan of drive signal generator respectively with the driving power amplifying circuit, first signal calibration amplifying circuit is connected with the input of secondary signal calibration amplifying circuit, the outfan of first signal calibration amplifying circuit and secondary signal calibration amplifying circuit respectively with the first input end of phase extraction circuit, the second input connects, the outfan of phase extraction circuit is connected with the input of microprocessor respectively, the second outfan of microprocessor is connected with the input of adjustment circuit, the first outfan of adjustment circuit, the second outfan respectively with the first input end of drive signal generator, the second input connects, the first outfan of microprocessor is connected with the input of output conversion circuit.
Drive signal to send to and drive the signal power amplifying circuit to amplify output by drive signal generator, for controlling differential flow signal collector work, thereby gather out first flow signal, the second flow signal.Drive signal to send to first signal calibration amplifying circuit and secondary signal calibration amplifying circuit as calibrating signal by drive signal generator, the first flow signal, the second flow signal is transferred to respectively first signal calibration amplifying circuit by differential flow signal collector and secondary signal calibration amplifying circuit is calibrated, amplify, converted respectively to the first flow digital signal that comprises phase information by the phase extraction circuit, the second flow digital data transmission is to microprocessor, through microprocessor processes, calculate again, output flow signal difference (now output is digital signal).When needs are checked the flow signal difference of analog form, microprocessor is exported to output conversion circuit by the flow signal difference calculated and is carried out digital-to-analogue conversion and amplification.Microprocessor is in the process of processing the calculated flow rate signal difference, if first flow digital signal, the second flow digital signal are after microprocessor software filtering, sample is greater than reference value, microprocessor sends pumping signal to the adjustment circuit, controlled the drive signal waveform of drive signal generator output by the adjustment circuit, act on the signal calibration amplifying circuit and realize the calibration of flow signal, act on the driving power amplifying circuit and realize the control of differential flow signal collector, guarantee accurately to gather first flow signal and the second flow signal.
An embodiment of differential signal harvester is as shown in Fig. 2～3, this differential signal harvester comprises the first pipeline 1, second pipe 2, pedestal 3, first signal harvester 8, secondary signal harvester 9, vibrating device 10 and signal processing apparatus 11, wherein the first pipeline 1, second pipe 2 extend to the other end of pedestal 3 side by side through an end of pedestal 3, and this first pipeline 1, second pipe 2 are structurally distinguished symmetrical along the direction vertical with pedestal 3, two fluids flow into the first pipeline 1, second pipe 2 from different directions.Vibrating device 10 is comprised of magnetic drive joint 12, electromagnetic driver 13 and drive signal generator 14, wherein the first pipeline 1 intersects fixing with second pipe 2 at symmetrical centre point, magnetic drive joint 12 is fixed on the symmetrical centre point of the first pipeline 1, electromagnetic driver 13 is sleeved on magnetic drive joint 12, and electromagnetic driver 13 is connected with the driving power amplifying circuit by wire.In the flow signal acquisition process, drive signal to send to the driving power amplifying circuit to amplify by drive signal generator, be transferred to electromagnetic driver 13, make electromagnetic driver 13 move up and down, so that 12 vibrations of magnetic drive joint, first signal harvester 8, secondary signal harvester 9 are transferred to the signal calibration amplifying circuit by the first flow signal, the second flow signal that collect respectively.Certainly, the differential signal harvester includes but not limited to said structure.
In one embodiment of the invention, power-switching circuit as shown in Figure 4, it converts alternating current to low-voltage DC by transformator T1, bridge rectifier VB3, more respectively through voltage stabilizing chip U4, U5 output+5V and-power supply of 5V, offer each assembly of this device.
As shown in Fig. 5～9, first signal calibration amplifying circuit is by integrated transporting discharging OP1A, OP2A, OP2B and OP1B form, and secondary signal calibration amplifying circuit is by integrated transporting discharging OP4A, OP5A, OP5B and OP4B form, and the outfan difference output drive signal of drive signal generator U7 is to integrated transporting discharging OP1A, the forward end of OP4A, input integrated transporting discharging OP2A after amplifying, the forward end of OP5A is as calibrating signal, and the first flow signal, the negative end signal of the second flow signal is inputted respectively integrated transporting discharging OP2B, the forward end of OP5B, input integrated transporting discharging OP2A after amplifying, the negative end of OP5A, by integrated transporting discharging OP2A, OP5A is to the first flow signal, the second flow signal is calibrated, and exports to integrated transporting discharging OP1B, the forward end of OP4B, and first flow signal, the forward end signal input integrated transporting discharging OP1B of the second flow signal, the forward end of OP4B, the first flow signal, in the second flow signal through negative end signal and the forward signal addition and respectively through integrated transporting discharging OP1B of calibration, OP4B amplifies output, and the calibration that completes thus first flow signal and the second flow signal is amplified.
The phase extraction circuit is comprised of the first identical branch circuit and the second branch circuit, modulus conversion chip, the first branch circuit is comprised of bridge rectifier VB1, resistance R 97, resistance R 98, polar capacitor C16, Zener diode D8, resistance R 99, resistance R 100 and polar capacitor C17, bridge rectifier VB1 is by resistance R 97 and resistance R 98, polar capacitor C16 and the Zener diode D8 connected and resistance R 99 parallel connections, then it is in parallel with polar capacitor C17 to pass through resistance R 100, the second branch circuit is by bridge rectifier VB2, resistance R 108, resistance R 109, polar capacitor C53, Zener diode D9, resistance R 110, resistance R 111 and polar capacitor C54 form, bridge rectifier VB2 is by resistance R 108 and resistance R 109, the Zener diode D9 of polar capacitor C53 and series connection and resistance R 110 parallel connections, in parallel with polar capacitor C54 by resistance R 111 again, wherein in the first branch circuit, resistance R 100 is connected with the first input end (port 2) of modulus conversion chip as its outfan with the node between polar capacitor C17, in the second branch circuit, resistance R 111 is connected with second input (port one) of modulus conversion chip as its outfan with the node between polar capacitor C54.The first flow signal amplified through calibration is through bridge type reorganizer VB1 rectification, obtain the first flow analogue signal that comprises phase signal through resistance R 97, resistance R 98, polar capacitor C16, Zener diode D8, resistance R 99, resistance R 100 and polar capacitor C17, then convert the first flow digital signal to through modulus conversion chip, the second flow signal amplified through calibration is through bridge rectifier VB2 rectification, through resistance R 108, resistance R 109, polar capacitor C53, Zener diode D9, resistance R 110, resistance R 111 and polar capacitor C54 obtain the second flow analog signals that comprises phase signal, convert the second flow digital signal to through modulus conversion chip again, above-mentioned first flow digital signal and the second flow digital signal are by the outfan CLK port of analog-digital chip, the DIN port, DOUT port and CS port are exported to the corresponding input of microprocessor U13, microprocessor U13 processes and to calculate the flow signal difference and by its first outfan DB1 port, the DB2 port, DB3 port and the output of DB4 port.
The flow signal difference of exporting due to microprocessor U13 is digital form, in order to obtain the flow signal difference of analog form, microprocessor U13 is transferred to output conversion circuit by the flow signal difference, output conversion circuit is comprised of analog-digital chip U2, the first a reference source module D2, integrated transporting discharging OPA, OPB, the flow signal difference is amplified through analog-digital chip U2, integrated transporting discharging OPA and OPB conversion, obtain the flow signal difference of the analog form of needs, wherein this first a reference source module D2 provides a reference source to analog-digital chip U2.Certainly, microprocessor U13 can also be connected with other change-over circuits, to convert when being necessary the other forms of signals such as pulse to.
The adjustment circuit comprises two voltage comparator integrated circuit U6, the second a reference source module D3 and adjustable resistance R29, and wherein the second a reference source module D3 provides a reference source to this couple of voltage comparator integrated circuit U6.The second outfan P1.5 port of microprocessor U13 is connected with the first input end Trans port of two voltage comparator integrated circuit U6, adjustable resistance R29 is connected with the second input of two voltage comparator integrated circuit U6, and the first outfan Charge1 of two voltage comparator integrated circuit U6, the second outfan Charge2 are connected with first input end port 3, the second input port one 3 of drive signal generator U7 respectively.When microprocessor processes is calculated first flow digital signal, the second flow digital signal, if first flow digital signal, the second flow digital signal are after microprocessor U13 software filtering, sample is greater than reference value, microprocessor sends pumping signal to the adjustment circuit, is controlled the drive signal waveform of drive signal generator U7 output by the adjustment circuit.Drive signal all bringing into play and acting in differential flow signal sampling and processing process, in the differential flow signal gatherer process for driving differential flow signal collector vibration, guarantee the accuracy of flow signal acquisition, for the calibration of flow signal, guarantee the accuracy that flow signal is processed in the differential flow signal processing procedure.Variable resistance R29, for manually adjusting the output of two voltage comparator integrated circuits, drives signal thereby adjust.
The device parameters adopted in the present embodiment is:
Drive signal generator U7 selects the accurate functional generator of the monolithic of ICL8038 model, the model of modulus conversion chip is the TLC2543 model, the model of microprocessor U13 is STC51, the model of analog-digital chip is TLV5618, the model of the first a reference source module is TL431, the model of two voltage comparator integrated circuits is LM393, and the model of the second a reference source module is TL431.
As shown in figure 10, the present invention also provides a kind of differential flow signal processing method, according to following steps, carries out:
(01) drive signal to send to the driving power amplifying circuit to amplify output by drive signal generator U7, control differential flow signal collector and gather first flow signal, the second flow signal, the first flow signal collected, the second flow signal are transferred to respectively first signal calibration amplifying circuit, secondary signal calibration amplifying circuit.
(02) drive signal to send first signal calibration amplifying circuit, secondary signal calibration amplifying circuit to as calibrating signal by drive signal generator U7, and this first signal calibration amplifying circuit, secondary signal calibration amplifying circuit amplify first flow signal, the second flow signal calibration respectively according to this calibrating signal, be transferred to the phase extraction circuit conversion and become to comprise first flow digital signal, the second flow digital signal of phase information, then be transferred to microprocessor.
(03), in the flow signal acquisition process, the flow signal that may exist many factors to cause to collect produces error, such as the foozle of each assembly in differential flow signal collector, and the alignment error of each assembly etc.In order to reduce measurement error, improve acquisition precision, introduced the whether normal reference value of duty for judging differential flow signal collector in this method, wherein measured value and the difference between theoretical value of this reference value differential flow signal collector in repeatedly surveying are determined.Microprocessor is to above-mentioned first flow digital signal, the second flow digital signal software filtering, and whether the sample after detection filter is greater than reference value: if the reference value of being less than or equal to, the duty that means differential flow signal collector is normal, the error of the flow signal measured, within acceptable scope, does not need by the drive signal waveform of adjustment the regulation of electrical circuit drive signal generator output;
If the reference value of being greater than, mean that Sudden Anomalies appears in the traffic figure signal, the working state abnormal of differential flow signal collector, microprocessor need to be by the drive signal waveform of adjustment the regulation of electrical circuit drive signal generator output, thereby the adjustment differential flow signal collector, the erasure signal Sudden Anomalies.For how adjusting drive signal waveform, in this method, introduced for meaning the setting value of the degree of deviation between first flow digital signal and the second flow digital signal, further to reduce error.As shown in figure 11, (a) be the drive signal waveform figure under the normal excitation state; (b) be drive signal waveform figure under the negative incentive signal; (c) be drive signal waveform figure under the positive incentive signal.
Microprocessor further judges whether sample is greater than setting value: if be greater than, microprocessor output negative incentive signal is to the adjustment circuit, and the drive signal waveform that is reduced drive signal generator output by the adjustment the regulation of electrical circuit changes (such as moving down) to negative sense;
If the reference value of being less than or equal to, microprocessor output positive incentive signal is to the adjustment circuit, and the drive signal waveform that is increased drive signal generator output by the adjustment the regulation of electrical circuit is to positive change (all as above move);
After adjustment completes, whether the microprocessor sample after detection filter again is greater than reference value, until be less than or equal to reference value, stops adjusting.
(04) microprocessor is obtained the first phase signal, the second phase signal by phase extraction algorithms from the first flow digital signal that comprises phase information, the second flow digital signal, and carry out Fourier transformation, ask for the phase signal difference, wherein phase extraction algorithms extensively is present in current technical research, belong to prior art, at this, will not tire out and state.
(05) whether microprocessor judges phase signal difference reaches stationary value, in certain hour section t, whether phase signal is greater than certain scope, wherein time period t and scope can be set according to practical situation oneself, if the phase signal difference reaches stationary value, microprocessor is calculated this phase signal difference with driving signal, ask for the flow signal difference and exported by microprocessor, wherein asking for as prior art of flow signal difference, will not tire out and state at this;
If microprocessor is judged the phase signal difference and is not reached stationary value, pass through adaptive algorithm, adjust the inner parameter (comprising the parameter related in phase signal difference computational process) of microprocessor, make and recalculate the phase signal difference drawn and reach stationary value, wherein adaptive algorithm is prior art, at this, will not tire out and state.
The present invention is not limited to the aforesaid specific embodiment.The present invention expands to any new feature or any new combination disclosed in this manual, and the arbitrary new method disclosed or step or any new combination of process.
Claims (9)
1. a differential flow signal processing device, comprise power-switching circuit, for power supply is provided, it is characterized in that: also comprise first signal calibration amplifying circuit and secondary signal calibration amplifying circuit, phase extraction circuit, microprocessor and adjustment circuit that drive signal generator, driving power amplifying circuit, structure are identical, the outfan of wherein said drive signal generator is connected with the input of described driving power amplifying circuit;
The outfan of described drive signal generator is connected with the input of secondary signal calibration amplifying circuit with described first signal calibration amplifying circuit respectively, described first signal calibration amplifying circuit is connected with first input end, second input of described phase extraction circuit respectively with the outfan of secondary signal calibration amplifying circuit, and the outfan of described phase extraction circuit is connected with the input of described microprocessor;
The second outfan of described microprocessor is connected with the input of described adjustment circuit, and the first outfan of described adjustment circuit, the second outfan are connected with first input end, second input of described drive signal generator respectively;
Drive signal to send to the driving power amplifying circuit to amplify output by described drive signal generator, for controlling the collection of first flow signal, the second flow signal;
Drive signal to send to respectively described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit as calibrating signal by described drive signal generator, first flow signal and the second flow signal input to respectively described first signal calibration amplifying circuit and the calibration of secondary signal calibration amplifying circuit, amplify, become to comprise first flow digital signal, the second flow digital signal of phase information by described phase extraction circuit conversion, through described microprocessor processes, calculate again, by its first outfan output flow signal difference;
Described microprocessor is in the process of processing the calculated flow rate signal difference, if described first flow digital signal, the second flow digital signal are after described microprocessor software filtering, sample is greater than reference value, described microprocessor sends pumping signal to described adjustment circuit, is controlled the drive signal waveform of adjusting described drive signal generator output by described adjustment circuit.
2. differential flow signal processing device according to claim 1, it is characterized in that: the first outfan of described microprocessor is connected with the input of output conversion circuit, described first flow digital signal, the second flow digital data transmission are to microprocessor, described microprocessor output flow signal difference, microprocessor is transferred to output conversion circuit by the flow signal difference, by described output conversion circuit, will carry out digital-to-analogue conversion and amplification.
3. differential flow signal processing device according to claim 1 is characterized in that: described first signal calibration amplifying circuit is by integrated transporting discharging OP1A, OP2A, OP2B and OP1B form, and described secondary signal calibration amplifying circuit is by integrated transporting discharging OP4A, OP5A, OP5B and OP4B form, and wherein said driving signal sends to respectively described integrated transporting discharging OP1A, the forward end of OP4A, input integrated transporting discharging OP2A after amplifying, the forward end of OP5A is as calibrating signal, and described first flow signal, the negative-going signal of the second flow signal is inputted respectively integrated transporting discharging OP2B, the forward end of OP5B, input integrated transporting discharging OP2A after amplifying, the negative end of OP5A, by integrated transporting discharging OP2A, OP5A is to described first flow signal, the second flow signal is calibrated, and exports to integrated transporting discharging OP1B, the forward end of OP4B, and described first flow signal, the forward signal input integrated transporting discharging OP1B of the second flow signal, the forward end of OP4B, described first flow signal, in the second flow signal through negative-going signal and the forward signal addition and respectively through integrated transporting discharging OP1B of calibration, output after OP4B amplifies, complete described first flow signal, the calibration of the second flow signal is amplified.
4. differential flow signal processing device according to claim 1, it is characterized in that: described phase extraction circuit is by the first identical branch circuit and the second branch circuit, modulus conversion chip forms, the first branch circuit is by bridge rectifier VB1, resistance R 97, resistance R 98, polar capacitor C16, Zener diode D8, resistance R 99, resistance R 100 and polar capacitor C17 form, bridge rectifier VB1 is by resistance R 97 and resistance R 98, the Zener diode D8 of polar capacitor C16 and series connection and resistance R 99 parallel connections, in parallel with polar capacitor C17 by resistance R 100 again,
The second branch circuit is comprised of bridge rectifier VB2, resistance R 108, resistance R 109, polar capacitor C53, Zener diode D9, resistance R 110, resistance R 111 and polar capacitor C54, bridge rectifier VB2 is by resistance R 108 and resistance R 109, polar capacitor C53 and the Zener diode D9 connected and resistance R 110 parallel connections, then it is in parallel with polar capacitor C54 to pass through resistance R 111;
In the first branch circuit, resistance R 100 is connected with the first input end of modulus conversion chip with the node between polar capacitor C17, in the second branch circuit, resistance R 111 is connected with the second input of modulus conversion chip with the node between polar capacitor C54, and the outfan of described modulus conversion chip is connected with the input of described microprocessor.
5. differential flow signal processing device according to claim 1, it is characterized in that: described adjustment circuit comprises two voltage comparator integrated circuits, the second a reference source module and adjustable resistance, wherein said the second a reference source module provides reference power supply to described pair of voltage comparator integrated circuit, the second outfan of described microprocessor is connected with the first input end of described pair of voltage comparator integrated circuit, described adjustable resistance is connected with the second input of described pair of voltage comparator integrated circuit, the first outfan of described pair of voltage comparator integrated circuit, the second outfan respectively with the first input end of described drive signal generator, the second input connects.
6. differential flow signal processing device according to claim 2, it is characterized in that: described output conversion circuit is comprised of analog-digital chip, the first a reference source module, integrated transporting discharging OPA, OPB, the flow signal difference is amplified through described analog-digital chip, integrated transporting discharging OPA and OPB conversion, obtain the flow signal difference of analog form, wherein said the first a reference source module provides a reference source to described analog-digital chip.
7. a differential flow signal processing method is characterized in that comprising the following steps:
(01) driving signal to send the driving power amplifying circuit to by drive signal generator amplifies, differential flow signal collector gathers first flow signal and the second flow signal under the effect of described driving signal, and is transferred to respectively first signal calibration amplifying circuit, secondary signal calibration amplifying circuit;
(02) drive signal to send described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit to as calibrating signal by drive signal generator, and described first signal calibration amplifying circuit, secondary signal calibration amplifying circuit amplify described first flow signal, the second flow signal calibration respectively according to described calibrating signal, be transferred to the phase extraction circuit conversion and become to comprise first flow digital signal and the second flow digital signal of phase information, then be transferred to microprocessor;
(03) described microprocessor is after to described first flow digital signal, the second flow digital signal software filtering, whether the detection signal instantaneous value is greater than reference value: if be less than or equal to described reference value, the duty that means differential flow signal collector is normal, do not need by the described drive signal waveform of adjustment the regulation of electrical circuit drive signal generator output, and then adjust differential flow signal collector;
(04) described microprocessor is obtained respectively described first flow digital signal, the first phase signal of the second flow digital signal, the second phase signal by phase extraction algorithms, again described the first phase signal, the second phase signal are calculated after by Fourier transformation, asked for the phase signal difference;
(05) described microprocessor judges whether described phase signal difference reaches stationary value: if reach stationary value described microprocessor is calculated described phase signal difference and described driving signal, draw the flow signal difference and by described microprocessor output digit signals.
8. differential flow signal processing method according to claim 7, it is characterized in that: in described step (03) if in described microprocessor detection signal instantaneous value be greater than described reference value, the working state abnormal that means differential flow signal collector, need by the drive signal waveform of adjustment the regulation of electrical circuit drive signal generator output, thereby adjustment differential flow signal collector, further judge whether described sample is greater than setting value: if be greater than described setting value, described microprocessor output negative incentive signal is to the adjustment circuit, drive signal waveform by the described drive signal generator output of described adjustment the regulation of electrical circuit changes to negative sense,
If be less than or equal to described setting value, described microprocessor output positive incentive signal is given described adjustment circuit, the drive signal waveform of being exported by the described drive signal generator of described adjustment the regulation of electrical circuit is to positive change, and wherein said setting value means the degree of deviation of described first flow digital signal and the second flow digital signal;
Described microprocessor detects described sample and whether is greater than described reference value, until be less than or equal to described reference value, stops adjusting.
9. differential flow signal processing method according to claim 7, it is characterized in that: in described step (05) if in described microprocessor judge that described phase signal difference does not reach stationary value, by non-linear amplitude control method, be adjusted at the parameter in phase signal difference computational process, make and recalculate the described phase signal difference drawn and reach stationary value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110191205 CN102389593B (en) | 2011-07-08 | 2011-07-08 | Differential flow signal processing device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110191205 CN102389593B (en) | 2011-07-08 | 2011-07-08 | Differential flow signal processing device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102389593A CN102389593A (en) | 2012-03-28 |
| CN102389593B true CN102389593B (en) | 2013-12-25 |
Family
ID=45857056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110191205 Expired - Fee Related CN102389593B (en) | 2011-07-08 | 2011-07-08 | Differential flow signal processing device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102389593B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015007596A1 (en) | 2013-07-15 | 2015-01-22 | Gambro Lundia Ab | Relative pump calibration for ultrafiltration control in a dialysis apparatus |
| WO2015007595A1 (en) | 2013-07-15 | 2015-01-22 | Gambro Lundia Ab | Individual pump calibration for ultrafiltration control in a dialysis apparatus |
| CN111415493A (en) * | 2020-04-01 | 2020-07-14 | 宿迁市计量测试所 | Combustible gas alarm circuit capable of rapidly alarming |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5178018A (en) * | 1989-10-31 | 1993-01-12 | British Gas Plc | System for measuring the time for a signal to pass between two spaced points in a fluid |
| US5555190A (en) * | 1995-07-12 | 1996-09-10 | Micro Motion, Inc. | Method and apparatus for adaptive line enhancement in Coriolis mass flow meter measurement |
| US5648616A (en) * | 1994-08-16 | 1997-07-15 | Endress + Hauser Flowtec Ag | Evaluation Electronics of a coriolis mass flow sensor |
| CN1981181A (en) * | 2004-06-14 | 2007-06-13 | 微动公司 | Coriolis flow meter and method for determining a signal difference in calbe and first and second pickoff sensors |
| CN101203733A (en) * | 2005-05-31 | 2008-06-18 | 恩德斯+豪斯流量技术股份有限公司 | Coriolis flow meter and method for flow measurement |
| JP4694645B1 (en) * | 2010-02-19 | 2011-06-08 | 株式会社オーバル | Signal processing method, signal processing apparatus, and vibration type density meter |
-
2011
- 2011-07-08 CN CN 201110191205 patent/CN102389593B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5178018A (en) * | 1989-10-31 | 1993-01-12 | British Gas Plc | System for measuring the time for a signal to pass between two spaced points in a fluid |
| US5648616A (en) * | 1994-08-16 | 1997-07-15 | Endress + Hauser Flowtec Ag | Evaluation Electronics of a coriolis mass flow sensor |
| US5555190A (en) * | 1995-07-12 | 1996-09-10 | Micro Motion, Inc. | Method and apparatus for adaptive line enhancement in Coriolis mass flow meter measurement |
| CN1981181A (en) * | 2004-06-14 | 2007-06-13 | 微动公司 | Coriolis flow meter and method for determining a signal difference in calbe and first and second pickoff sensors |
| CN101203733A (en) * | 2005-05-31 | 2008-06-18 | 恩德斯+豪斯流量技术股份有限公司 | Coriolis flow meter and method for flow measurement |
| JP4694645B1 (en) * | 2010-02-19 | 2011-06-08 | 株式会社オーバル | Signal processing method, signal processing apparatus, and vibration type density meter |
Non-Patent Citations (1)
| Title |
|---|
| JP特许第4694645号B1 2011.06.08 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102389593A (en) | 2012-03-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102389593B (en) | Differential flow signal processing device and method | |
| CN102970646B (en) | Loudspeaker abnormal sound detection circuit device and detection method based on constant current source power amplification | |
| CN101557204A (en) | Automatic gain control circuit of multistage high dynamic range used in ultrasonic distance measurement | |
| CN102116757A (en) | Electrical conductivity measurement system and method for liquid | |
| CN108992068A (en) | A kind of phase compensating circuit, magnetic induction image device and phase compensating method | |
| CN102707162A (en) | Strain acquisition circuit system and strain acquisition method | |
| CN103528492B (en) | Signal translating system based on wide range submicron order high accuracy LVDT displacement transducer | |
| CN102495275A (en) | High-precision current detection circuit based on CPU (Central Processing Unit) | |
| CN202710200U (en) | Space remote sensing CCD camera high-precision CCD temperature measurement circuit | |
| CN209157099U (en) | Vacuum pressure casting machine casting temperature measuring device | |
| CN110673083B (en) | Direct current standard source device for detecting electric energy meter metering error | |
| CN106885948B (en) | A kind of laser Height-adjusting device capacitance measuring device | |
| CN104776791A (en) | Displacement sensor and displacement measuring method | |
| CN104267262A (en) | High-precision intelligent loop resistance tester | |
| CN204495414U (en) | A kind of low-power consumption Roots type flowmeter based on GPRS | |
| CN208156065U (en) | A kind of lossless high-precision fast current detection circuit | |
| CN114440936A (en) | Signal acquisition circuit of vibrating wire type sensor | |
| CN105445536A (en) | Alternating current voltage acquisition device and working method thereof | |
| CN104393851A (en) | Automatic gain control circuit applied to ultrasonic heat meter and control method of automatic gain control circuit | |
| CN206479576U (en) | A kind of intelligent high-accuracy voltage data collecting system | |
| CN204216856U (en) | A kind of automatic gain control circuit being applied to ultrasonic calorimeter | |
| CN205898902U (en) | Small resistance measurement device | |
| CN111857220B (en) | Temperature sampling circuit and control method thereof | |
| CN205015083U (en) | Frequency measuring device of vibration wire formula sensor | |
| CN102347720B (en) | Method for automatically zeroing analog quantity speed instructions of servo controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Science and technology building, No. 5 South mercury 401121 northern New District of Chongqing municipality Mount Huangshan Avenue 5 floor Patentee after: Chongqing Australia Chiron medical Polytron Technologies Inc Address before: 401121 New District of Chongqing City High Tech Park, Mount Huangshan Jiangbei District North Road No. 5 south building, 5F mercury B Patentee before: Chongqing Oakland Medical Equipment Research Co., Ltd. |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Differential flow signal processing device and method Effective date of registration: 20170619 Granted publication date: 20131225 Pledgee: Bank of Chongqing Limited by Share Ltd Renmin Road Branch Pledgor: Chongqing Australia Chiron medical Polytron Technologies Inc Registration number: 2017990000501 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20180703 Granted publication date: 20131225 Pledgee: Bank of Chongqing Limited by Share Ltd Renmin Road Branch Pledgor: Chongqing Australia Chiron medical Polytron Technologies Inc Registration number: 2017990000501 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Differential flow signal processing device and method Effective date of registration: 20180703 Granted publication date: 20131225 Pledgee: Bank of Chongqing Limited by Share Ltd Renmin Road Branch Pledgor: Chongqing Australia Chiron medical Polytron Technologies Inc Registration number: 2018990000520 |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131225 Termination date: 20210708 |