CA1092234A - Method and apparatus for detecting and locating fluid leaks - Google Patents

Abstract

ABSTRACT OF DISCLOSURE
An apparatus and method for detecting and locating a fluid leak in an underground pipe or the like in which the vibration produced by the leak is intercepted at selected spaced apart points by microphones or other trans-ducers, in which the vibration intercepted at each of the two points is con-verted into an electrical signal, and in which the extent of correlation of the two resulting signals is varied by variably time delaying one signal relative to the other to determine the leak's location from the occurrence of maximum correlation between the signals. In one embodiment, the variable time delay of one signal relative to the other is accomplished by a variable length time delay line and a means for progressively varying the length of the delay line. In another embodiment the variable time delay is accomplished by a recirculating delay line analyzer that does more data age comparisons with the same delays in the same time than the variable length delay line.

Description

m~z234 METHOD AND APPARATUS FOR DETECTING
AND LOCATING FLUID LEAKS

`FIELD OF INVENTION
~ his invention relates to methods and apparatus for detecting and locating fluid leaks in fluid-conveying conduits or pipes which are buried, underground, or otherwise unexposed or inaccessible for inspection.

BACRGROUND
Detection and location of fluid leaks in underground fluid-conveying pipes is frequency desirable to avoid unnecessary, time-conswning excavations and attendant costs. AS a result, the need has arisen ~or a reliable system which can be employed on the surface above an underground pipe for accurately locating the site of a fluid leak in the pipe before making an excavation.
Numerous leak detecting systems have been proposed prior to this invention, some for merely detecting the presence of a leak, others for both detecting and locating a leak in a fluid-conveying pipeline. Examples of these prior systems are described ;~ in United States Letters Patent 3,814,207 issued on June 4, 1974 to T. Kusuda et al, United States Letters Patent 3,055,209 issued on September 25, 1962 to J.M. Reid et al, United States Letters Patent 3,851,521 issued on December 3, 1374 to S.A. Ottenstein, United States Letters Patent 3,478,576 issued on Noven~er 18, 1969 to ~.G. Boyle, United States Letters Patent 3,807,220 issued on April 30, 1974 to S.A. Ottenstein et al, United States Letters Patent 3,800,217 issued on March 26, 1974 to D.A. Lowrance, United .

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l~)9Z2~4 States Letters Patent 3,750,711 issued on August 7, 1973 to J.T. Conklin etal, United States Letters Patent 3,744,298 issued on July 10, 1973 to N E
Flournoy et al, United States Letters Patent 3,738,156 issued on June 12, 1973 to H. Bosselaar, United States Letters Patent 3,690,150 issued on September 12, 1972 to J.S. Mullen, United States Letters Patent 3,575,040 issued on April 13, 1971 to H. Bosselaar, United States Letters Patent issued on February 9, 1971 to W.M. Bustin et al, United States Letters Patent 3,531,264 issued on September 29, 1970 to F.J. Greipel, United States Letters Patent 3,530,705 issued on September 29, 1970 to F.M. Lathrop, United States Letters Patent 3,508,433 issued on April 28, 1970, United States Letters Patent 3,500,676 issued on March 17, 1970 to M.N. Palmer, United States Letters Patent issued on August 19, 1969 to H. Bosselaar et al, United States Letters Patent issued on November 5, 1968 to H. Bosselaar et al, United States Letters Patent 3,413,653 issued on November 26, 1968 to F.M. Wood, United States Letters Patent 3,321,957 issued on May 30, 1967 to M. Blander et al, United States Letters Patent 3,308,424 issued on March 7, 1967 to A.B. Simpkins et al, United States Letters Patent 3,261,200 issued on July 19, 1966 to F.V. Long, United States Letters Patent 3,192,516 issued on June 29, 1965 to A.B. Simpkins et al, United States Letters Patent 3,170,152 issued to F.V. Long on February 16, 1965, United States Letters Patent 3,028,450 issued on April 3, 1962 to D.J. Manning, United States Letters Patent 3,626,750 to C.A. Talman, and ~` United States Letters Patent 3,008,934 issued on July 23, 1935 to A.C. Smith.
Other prior patents known to applicant, though not describing to fluid leak detecting systems, are United States Letters Patent 3,295,362 issued to F,M. Wood et al on January 3, 1967, United States Letters Patent 3,753,260 issued on August 14,1973 to A. Nelkin et al, United States Letters Patent .
3,756,275 issued on August 21, 1973 to N.G. Carter et al, United States Letters Patent 3,264,863 issued on August 9, 1966 to N. Mapopis, and United States Letters Patent 3,253,457 issued to W.E. Parkala et al on May 31, 1966.

Of the foregoing prior disclosures, Patents 3,814,207, 3,851,521, , ...

109~Z34 3,478,576 and 3,055,209 are of particular interest. The leak detecting systems described in these patents, however, are disadvantageous for one reason or another.
In Patent 3,814,207, for example, apparatus for measuring fluid velocity and complex circuitry for performing mathematical operations is re-quired for locating the site of a leak in a pipeline. In Patent 3,478,576, the apparatus is not capable of locating the site of a fluid leak and requires the insertion of a pig into the pipe to detect a leak. The system described in Patent 3,055,209 while capable of locating a leak in an underground pipe requires a sound generator to artificially develop a sound for locating the leak. The apparatus in Patent 3,851,521, on the other hand, is capable of detecting the location of the leak only at the moment of pipeline rupture.
SUMMARY AND OBJECTS OF INVENTION
This invention provides a novel leak detecting and locating method and apparatus which is subject to none of the foregoing disadvantages.
More particularly, this invention provides for a novel method and apparatus for reliably and accurately locating a fluid leak in an underground pipe or conduit.
In this invention, two transducers, such as geophones or other types of microphones, are adapted to be positioned at spaced apart regions over the undergrourdpipe on opposite sides of the suspected site of the leak to inter-cept the sound wave or vibration emanating from the escaping fluid. Electrical circuits connected to the transducers produce separate electrical signals. ~ -These signals are a function of the frequency of the intercepted sound wave and are miscorrelated to an extent that is determined by the location of the leak from the points at which the leak's vibrations are intercepted by the microphones.
According to this invention the extent of correlation between the two electrical signals is varied to establish maximum correlation between the signals, and the varied extent of the correlations is recorded or indicated lC~9Z234 to enable the leak's location to be determined from the place where the maxi-mum correlation occurs. In the illustrated embodiments the extent of cor-relation between the two signals is varied by variably time delaying one of the signals or at least samples thereof relative to the other of the signals or samples thereof. -The extent of correlation between the two signals is measured by a correlator which compares the two signals or their samples to determine if they are the same or different. A record of the resulting signal or cor-relation comparisons is accumulated, and these comparisons are displayed or graphed as a function of relative age between the signals that produced the comparisons to indicate the occurrence of maximum correlation.
In one embodiment the time delay of one signal relative to the other is accomplished by a variable length time delay line and a means for progres-sively varying the length of the delay line. In a second embodiment the time delay of one signal relative to the other is accomplished by a recirculating time delay line which delays samples of one signal relative to the other.
In the second embodiment mentioned above the samples of one signal are recirculated by the circulating delay line at a rate that is faster than the rate at which samples are periodically entered intothe circulating delay line. This embodiment is faster in operation than the first embodiment men-tioned above.
In the second embodiment the relative ages of the signal samples in the recirculating delay line will be in a scrambled but predetermined order.
Unscrambling of the data obtained from these signal samples is accomplished by use of an addressable memory and by addressing the memory to write in the correlation comparisons at predetermined locations in the memory. The memory -contents are then read out for displaying the stored data as a function of the relative age differences of the compared signals that produced the data.
The apparatus for delaying the signal samples in a scrambled order and then for unscrambling the data obtained from the samples may be employed . . . . . . .

10~3Z234 for purposes other than locating the site of the leak in a pipeline.
According to another feature of this invention, an envelope detector may be employed in each of the two electrical circuits mentioned above so that waveshapes following the envelopes of the microphone-produced electric waves are developed to more accurately pin point the location of the leak.
This invention may be employed to detect and locate both gas and liquid leaks.
With the foregoing in mind, a major object of this invention is to provide a novel method and apparatus for accurately and reliably locating the site of a fluid leak in an underground fluid-conveying conduit.
Another important object of this invention is to provide a novel method and apparatus for locating a fluid leak in an underground pipe by means of a correlation technique.
Still another important object of this invention is to provide a novel, leak-locating method and apparatus in which a vibration emanating from a fluid leak in a pipe is intercepted at two selected spaced apart points, in which the intercepted vibration at each of the interception points is converted into an electrical signal such that the miscorrelation between the two re-sulting signals is determined by the location of the leak from the interception points, in which the extent of correlation of the two signals or at least samples thereof is varied to establish maximum correlation between the signals by variably time delaying one of the signals or samples thereof relative to the other signal or samples thereof, and in which the varied extent of cor-relation is displayed or indicated to enable the leak's location to be de-termined from the occurrence of the maximum correlation.
Still another important object of this invention is to provide a novel leak-locating apparatus and method as in the immediately preceding object wherein the time delay of one signal relative to the other is accomplished by using either a recirculating time delay line or a variable length time delay line.
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~09Z234 Yet another important object of this invention is to provide a novel data treatment apparatus in which digital data bits are time delayed in a scrambled relative age order in a recirculating time delay line, and in which data obtained from the delayed, scrambled data bits is unscrambled.
Still another object of this invention is to provide a novel method and apparatus for locating a fluid leak in a fluid-conveying pipe by inter-cepting the sound wave or vibration propagating in opposite directions along the pipe from the leak to produce two electrical signals having a time delay which is related to the location of the leak between the interception points, and by delaying at least one of the two electrical signa~srelative to the other to cause maximum phase correlation between the two electrical signals.
A more specific object of this invention is to provide a novel method and apparatus for locating the site of a fluid leak in a fluid-conveying pipe by intercepting the sound wave or vibration propagating in opposite directions along the pipe from the site of the leak to produce two electrical signals having a time difference which is determined by the location of the leak between the two intercept points, by time delaying at least one of the two electrical signals relative to the other to cause maximum phase correlation between the two signals, by indicating the occurrence of the maximum phase -20 correlation, and by producing a distance measurement which is a function of the site of the leak from a known point at the time maximum correlation is produced between the two signals.
According to one aspect, the present invention provides in anapparatus for locating a fluid leak in an underground or unexposed pipe or conduit, first means effective upon receipt of a vibration caused by the leak for pro-` ~ ducing an electrical signal corresponding in phase and frequency to the re-ceived vibration, second means effective upon receipt of the vibration for producing a further electrical signal corresponding in phase and frequency to -~
the received vibration, electrical time delay circuit means electrically con-nected to said first means for variably time delaying one of said electrical "
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signals relative to the other to cause maximum mutual time correlation between the two signals, and means providing an indication of the time correlation between the time delayed one of said signals and the other of said electrical signals.
According to another aspect, the present invention provides in an appa-ratus for locating a fluid leak in an underground or unexposed pipe, first means for intercepting a vibration produced by the leak at two spaced apart points and for converting the vibration intercepted at each of said points in-to an electrical signal to provide two electrical signals that are miscorre-lated in time to an extent determined by the location of the leak from saidpoints, an electrical circuit electrically connected to said first means and including time delay means for varying the extent of time correlation between at least samples of said two signals to cause maximum time correlation there-between and means providing an indication of the variation of the extent of time correlation between the samples to enable the leak's location to be de-termined from the occurrence of the maximum time correlation.
According to a further aspect, the present invention provides in an apparatus for locating a fluid leak in an underground or unexposed pipe, means for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at said points into two digital signals that are related to the : location of the leak from said interception points, means for variably time delaying one of said signals relative to the other to vary the extent of cor-relation between the two signals, and means for indicating the varied extent of correlation to provide an indication~of the location of the leak.
According to yet another aspect, the present invention provides an apparatus for locating a fluid leak in an underground or unexposed pipe com-prising means for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of the pipe and for converting -the vibration intercepted at said points into two digital signals that are D

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related in phase to the location of the leak from said points, and means for : scanning at least a portion of said pipe between said points for the location of said leak by variably time delaying samples of one of said signals relative to samples of the other of said signals.
According to~ still another aspect, the present invention provides a method of locating a fluid leak in an underground or unexposed pipe compris-ing the steps of intercepting the vibration produced by the leak at two spaced apart points and converting the vibration intercepted at each of said points into an electrical signal to provide two electrical signals that are miscor-related in time to an extent determined by the location of the leak from said points, electrically processing at least one of said signals by varying the extent of time correlation between the two signals to cause maximum time cor-relation between the signals, and determining the location of the leak from the occurrence of said maximum correlation.
According to a final aspect, the present invention provides a method of locating a fluid leak in an underground or unexposed pipe comprising the : steps of intercepting the vibration produced by the leak at two selected points spaced apart along the path of the pipe and converting the vibration inter-cepted at each of said points into an electrical signal to provide two elec-trical signals that are miscorrelated in time to an extent determined by the location of the leak from said points, electrically processing at least one of said two signals by variably time delaying one of said signals relative to the .` other without changing the selected points at which the vibration is intercep-ted to vary the extent of time correlation between the signals, and determining : - -: the location of the leak from the variation of the extent of time correlation between the signals. .
The invention will now be described in greater detail with reference - to the accompanying drawings, in which: ~
Figure 1 illustrates a schematic circuit diagram constructed in -accordance with one embodiment of this invention and also one example (in ' "'' ' ', ' ,' ' ' ' , .

elevation) of the manner in which the geophones or other microphones are adapt-ed to be positioned for locating a fluid leak in an underground fluid-convey-ing pipe such as a water main or pipeline;
~: Figure 2 is a plan view of a typical water pipe distribution system t, in which the locations of the geophones or other microphones are shown in J` phantom lines;
; Figure 3 is a schematic circuit diagram of one of the variable length delay lines and the automatic scanning equipment shown in Figure l;
Figure 4 is a wave form diagram illustrating the degree of phase correlation between the two electrical signals mentioned above at different time delay increments;
Figure 5 is another wave form diagram illustrating the clock and correlated signals which are fed to one of the counters shown in Figure 1 for developing an indication-of the degree of phase correlation between the two previously mentioned electrical signals;
Figure 6 is a wave shape diagram illustrating the recordation which is made by the strip chart recorder in Figure l;
Figure 7 is a fragmentary schematic circuit diagram illustrating a modification in which envelope detectors are employed in conjunction with the circuitry of Figure l;
Figure 8 is a wave shape diagram illustrating the recordation of the strip chart recorder for the modification shown in Figure 7;
Figure 9 is a fragmentary schematic circuit diagram illustrating a -:
further embodiment of this invention in which only one delay line is employed;
Figure 10 is a schematic circuit diagram of another embodiment of this invention in which a recirculating delay line is used instead of a vari-able length delay line;
Figure 11 is a schematic circuit diagram of the recirculating control circuit, the jog control circuit and the parallel load circuit shown in Figure 10;

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' '~'' ~OgZZ34 Figures 12 and 13 are timing diagrams of various signals associated with the circuits in Figure 11;
Figure 14 is a partial schematic diagram showing the registers of Figure 10 and the relative ages of data bits in the stages of the registers;
Figure 15 is a schematic diagram of the memory section shown in Figure 10;
Figure 16, appearing on the same drawing sheet as Figure 3, illus-trates an example of the wave form that the apparatus of Figure 10 generates on an oscilloscope screen;
Figure 17 is a timing diagram of various signals associated with the circuit shown in Figure 15; and Figure 18 is a schematic circuit diagram of the circuit for select-ively adjusting the scanning resolution of the apparatus shown in Figure 10.
Detailed Description of the Drawings Referring to Figure 1, a fluid leak detecting and locating apparatus 20 incorporating the principles of this invention is shown to employ a pair of geophones 22 and 24. Geophones 22 and 24 are adapted to be positioned on the surface or other points at spaced apart regions which are over a buried or underground fluid-conveying pipe or pipeline 26 in which a leak has devel-oped. The spacing of geophones 22 and 24 is selected so that the suspected location of the leak is between the two geophones.
In the case of a water main or pipeline, geophones 22 and 24 are preferably removably positioned on or attached to water hydrants 28 and 30 ~see Figure 1) or stop boxes 32 and 34 (see Figure 2) on opposite sides of the ~` suspected location of the leak. Alternatively, geophones 22 and 24 or other microphones may be attached to probes (not shown) for insertion into the ground to locate the geophones or microphones in contact with or in close proximity to the pipe in which the leak has developed.
Geophones 22 and 24 intercept sound or mechanical vibrations which are produced by the water or other fluid escaping from the pipeline and convert .' ~,.
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~O~ZZ34 the vibrations into a.c. signals which are indicative of the amplitude and frequency of the vibrations. In place of geophones 22 and 24, it will be appreciated that any suitable type of microphone or transducer may be employed to convert the leak-producing sound waves or vibrations into an electrical signal.
The sound wave produced by the leak has an amplitude that is random-ly varying and a frequency that is partially tuned and partially randomly varying.
Apparatus 20 is portable and is normally carried to the suspected site of the leak. Alternatively, apparatus 20 may, if desired, be permanently located at the site of a pipe or pipeline to continuously monitor the pipeline for leaks.
As shown in Figure 1, geophones 22 and 24 are connected by separate signal processing circuits 40 and 42 to separate inputs of a correlator or parity detector 44 in a signal-analyzing portion of apparatus 20. Circuits -40 and 42 define separate signal channels for feeding correlator 44.
In the embodiment of Figure 1, circuit 40 comprises an amplifier :
46, a filter 48, a volume control 50, a polarity detector 52 and a variable length digital delay line 54. The a.c. signal voltage developed by geophone 22 is amplified by amplifier 46 and then fed to filter 48.
Filter 48 may be of the low pass or band pass type for eliminating or reducing background noise. The cutoff frequency or frequencies of filter 48 msy optionally be operator adjustable for obtaining optimum filtering action.The filtered signal at the output of filter 48 is fed by the volume ~`
control 50 to the polarity detector 52. Volume control 50 may be any suitable device, such as potentiometer (not shown), for selectively adjusting the ampli-tude of the a.c. signal voltage which is applied to the input of detector 52.
In place of volume control 50, a suitable automatic gain control circuit (not shown) of response time approximately 1 second may be employed to control the gain of amplifier 46 in such a manner that the strength or amplitude of the ~ ~ .

, Z2~4 amplified signal voltage at the output of amplifier 46 is stabilized within the correct operating range of the polarity detector 52 despite different leaks producing different sound intensities.
Polarity detector 52 may be of any suitable circuit design for de-tecting alternations of only one pre-selected polarity of the a.c. signal voltage In this embodiment, detector 52 detects the positively going alter-nations of the incoming a.c. signal voltage to develop a pulse wave form in which the pulses are of constant amplitude. Thus for the full duration of each positively going alternation of the a.c. signal voltage, the output volt-age of detector 52 will be positive at some suitable pre-selected value. For the full duration of each negatively going alternation of the a.c. signal volt-age, the output voltage of detector 52 will be at zero volts.
Detector 52 therefore converts or modifies the a.c. signal voltage - into a digital signal voltage in the form of a rectangular somewhat periodic wave as shown. It will be appreciated that any suitable circuit may be employed for effecting this conversion. Additionally, detector 52 may alter-natively be designed to detect the negative going alternations rather than the positive going alternations of the a.c. signal voltage. The pulse signal developed by detector S0 is fed to delay line 54.
Circuit 42 is preferably of the same design as circuit 40. Accord- -ingly, like reference numerals have been applied to designate like parts of circuits 40 and 42, with the reference numerals for circuit 42 being suffixed ~ `~
by the letter "a" to distinguish them from the reference numeral designations ` for circuit 40.
In circuit 42, the vibration-indicating a.c. signal produced by geophone 24 is amplified by amplifier 46a and then filtered by filter 48a in `
the same manner as described for circuit 40.
From filter 48a, the amplified and filtered a.c. signal voltage is fed by volume control 50a to polarity detector 52a. Polarity detector 52a, which is preferably the same as detector 52, detects the positive going alter-Z~3~

nations of the a.c. signal voltage to produce a pulse wave form in the same manner as described for detector 52. The pulse or digital signal voltage from detector 52a is fed to delay line 54a.
From the foregoing description it will be appreciated that detector 52 modifies the incoming a.c. signal from geophone 22 to a train of pulses ~indicated at 60 in Figure 1) having the same or substantially the same period and repetition frequency as the a.c. signal voltage. Additionally, the pulse signal voltage at the output of detector 52 ~ill change states from one pre- -selected value to another (which in this particular embodiment is from some suitable positive value to zero) at or substantially at zero cross-over of the a.c. wave form from geophone 22. - -Hence, the period and repetition frequency of the pulse wave form at the output of detector 52 ~ill be the same or substantially the same as the mechanical vibration or sound wave which is produced by the leak and received by geophone 22. In additlon, the phase ~f the pulse wave form at the output of detector 52 will be fixed relative ~o that of the vibration picked up or intercepted by geophone 22.
Detector 52a likewise modifies the a.c. signal from geophone 24 into a train of pulses (indicated at 62 in Figure 1) having the same period and repetition frequency as the a.c. signal voltage from geophone 24. Hence, the period and frequency of the pulse wave form fed by detector 52a to delay line 54a will be the same or substantially the same as that of the mechanical vi-brstion produced by the leak and picked up or intercepted by geophone 24.
Additionally, the phase of the pulse wave form at the output of detector 52a will be fixed relative to that of the vibration picked up by geophone 24.
Because the pulse wave forms developed by detectors 52 and 52a are indicative of the above-described characteristics of the vibration picked up by geophones 22 and 24, the phase difference between the two pulse wave forms will be a function of the location of the leak between the two geophones.
Assume, for example, that the leak in pipe 26 is located at point a (see D

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lOgZ234 Figures 1 and 2) which is some unknown distance dA from geophone 22 and some unknown distance dB from geophone 24. Since the velocity (c) of the propagated sound wave along pipe 26 is usually constant, the time (tA) required for the sound wave to reach geophone 22 will be proportional to the distance dA
(dA = c tA) and the time (tB) required for the same sound wave to propagate to geophone 24 will be proportional to the distance dB (dB = c tB). The time difference between tA and tB will therefore be proportional to the phase difference between the two pulse wave forms 60 and 62 which are developed by detectors 52 and 52a.
In accordance with this invention, the phase difference between the two pulse wave forms supplied by detectors 52 and 52a is analyzed by progres-sively delaying one of the pulse signals 60 and 62 relative to other in such a manner to phase correlate the two pulse wave forms (i.e., to bring the two pulse wave forms into phase with each other as much as possible) and by de-termining or measuring the degree or extent of phase correlation during the ~ -operation of the delaying one signal relative to the other. ~ -; The desired relative signal delay may be accomplished in one of two ways with the apparatus shown in Figure 1. First-, it may be accomplished by -selectively setting a zero delay into delay line 54a and by varying the delay in delay line 54. Alternatively, a fixed delay equal ~o the time required ` for the leak-produced sound wave to propagate the full length of pipe line 26 between geophones 22 and 24 may be entered into delay line 54a. Then, the -` delay in line 54 is varied relative to the fixed delay. This latter method of employing apparatus 20 has an advantage over the former method mentioned above because ~he latter method permits the full length of the pipe between the geo-phones to be scanned for the site of the leak without halt or interruption from one geophone to the other geophone.
As shown in Figure 1, the relatively delayed pulse signal voltages from delay lines 54 and 54a are applied to separate inputs of correlator 44.
t, ` 30 Correlator 44 may be any suitable circuit design for detecting equality or ' - 14 -Z2~

parity of the two incoming pulse signal voltages. In this embodiment corre-lator 44 is an exclusive NOR gate as indicated at 66 in Figure 3. Alternative-ly, an exclusive OR gate may be employed.
Thus, when there is equality or parity between the two incoming pulse wave forms at a given instant, the output of gate 66 will be high ~a logic 1). ~-Conversely, if there is unequality between the two incoming pulse wave forms at a given instant the output of gate 66 will be low (a logic 0).
From the apparatus thus far described, it will be appreciated that when the phase difference between the two pulse wave forms 60 and 62 is beyond a critical minimum phase difference, the summation of the pulse or logic 1 state durations at the output of gate 66 will be roughly 50% of the summations of both logic 0 and logic 1 states, indicating that no correlation exists.
As the phase difference between the pulse wave forms 60 and 62 is reduced and approaches zero by delaying one of the pulse wave forms 60 and 62 relative to the other, the above-mentioned percentage or ratio of the summation of the logic 1 state durations to the selected time interval increases as shown in Figure 4. When, the delay is sufficient to place the two pulse wave forms 60 and 62 substantially in phase with each other, the correlation between the two pulse wave forms is maximized, and the percentage or ratio mentioned above will become a maximum as also shown in Figure 4.
In Figure 4, the delayed pulse wave form at the output of delay line 54 is indicated at 60', the delayed or undelayed pulse wave form at the output -of delay line 54a is indicated at 62' and the output of gate 66 is indicated at 67.
In order to convert the digital signal produced by gate 66 into a meaningful analog read out the output of gate 66, a counter 70 is employed.
s In this embodiment counter 70 is preferably of the serial in/parallel out binary type having a suitable storage or bit capacity to count in a multipli-city of bits. The digital signal produced by gate 66 and clock pulses (indi-cated at 71 in Figures 1 and 5) of pre-selected constant repetition frequency '''1''~ ;
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are fed to separate inputs of an AND gate 69. The output of gate 69 is fed to the input of counter 70 to load the counteT.
The frequency of clock pulses 71 is preferably selected to be sig-nificantly higher than the highest expected frequency of the pulse wave forms 60 and 62 so that at least one and frequently several clock pulses occur dur-ing each time interval of any significant duration in which the output of gate 66 is high and during each time interval of any significant duration in which the output of gate 66 is low as shown in Figure 5. In this fashion the count loaded into counter 70 for a selected time period (which is equal to or less than the counter's bit capacity) will be proportional to the previously mentioned ratio of the summation of time intervals in which the output of gate 66 is high (a logic 1) to the total selected time period.
Whenever the output 67 from gate 66 is high (a logic 1) at the trail-~ ing edge of a clock pulse, the count in counter 70 will be advanced by one.
- Whenever the output 67 is low at a trailing clock pulse edge, the counter will not advance. Thus, for the example shown in Figure 5, the count in counter ~ -70 will be advanced by 5 for a total number of 9 input clock pulses. The total count loaded into counter 70 for the interval shown in Figure 5 will there-fore read out as 0101. Practical statistics require 21 to 2l6 counts to be stored in counter 70 at one time.
From the foregoing it will be appreciated that the pulse output wave form 67 is effectively recurrently sampled at a rate equal to the repetition rate of clock pulses 71. One example of a suitable clock pulse frequency is lkHz.
; The bits in the data word produced at the output pins of counter 70 - are transferred in parallel to input pins of a storage latch or memory latch circuit 72. Latch 72 may be of any appropriate conventional form and has an adequate number of stages for latching in and thereby memorizing the binary data word fed from counter 70 upon receiving a latching signal of proper logic state.

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When a latching signal or pulse is applied to latch 72, the multi-bit data word fed from counter 70 is transferred to and stored at output terminals of the latch. From here the stored data word is applied to a suit-able digital to analog converter 74. Converter 74 converts the digital in-formation into a d.c. signal voltage whose magnitude is proportional to the binary number which is represented by the data word.
The analog output signal voltage from converter 74 is applied to drive a graphic recorder 76 or a voltage meter 78, or both. Alternatively, other forms of read-out may be employed. Recorder 76 is advantageously of the strip chart type and is preferred because it permits the pipeline distance or footage being analyzed to be marked on the strip chart or to be displayed with or on the strip chart in a manner to indicate the distance of the detec-ted leak from a known location or point.
Latching and reset pulses are respectively fed to latch 72 and coun-ter 70 at the same pre-selected fixed repetition frequency. These latch and reset pluses may be developed by any suitable timing control or logic circuit.
, For example, a counter circuit may be employed to count the pulses 71 and to t ; produce the latch and reset pulses each time the count reaches a pre-selected amount which is not greater than the bit storage capacity of counter 70. The clock pulses 71 of appropriate repetition frequency may be developed by a suit-able frequency divider 79 which is fed by a master clock 80. Divider 79 may be of any suitable type for producing separate clock pulse trains at the vari-ous different repetition rates required by the circuitry. Master clock 80 may be an astable multivibrator for developing a square or rectangular pulse wave form.
From the foregoing it will be appreciated that the count in counter 70 is periodically transferred to and stored at the output of latch 72. With .:
each latching pulse, the new count at the latch's input is transferred to the output to replace the existing count. Immediately upon storing a new count at the output of latch 72, counter 70 is reset to zero by a reset pulse.

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lO~ZZ34 Counter 70 now begins a new count in a new time interval. At the same time, the old count, which is at this time stored on the output pins of latch 72 will be converted by converter 74 into a d.c. signal voltage to oper-ate an unshown pen motor or the like for driving a pen 75 (Figure 6~ in recor-der 76. Recorder 76 therefore records on a visible scale the counts periodi-cally read out of counter 70.
Thus, the record presented by recorder 76 will be a continuous curve ~see Figure 6, for example) which is indicative of the previously mentioned ratio of the sum of the time intervals in which the pulse output 67 is high to the total pre-selected time period which is set by the period or frequency of counter reset pulses (see Figure 5). As previously described, this ratio will change as the delay in delay line 54 is automatically changed in the manner shown in Figure 4.
As the phase difference between wave forms 60 and 62 is reduced and - --approaches a minimum by increasing the delay of one of the wave forms relative to the other, the magnitude of the measured value recorded by recorder 76 in-creases. When maximum phase correlation is achieved between the two pulse wave forms 60 and 62, the amplitude of the waveshape recorded by recorder 76 increases to a maximum as indicated at 81 in Figure 6.
From the foregoing description it will be appreciated that the written record produced by recorder 76 is indicative of the extent or degree of phase correlation between the pulse wave forms which are fed from delay lines 54 and 54a to gate 66. The analog read-out supplied by recorder 76 may therefore be regarded as a correlation ratio. The oscillations shown in Figure 6 occur because the leak sound frequency is partially tuned.
In this embodiment, the delay length in delay line 54 is automatical-' ly changed by progressive increments by a scanning apparatus 82 to progressive-ly phase shift the pulse wave form 60 relative to the pulse wave form 62.
Delay line 54 may be of any suitable circuit design for this purpose, one being illustrated in Figure 3.

' '" ''I ~, :, .

.:

lV~Z234 The delay line in Figure 3 is of the variable length shift register type and comprises a multiplicity of shift registers and a corresponding num-ber of multiplexers. Seven registers are shown for the purpose of illustration and are indicated at 83, 84, 85, 86, 87, 88 and 89. Registers 83-89 are of the serial-in/serial-out type in which data bit shifting takes place on a clock command. The bit storage capacity of registers 83-89 is in increasing order as shown, namely 1, 2, 4, 8, 16, 32 and 64, for registers 83-89 respectively.
Additional shift registers having higher bit storage such as 128, 256 and 512 capacity may be added.
The multiplexers mentioned above are indicated at 92, 93, 94, 95, 96, 97, and 98 in Figure 3 and may be of any suitable circuit design. Multiplexers 92-98 are serially connected as shown. In this embodiment each of the multi-plexers 92-98 comprises three NAND gates and an inverter connected in the manner shown to provide a first data input 100, a second data input 101, a control or selector input 102, and an output 104. The logic state of a signal on the control input 102 determines which of the two signals at inputs 100 and 101 will be fed to the output 104.
For each multiplexer it will be appreciated from the illustrated logic than when a d.c. signal voltage having a logic 0 state is applied to the control input 102, the circuit path between the data input 100 and the output 104 is enabled and the circuit path between the data input 101 and output 104 is disabled. Thus, for this condition, the signal at input 100 will be fed to output 104, and the signal at input 101 will not be fed to output 104. When -the signal applied to the control input 102 has a logic 1 state, the signal at input 101 will be fed to output 104, and the signal at input 100 will not.
As shown, the pulse wave form 60 from polarity detector 52 is fed to the serial input of shift register 89, which has the largest bit storage and ~ ~-also to input 100 of multiplexer 98. The serial output of register 89 is fed to input 101 of multiplexer 98, and the output 104 of multiplexer 98 is fed to the serial input of the next shift register 88 and also to input 100 of multi-, ' , ~ , , , ::

109~234 plexer 97.
The serial output of register 88 is applied to input 101 of multi-plexer 97, and the output 104 of multiplexer g7 is fed to the serial input of register 87 and also to input lO0 of multiplexer 96. The serial output of register 87 is applied to input 101 of multiplexer 96, and the output 104 of multiplexer 96 is fed to the serial input of the next shift register 86 and also to input 100 of multiplexer 95.
The serial output of register 86 is applied to input 101 of multi-plexer 95, and the output 104 of multiplexer 95 is fed to the serial input of the next shift register 85 and also to input 100 of multiplexer 94. The serial output of register 85 is applied to input 101 of multiplexer 94, and the out-put 104 of multiplexer 94 is fed to the serial input of the next shift regis-ter 84 and also to input 100 of multiplexer 93.
The serial output of register 84 is applied to input 101 of multi-plexer 93, and the output 104 of multiplexer 93 is fed to the serial input of the next shift register 83 and also to input 100 of multiplexer 92. The serial output of register 83 is applied to input 101 of multiplexer 92, and the output 104 of multiplexer 92 is fed to one of the inputs of gate 66 as shown.
To shift data through registers 83-89, clock pulses of suitable pre-selected repetition frequency are fed from frequency divider 79 to the clock or data shift inputs of registers 83-89. The repetition rate of these clock ` pulses applied may, for example, be on the order of lkHz.
Scanning apparatus 82 is a clock-driven binary counter 110 having a -sufficient number of stages to accommodate the number of shift registers in delay line 54. In this embodiment, counter 110 has two cascaded 4 bit stages ` lll and 112 to develop an eight bit word. Only the first seven bits are em-ployed for the illustrated circuit, however, inasmuch as there are only seven shift registers in the illustrated embodiment. Carry-over from state 111 feeds stage 112.
The 4-bit binary output pins of counter stage 111 are indicated at

2~

QA, QB, QC, and QD, and the binary outputs of stage 112 are indicated at QE, QF, QG and QH. Outputs QA-H increase in binary order, starting with the least significant bit at output QA and progressing to the most significant bit at output QH.
Outputs QA - QG are separately connected to the control inputs 102 of multiplexers 92-98 respectively. Thus, the least significant bit at the output of counter 110 is fed to the control input 102 of multiplexer 92, the second least significant bit at the output of counter 110 is fed to the con-trol input 102 of multiplexer 93, and so on to the connection feeding the most significant bit (in this case at QG) to the control input 102 of multiplexer 98.
Clock pulses supplied by way of generator 79 are fed to the clock or A in input pin of counter stage 111 to advance the count in counter 110 when power is applied from a suitable source 116 to clock 80 through a switch 118.
The repetition rate or frequency of clock pulses applied to the clock input of counter stage 111 is pre-selected and significantly less than the repetition frequency of clock pulses applied to the clock inputs of registers 83 - 89.
When the circuit shown in Figure 3 is first activated, a reset pulse is supplied to the reset pins of counter stages 111 and 112 by any suitable -means to reset counter 110 to zero. At the beginning of a scanning operation and before the first clock pulse is fed to counter stage 111, therefore, the starting state data word at output pins QA - QG will be 0000000 to provide zero time delay. Accordingly, the pulse wave form 60 from detector 52 will be fed without time delay directly and serially through multiplexers 98, 97, 96, 95, 94, 93 and 92 to gate 66.
After the elapse of a pre-selected time interval, following reset of counter 110, the first clock pulse is fed to counter stage 111 to advance the counter by one count. The output at pins QA - QG therefore changes to 0000001.
With this counter output, multiplexer 92 will be conditioned to gate data only from its input 101, while the multiplexers 93 - 98 remain in condition to gate `~ '`

the data only from their inputs 100. --Thus, the pulse wave form 60 now must be clocked through the 1 bit shift register 83. The pulse wave form 60 will therefore be delayed one bit time which is the time required to fill up the 1 bit shift register 83 at the lkHz clock rate on the line 126 (see Figure 3) feeding the shift registers.
At the lkHz clock repetition frequency, the pulse wave form 60 will be delayed 1 msec.
When the second clock pulse is fed to counter stage 111 to advance counter 110 to the second count, the output on pins QA - QG will change to 0000010. As a result, multiplexer 93 will now be conditioned to gate data only from its input lOl, while the remaining multiplexers will be conditioned to gate the data only from their inputs 100.
` Now the pulse wave form 60 must fill up the two bit shift register 84 at the lkHz clock rate before passing on. The pulse wave form 60 will therefore be delayed by 2 bit times or 2 msec.
When the third clock pulse is fed to counter stage 111 to advance the counter, the output states on pins QA - QG will change to 0000011. As a result, both of the multiplexers 92 and 93 will be conditioned to gate data only from their inputs 101, while the remaining multiplexers will be condi-tioned to gate data only from their inputs 100. ~-Thus, the pulse wave form 60 is now required to first fill up the 2 ` bit shift register 84 and then the 1 bit shift register 83 at the lkH7 clock ``
rate before passing on. The pulse wave form 60 will therefore be delayed by

3 bit times or 3 msec. `
When the sixty-fourth clock pulse is received to advance counter 70 by 64 counts, its output will be 1000000. Thus multiplexer 98 will be condi-tioned to gate data only from its input 101, while the remaining multiplexers will be conditioned to gate data only from their inputs 100. The pulse wave form 60 will therefore be required to fill up register 89 at the lkH~ clock rate before passing on. Wave ~orr 60 will consequently be delayed by 64 msec.

1 .

' ' ~, , lO~Z~

From the foregoing description it will he appreciated that the delay entered into del~y line 54 is incrementally and periodically increased at a constant rate to delay wave form 60 by incrementally increasing times in which the increments of time delay are equal (i.e., 1 msec. for this example~.
In this embodiment, the repetition frequency of clock pulses 71 is desirably much faster than the repetition frequency of clock pulses fed to counter 110. For example, where the repetition rate of clock pulses on line 126 is lkHz, the repetition frequency of the clock pulses fed to counter 70 may be lkHz, and the repetition frequency of clock pulses fed to counter 110 may be l Hz.
The reset pulses for counter 70 and the clock pulses for counter llO
are conveniently made the same.
It will be appreciated that operation of the apparatus thus far described could be initiated manually be manually feeding one clock pulse at a time to counter llO and be selectively initiating the supply of the desired number of clock, reset and latch pulses for counter 70 and latch 72 for each clock pulse delivered to counter llO.
The circuit design for delay line 54a may be the same as that just described for delay line 54. The delay selectively entered into line 54a by the operator before initiating operation of apparatus 20 may be either zero or the time required for the leak-produced sound wave to propagate the selected -spacing between geophones 22 and 24 as previously mentioned. Any suitable equipment may be employed to conveniently enter the selected delay into delay line 54a.
In this embodiment the manual entry of a selected delay into line 54a is accomplished by a conventional thumb wheel selector 130 (Figure 1).
Selector 130 has a multiplicty of manually manipulatable thumb wheels 131 for entering a multi-digit decimal number representive of a selected distance or footage. The electrical signals developed by the thumb wheel entries are transferred in parallel to a suitable BCD-to-binary converter 132 which has a 13 :' .. . . .
. . . . ,, .. : . ..
. .

lO~ZZ~4 multi-bit output similar to that of counter 110. Each of the bit outputs of converter 132 is fed to a different multiplexer control input ~101) in the delay line 54a in the same manner as described for the connections of the out-puts of counter 110 to multiplexers 92 - 98. Data shifting clock pulses are fed to the unshown shift registers in delay line 54a in the same manner de-scribed for delay line 54. The data-shifting clock pulses for delay line 54a are preferably taken from the output of generator 79 which feeds the clock ` pulses to shift registers 83 - 89.
For the purpose of the following analysis and operation of apparatus 20 the following designations are employed:
tA = the time required for the sound wave emanating from the leak to reach geophone 22.
tB = the time required for the sound wave emanating from the leak to reach geophone 24.
tAA = the time delay in delay line 54.
- tBB = the time delay in delay line 54a.
- The pulse wave forms 60' and 62' will be in phase with each other ~ -to provide maximum correlation when the following relationship is established:
tA + tAA = tB + tBB
If zero delay is entered in delay line 54a ~i.e., tBB=0) and tB is greater than tA~ then the time delay t M required to bring wave form 60 in phase with wave form 62 will be:
tM = tB ~ tA ~2) The effective point or location of pipe 26 being analyzed or scanned for maximum phase correlation at any given moment in the operation of appara-; tus 20 is determined by the difference between the delay times t M and tBB.
For example, if tM and tBB are zero or otherwise equal, then the location of the pipeline being analyzed or correlated is midway between the spaced apart geophones 22 and 24. This is substantiated by the fact that maximum correla-tion and, hence, maximum read-out on recorder 76 will occur for t M = tBB if ~r~

.. .

l~Z~3~
/
the site of the leak is midway between geophones 22 and 24.
If the delay time tAA is increased to equal the time required for the sound wave to propagate one-half the pipeline length (1) between the two geophones and tBB = ~ then the location of the pipe being analyzed or scanned for maximum correlation will be one-fourth of the pipeline length (i.e., the length between geophones 22 and 24) as measured from the midpoint of the pipe-line length 1 in the direction of geophone 22. If the delay time tAA is further increased to equal the time required for the leak-produced sound wave to propagate the full length of pipe 26 between geophones 22 and 24 and if tBB = - then the location of the pipe being analyzed or correlated will be at the location of geophone 22.
From the foregoing it will be appreciated that if the delay time in line 54a is set to zero (tBB = 0), only the half of the pipeline length ex-tending from the pipe's midpoint between the geophones to geophone 22 may be analyzed or scanned with the arrangement of geophones shown in Pigure 1. In order to analyze the remaining half of pipe 26 for the condition where tBB is set to zero, one can switch geophones 22 and 24 to locate geophone 22 to the right of the leak in the original position of geophone 24 and to locate geo-phone 24 to the left of the leak in the original position of geophone 22.
The switching of geophones 22 and 24 may be avoided simply by selec-tively setting the time delay tBB in delay line 54a to equal the time required for the sound wave emanating from the leak to propagate the length of pipe 26 between geophones 22 and 24. With this delay in line 54a then the pipe loca-tion being scanned or analyzed when t M = will be at the location of geo-phone 24. As the delay time tAA is automatically incrementally increased with ; this setting of tBB the location of pipe 26 being analyzed or scanned is ad-vanced toward geophone 22, and when tAA is increased to equal or approximately equal to the time required for the leak-produced sound wave to propagate twice the length of pipe 26 between geophones 22 and 24, then the pipe location being analyzed or scanned will be at the location of geophone 22.

- 25 - `~

.

10'3ZZ3~

Thus, by selectively setting the delay time in line 54a to equal the time required for the leak-produced sound wave to propagate the length of pipe 26 between geophones 22 and 24, the entire length of the pipe between the two geophones may be scanned by increasing t M from zero to a delay equal to the time required for the leak-produced sound wave to propagate twice the length of the pipe between the geophones.
From the foregoing description it will be appreciated that the loca-tion of the pipeline being scanned at a given instant may be found from the following equation:
( M BB)/2 (3) where d = distance measured from the midpoint of pipe 26 between the two geophones, and c = speed of sound in water in the pipe.
If d is computed to be a positive number from equation (3), then the pipe location being scanned is between the midpoint of the pipe and geophone 22. If d is negative then the pipe location being scanned is between the mid-point of pipe 26 and geophone 24.
To fix the location of the leak, apparatus 20 includes a counter circuit 140 which drives a display unit 142 which is preferably, but not necessarily, of the digital type. For example, a digital LED display may be employed.
Counter circuit 140 is driven in step with counter 110 during a scanning operation to advance by a pre-selected number each time counter 110 is advanced by the count of 1 to incrementally increase or advance the time delay in delay line 54. For a predetermined speed of sound in a given medium (say, water essentially at rest in pipe, for example), counter 140, and more particularly display unit 142, will be advanced with each clock pulse by an ~ -amount approximately equal to ~d/2 where ~d = ~t~c), and where:
~t = the incremental time delay entered into delay line 54 for each lO~Z;Z~4 clock pulse 71 (namely 1 msec for this example);
c = the speed of sound in the selected medium; and ~d = the distance over which the sound propagates for the time ~t.
To advance counter 140 in a scanning operation a pulse train 73 hav-ing an appropriate repetition frequency may be supplied from frequency divider 79 to counter 140. Alternatively, the clock pulses 71 may be employed to advance counter 140 so that each time the delay in delay line 54 is increment-ally shifted, or more specifically increased, by counter 110, the count in counter 140 will be advanced by the desired, predetermined amount.
From the foregoing it will be appreciated the display unit 142 pro-vides a read-out of a distance measurement to continually indicate the loca-tion of the pipeline being scanned or analyzed during a scanning operation.
The read-out provided by display unit 142 may be in any suitable units of ; length such as feet or meters.
' Taking the particular operating mode in which the time delay entered into line 54a is the time required for the leak-produced sound wave to propa-gate the length of pipe 26 between geophones 22 and 24, the read-out furnished ` by display unit 142 will be zero when the output of counter 110 is zero ~i.e., 0000000) at the start of the scanning operation when the delay tAA entered t ~ 20 into line 54 is zero. It is now known that the pipe location being scanned and read-out on recorder 76 at this moment is zero feet from geophone 24. The operator may then write or record this distance measurement on the recorder's strip chart as shown in Figure 6 to correlate the distance read-out with the correlation waveshaping being made by recordeT 76.
When counter 110 is advanced by one count to increase the time delay ~` tAA by one-preselected increment ~t(namely, 1 msec. in this example), display unit 142 will be advanced by counter 140 to indicate the distance of the pipe-line location from geophone 24 which is currently being scanned at the 1 msec.
¦ delay, Thus, display unit 142 continues to read out the pipeline location being scanned for the entire scanning operation.

~ D

l~gZ2~4 The operator advantageously periodically marks the distances indi-cated by display unit 142 on the strip chart in recorder 76 to thus provide a ` precise determination of the location of the leak in the manner shown in Figure 6. To facilitate accurate marking of distances on the strip chart of recorder 76, the distance increase pulses 73 may advantageously be employed to operate an additional pen motor (not shown) which drives a second pen 144 in recorder 76. Distance pulses 73 before being applied to the additional pen motor are advantageously frequency divided by a frequency divider 146 (Figure 1) to supply pulses at a reduced, pre-selected frequency. For example, frequency divider 146 may divide by ten so that one out of every ten successive distance pulses 73 is applied to cause pen 144 to place a mark or blip on the recorder strip chart as indicated at 150 in Figure 6. The operator takes a reading of display unit 142 when each mark 150 is made and records the read-out or the mark as shown in Figure 6.
To locate a leak with apparatus 20, the operator first places geo-phones 22 and 24 at appropriately spaced apart places on the surface above ' pipe 26 in the manner previously described 90 that they are on opposite sides of the suspected location of the leak and over spaced apart regions of the underground pipe. Preferably, geophones 22 and 24 are positioned on or re-movably attached to such structure as the fire hydrants 22 and 24 or the stop boxes 34 and 32 in the case of a water main supplying water to buildings.
Power for the circuitry is then readied, and at this time reset signals are applied to each counter in the circuit to reset or clear the counters to zero ; in preparation for a scanning operation. The reset signals in preparation for a scanning operation may be produced by any suitable conventional means.
In addition to clearing all of the counters, the selected time delay -tBB is entered into delay line 54a by manipulation of thumb wheels 131 in selector 130. For example, assume that the entered time delay tBB is equal to the time required for the sound wave emanating from the leak to propagate the length of pipe 26 between geophones 22 and 24.

r~

.. ..

lO~Z234 Thereafter, the circuit is energized as by closure of switch 118 to start the automatic scanning operation which was previously described. The operator observes the reading on display unit 142 and the strip chart record-ing in recorder 76 and preferably marks the distances displayed by unit 142 for each of a selected number of the markers 150 made on the recorder's strip chart by pen 144 in the manner shown in Figure 6.
Assume that the site of the leak is at location "a" between the two geophones at a distance of about 120 feet from geophone 24. The maximum amplitude 81 of the strip chart recording will therefore occur at or near the 10 marker 150 which was made when the reading of display unit 142 is at or near 120 feet.
Having now determined the site of the leak, the distance of 120 feet may be measured along the path of the pipeline from geophone 24 to establish the location which is over the leak. Alternately, in the example shown in Figure 6 in which the spacing between geophones was selected to be 200 feet, the distance of 80 feet may be measured from geophone 22 to locate the site of the leak. Excavation may now be made at the proper location to uncover the leaking portion of the pipeline for repair or replacement.
If the site of the leak happens to be vertically below geophone 24, 20 then the maximum amplitude (81) on the recorder's strip chart will occur at a ~ ~ -reading of zero feet from geophone 24. If the site of the leak happens to be vertically below geophone 22, then the maximum amplitude (81) will occur at the maximum length of the scanned distance which, in the example of Figure 6, occurs at 200 feet from geophone 24 or zero feet from geophone 22.
If the actual site of the leak happens to be in an adjacent pipeline portion, say to the right of geophone 24 as viewed from Figure 1, then the spparent site of the leak indicated by the strip chart's maximum amplitude (81) will occur at the zero foot marker (150) on the strip chart. To distin-guish whether the leak is actually directly below geophone 24 or in the adja-30 cent pipeline portion, geophones 22 and 24 are transferred to the adjacent " , .
.. . . . . .
' ~ ' ' ' ': ' ' " ' ' . ' ~ :

lO~Z~

portion as by locating geophone 22 at the Griginal location of geophone 24 and locating geophone 24 farther to the right as viewed from Figure 1 With these new geophone positions the adjacent pipeline portion is automatically scanned in the same manner as previously described. If the maximum amplitude 81 on the strip chart now occurs between the two geophones, then the true site of the leak is located in the adjacent pipeline portion. On the other hand, should the maximum amplitude 81 occur at the new position of geophone 22, then the actual site of the leak is established to be vertically below geophone 22.
If the second scanning operation indicates the site of the leak to be vertical-ly below geophone 24, then the next adjacent pipeline portion to the right of geophone must be checked. This procedure is repeated until the recorder 76 indicates that the site of the leak is between the two geophones. The same procedure can be applied to locate the actual site of a leak in the case where a first scan indicates that the apparent site of the leak is vertically below geophone 22.
An ambiguous location of a leak may also occur in a case where a further fluid-carrying pipe 151 is connected to pipeline 26 as shown, for example, in Figure 2. Assume that the actual site of the leak is at location b in pipe 151, and pipeline 26 is first scanned with apparatus 20 by placing -geophones 22 and 24 on opposite sides of the intersection at stop boxes 32 and 34 respectively. For this condition, the maximum amplitude 81 in the strip chart read-out will occur at the juncture of pipe 151 with pipe 26 (at location c).
To determine the actual location of the leak under these circumstan- -ces, geophone 24, for example, could be transferred to stop box 36. Apparatus 20 is then operated in the manner previously described to scan continuously the section of pipe 151 from stop box 36 to location c and the section of pipe 26 from location c to stop box 32. If the maximum amplitude (81~ of the strip chart read-out falls at location b along pipe 151 then the actual site of the s~30 leak is at location b. If, contrary to the above assumption, the maximum ~ - 30 -. ,.
- .

1~ 4 amplitude (81) of the strip chart read-out occurs at location c then the actual location of the leak is truly at location c.
To more accurately determine the location of a pipeline leak, enve-lope detectors 160 and 160a may be added to circuits 40 and 42 respectively as shown in Figure 7. Each of the detectors 160 and 160a comprises a full wa~e rectifier for rectifying the inc~ming a.c. signal in its associated circuit and also a filter (such as an RC filter) for smoothing the rectified waveform to produce the slowly varying envelope shown in Figure 7. The rectifiers in detectors 160 and 160a may be of the semiconductor diode type. `
As shown, detector 160 is connected between volume control 50 and polarity detector 52. Likewise, detector 160a is connected between volume control 50a and polarity detector 52a.
The output of envelope detector 160 is coupled to the input of polar-ity detector 162 by a capacitor 162 to remove the d.c. component from the detected waveform. Similarly, the output of envelope detector 160a is coupled by a capacitor 162a to the input of polarity detector 52a to remove the d.c.
component from the detected waveform at the output of detector 160a.
The a.c. signal developed in each of the circuits 40 and 42 will vary in amplitude and frequency due to background or extraneous noise and variations ~ `
in the pitch and volume of the sound emanating from the leak. Each of the detectors 160 and 160a is effective to produce a waveshape which follows the envelope of its associated incoming a.c. signal. These envelope waveshapes therefore have a frequency which is considerably less than that of the incoming a.c. signals which are fed to detectors 160 and 160a. Consequently, the posi- ~ -` tive alternations of the capacitively coupled envelope waveshapes will be many times longer in time than the positive alternations of the a.c. signals which ~ -are fed to detectors 160 and 160a. The durations of the positive and 7ero voltage levels at the outputs of polarity detectors 52 and 52a are therefore much longer as compared with those in the embodiment of Figure 1. In other words, the periods of the pulses waveforms fed to gate 66, though varying, i - 31 -.

109Z23~

are much longer than those developed in the embodiment of Figure 1. This plus the completely random nature of the amplitude variations has the effect of producing a strip chart recordation as shown in Figure 8.
In Figure 8, the strip chart curve is devoid of the oscillations which occur in the curve of Figure 6 and rises to a peak 164 at the site of the leak.
The oscillations which occur at and near maximum correlation in the strip chart curve shown in Figure 6 are due to the repetitive recurring cor- -relation of the two waveforms 60' and 62' which are partially tuned with respect to each other.
If no delay is to be imparted to wave form 62 (i.e., tBB=0~, then the circuit of Figure 1 may be simplified in the manner shown in Figure 9 and yet facilitate the automatic scanning of the full pipeline length between geo-phones 22 and 24 without changing the positions of the geophones.
In the embodiment of Figure 9, delay line 54a is replaced with a double pole double throw switch 170. The remainder of the circuit for Figure ` 9 is the same as that shown in Figure 1.
As shown in Figure 9, polarity detectors 50 and 50a are connected to separate input terminals of switch 170 which provides switchable connections to delay line 54 and correlator 44. The output of delay line 54 is connected to one input of gate 66 as before. In this embodiment, however, the other in-put of gate 66 is connected by a wiTe 172 to an output terminal of switch 170.
In one position of switch 170, detectors 50 and 50a will be respec-; tively connected to delay line 54 and through wire 172 to correlator 44. In the other position of switch 170, the connections are reversed so that detec-tor 50a is connected to delay line 54 and detector 50 is connected through wire 172 to correlator 44.
. Considering operation in the first position of switch 170 mentioned above, the portion of pipe 26 scanned by apparatus 20 will extend from the mid-point of pipe 26 between the two geophones 22 and 24 to geophone 22 as pre-~. , .

-~9ZZ~

viously described. In this first position of switch 170, wave form 62 will be fed without time delay to correlator 44 by way of wire 172, and wave form 60 will be fed to the other input of correlator 44 by way of delay line 54.
Wave form 60 will therefore by delayed in progressively increasing increments as previously explained.
If the leak in pipe 26 is between geophone 22 and the midpoint of pipe 26 between the geophones, recorder 76 and display unit 142 will indicate the proper location of the leak. If the leak happens to be in the unscanned half of the pipe, then the maximum phase correlation indicated by recorder 76 will not appear in the scanned distance.

, .

, ... . .. .

-' .. . .
:, ., .. , , . : , , . . . : .

2~3~

To scan t~le G~her hcl],f o~ pipe ~6 ext~ndi,ng frorn ~-he m,idpoint of pipe 26 between t~le two geophones to gcophone ~4 switch 170 is thrown to its other position wi,thout mGving the geophones from their original positions. ~ow, wave form 60 will be fed without any delay to correlator 44 by way of wire 172, and wave form 62 will be fed to correlator 44 by way of delay line 54. Wave form 62 will now be delayed in progressively increasing increments in the same manner as previously described for wave form 60.
Thus, the entire length of pipe 26 between geophones 22 and 24 may be automatically scanned in two stages without requiring a change in the positions of the geophones.
While display unit 142 provides a specific location , of the leak, it is equally clear that the phase correlation ,' record or waveshape produced by recorder 76 provides an indica-tion of the location of the leak in that it will indicate , whether or not the leak is between the selected locations of ' geophones 22 and 24. It also will be appreciated that instead of starting with zero or minimum delay in delay line 54 and progressing incrementally to a maximum delay, the scanning operation may initiate with a maximum delay in line 54 and progress to zero or some other minimum. Additionally, analog ,, delay lines may be employed in lieu of the illustrated digital delay lines.
In the preceding embodiment the variable time delay , line 54 is shown to be of the non-circulating variable length ; shift register type for variably time delaying the digital data 62 relative to the digital data 60. This type of variable delay line is of simplified construction, but relatively slow in operation. The slow operation mainly results from the need to accumulate samples of a large number correlation comparisons in counter 70 for each increment of delay in line 54 in order.

~ , ' , -,: ' ,, ., . , . ~
- , l~Z2~4 ~s compal-cd with 1ll~ precc~irlg embodlmc~t, the leclk detecting apparatus shown in Figures lO-15 is considerably more rapid in opera~ion, thus enabling ~reater pipe footagc to be scanned for leaks in the course of a working day. The more rapid operation is accomplished in part by employing a circu-lating delay line 200 (also called a recirculating delay line) in place of the non-circulating variable length delay line 54.
To the extent ~hat the apparatus of Figure 10 is the same as the apparatus in Figure 1, like reference charac-ters have been employed to designate corresponding circuits and parts.
As shown in Figure 10, geophone 22 feeds data channel A, and geophone 24 feeds data channel B. Channel A, as pre-viously described, includes amplifier 46, filter 48, volume control 50, and polarity detector 52. Channel B, as previously ~- described, includes amplifier 46a, filter 48a, volume control. ~ -: .
50a and polarity 52a. With this circuitry, the analog signal fed into each of the two data channels is conditioned and con-verted into a digital or binary signal in the same manner as described in the embodiment of Figure 1. -~
As shown in Figure 10, channel A further includes a non-circulating shift register 204, the circulating delay line -200, and a l bit shift register in the form of a clocked, type D flip-flop 206. Delay line 200 variably time delays the data signal in channel A relative to the data signal in channel B.
~or accomplishing this function, delay line 200 may be a recir-culating shift register (also called a circulating shift . register) as indicated at 208. The output of register 208 is tied around to its input to cause the data in the register to ~' ,~,~

.:
.

.

l~ZZ34 recircula~e un~er thc control o~ a circulating con~rol ci~cuit 209.
The len~th of recirculating rcgister 208 is pre;elec~ed and is identified by the character n'. In order to fill up the n' length of register 208 with data at every location in the re-gister, it is necessary to inject data into every successive i'+l location, where n' and i'+l have no common factors. The apparatus to be described accomplishes this purpose.
The binary data (see signal 62) fed to the input of shift register 204 is serially clocked into and shifted throu~h the shift register at a clock pulse rate of l/TsLow where TSLow is frequently referred to as the bit time period (or simply the bit time) and is the period of clock pulses fed from a count-er output stage of a master clock 210.
Clock 210 is made from a series of synchronous count-ers to provide separate clock Pulse outputs of different pre-selected periods. In this embodiment, the fastest or smallest clock output period is TFAST/2, followed by TFAs~, then by 2TFAsT and so on up to 2 TFAST as shown in Figures 10 and 11.
The clock pulse period at the TFAST output is twice as great as ` `the clock pulse period at the TFAST/2 output. Likewise, the clock ~ulse ~eriod at the 2TFAST outPut is twice as lonq as the clock Pulse period at the TFAST outPut~ the clock pulse period at the 4TFAST output is four times as long as the clock pulse period at the TFAST output, and so on. Accordingly, the illus-trated designations of clock pulse outputs indicated the periods of the different clock pulse outputs relative to the period TFAST.
-Data shifted through register 204 is gated through control circuit 209 and entered into register 208 at the end of each clock pulse period TSLow~ In this embodiment, the TSLow clock pulses are taken from the 64TFAST output of clock 210. As will be described in detail presently, control circuit 209 ' ''. ' ~ ' . ' ' :

~092234 oT~era~es to l-ltomentarily stop recircu]a~iorl of da~a ;i~ound re-~is~cr 20~ at the end ~f each clock pulsc period TS~ow in order to enter a new or fresh data bit into register 208 and to drop the oldes~ data bit from the register.
In addition to being recirculated, data the the out-put of register 208 is clocked throuyh flip-flop 206 to one of the inputs of the exclusive NOR gate 66 which, as previously described, defines a correlator 44.
The contents in register 208 are shifted under the control of a jog control circuit 218. Throughout each re-curring period of TSLow~ circuit 218 normally shifts the con-tents in register 208 at a constant clock pulse frequency of l/TFAsT excePt for one interval in which the shift frequency is doubled to 2/TFAsT. The purpose of this increase will be explained later. Clock pulses for shifting the contents of register 208 at the rate of l/TFAsT are supplied by the TFAST
output of clock 210. The period of these clock pulses may be referred to as the TFAST bit time period or simply the TFAST
bit time.
For reasons to be explained later, the clock period TFAST is much smaller than the clock period TSLow. ~ence, the rate at which data is recirculated through register 20~ is much faster than the rate at which fresh data is injected into register 208.
Register 208 is provided with a fixed length of n' --bits where n' is an integer much greater than zero and con- -veniently equal to 2 raised to some pre-selected powex (i.e., n'=2n). For example, n may conveniently be selected to be 9 so that register 208 will be 29 or 512 bits long. The selected length of register 208 sets the number of delay line partitions in the scanning operation.
Still referring to Figure 10, the data channel B

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further illcl~ld~s a nc~n recirculatin-J s~ri~l i,nput/p~lrallcl output t~pe s~lift register 220 and a circulating delay line 202. Dclay line 202 may be a rccirculating .shift regi,~tcr (also called a circu],ating shift register) as indicated at ~22. The output of register 222 is tied around to tis input to cause the data ]oaded into the register to continuously recirculate.
In addition to clocking register 204, the TSLo~
clock output is applied to the clock input of register 220.
Thus, digital data (see signal 60) fed to the input of register 220 is serially clocked into and shifted through register 220 at the clock pulse rate of l/TsLow. As will be described in detail presently, a pre-selected number of bits in register ` 220 are periodically parallel loaded into register 222 under '~ the control of a parallel load circuit 224.
' In addition to being recirculated, the data at the output of register 222 is fed to the second input of gate 66 for comparison with the binary signal from flip-flop 206. The correlations detected by gate 66 are placed in memory in a memory section 228. The memeory contents are read out after ' 20 the completion of the scanning operation to establish the location of the leak. Memory section 228 and its operation will be described in detail later on.
The TFAST output of the master clock 210 is also used to clock register 222. Thus, the data in register 222 is re-circulated at the same rate (namely l/TFAsT) as the data re-circulates through register 208. Register 222, however, has a ' ' fixed bit length which is less than the bit length of register , 208 and which bears a predetermined relationship to the length ` of register 208. ~ ~ ' As shown, register 222 is 2n i bits long where i is '~

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a sc~lectc~ int~cr ~ e~er ~h<ln ~ero, ~ less th,ln thr selected -~alue of n (i.c., O~i Cn) . E'or n-9, orJe satisact~ry value of i is 6. Thlls, for tl-is numexical ~xamplc, the length of register 222 will be 29 6 or 8 bits.
The total length of register 220 is the sum o~ 2n i and 2n 1 bits, where only the 2 i bits are used to periodically parallel load register 222. Register 220 may be regarded as having two sections 230 and 232, where sections 230 has a length and parallel output of 2 bits and where section 232 has a serial output feeding section 230 and a length of 2n i bits.
For the numerical example given above, section 230 will be 8 bits long, and section 232 will be 256 bits long.
Register section 232 is employed to delay the digital ; data in channel B by a fixed interval equal to 256xTsLow or 256TSLoW bit times. The purpose of this delay is the same as that described for delay line 54a in the first embodiment.
- Thus, delaying the channel B data by 256 bit times causes the , apparatus of Figure 10 to scan a length of pipe 26 between geo-phones 22 and 24. Without this delay the leak detecting appara-tus will scan only from or to the midpoint between the two geo- -phones. -`
The purpose of register 204 is to offset or cancel the time delay that is caused by register section 230. To accomplish this register 204 is provided with a length of -w i bits and is clocked at the same rate (namely ljTSLow) as register 220. Accordingly, the net time delay that register 220 causes in channel B will be 2 or 256TSLoW bit times- ~ -From the description thus far it will be appreciated that reqister 208 provides 512 presentations of data of different relative ages in 512TE,AST bit times. Register 222, on the other hand, recirculates the channel B data once in 8 TE~AST bit times.
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~or every cornr~ete S]2 bit rec~culatin~ cycle macle by rcgisler 20~, re~ister ''22 com}?letes 2i or 64 cornplete g l~it cycles.
~ach data bit in register 222 will thus be colnpared with one-eighth of the contents in re~ister 208.
In this embodiment the clock pulse period ratio of TSLow/TFAsT is set or determinccl by the selected value of 2i.
That is, the values of TsLow and TFAST are so selected that the ratio TSLow/TFAsT equals 2 , which in the foregoing n~merical example is 64.
Since the values of TSLow and TFAST a that TSLow-2iTFAsT, it is apparent that a fresh data bit will be entered into register 208 at every recurring bit time inter-val of 2 TFAST. For i=6, the new data will therefore be entered at every 64th bit time period of TFAST. ~wo sequential opera-tions actually take place on every 64th bit time period of TpAST.
First, recirculation of data around register 208 is inhibited by circuit 209 and the contents in register 208 are -~
shifted one bit to the right from the register's input to the register's output. This shift enters the new data in the leftmost stage of register 208 and drops the binary data bit in -the register's rightmost stage. In the second operation, which follows the first operation, the recirculation of data around register 208 is enabled and the register contents are shifted right by one stage to recirculate one data bit.
To cause these two operations to sequentially occur " at every 64th TFAST clock pulse (i.e., at 2iTFAST), two shift pulses having a frequency of 2/TFAST are applied to register 208 instead of a single TFAST clock pulse. The clock pulses of frequency 2/TFAST are obtained from the master clock output

-4~ . ' , 1~2~4 wllicll is indic(lted at Tl~ST/7. '['i~ it tiTrle period Gf T~,~S,~/2 is equal to one-half of the TF~ , cloc~. ~ulse ~eriod. Ik should be noted that counting from zero, the two 'rFAsT/2 clock pulses will he applied in the 63rd bit tirne period of TF~5T.
For performing the two operations described ahove, circuits 209 and 218 may be of any suitable design, one example being illustrated in Figure 11.
Referr:ing to Figure 11, the recirculating control circuit 209 is shown to comprise a JK flip-flop 234, NAND
gates 236, 237 and 238, AND gates 240 and 241 and a NOR gate 242. Gate 236 detects a master clock output of 1111102 or 621o. In this regard it will be observed that the outputs of the clock 210 represent a binary number or word in which the master clock's 2TFAsT output is taken as the least significant digit and the clock's 2nTFAST output is the most significant digit. This binary number is designated in the following des-P CLOCK NCLocK increases by the binary count of 1 ; for each TFAST clock pulse. In other words, NCLocK is a count number of TFAST clock pulses supplied by clock 210 At the beginning of a cycle, NCLocK changes from 1111111112 to 2 at the start of the first TFAST clock pulse. The state of NCLocK thereupon changes to 12 at the second TFAST clock pulse, then to 12 at the third TFAST clock ` pulse, and so on. ~ -In order to detect the 1 states in the five most significant digits of 1111102, the following master clock out-puts are connected to and feed separate inputs of N~ND 236:
4TFAST' 8TFAST' 16TFAST' 32TFAsT and 64TFAsT. In order to : detect the 0 state in the least significant digit of 1111102, a further input of gate 236 is connected by way of an inverter lO!~Z~3~

2~ to thc 2r~ sT ~ }JIjt ~f c~)(k 21() ~ ~,}10~7n, ~;h~i ~'r OlltpUt of cloc~. 210 is the lea,t signi~icant digi~ in ~CIOCK
as previouslv mentioned. With this lo~ic, the output of N~ND
qate will qo low (to the 0 sta~e) on the transition of NcLocK
(i.e., the binarY number at the outPut of the master clock) to XXX1111102 where the three most significant digits of NCLoc~/ as indicated by the X's, may be of either binary state.
Gate 236 feeds one of the two inputs of NAND gate 238. The other input of NAND gate 237 are fed by NAND gate 237, and the two inputs of gate 237 are fed by the Q output of flip-flop 234 and the TFAST/2 output of clock 210. The output of ~ -gate 238 is connected to the clock input of flip-flop 234 for triggering the flip-flop, and the flip-flop's JK inputs are connected to a suitable d.c. voltage source representing the 1 state. Flip-flop 234 is wired to respond to the falling edge of a clock pulse as indicated by the bubble at the clock input of the flip-flop. With these circuit connections, flip-flop 234 operates as a counter and will be set to its 1 state, causing its Q output to be high, on the falling or negative going edge of a pulse at its clock input.
As shown in Figure 11, the Q output of flip-flop 234 is connected to one input of gate 241, and the serial out-put of register 208 is connected through an inverter 246 to the other input of gate 241 to undo the inversion of NOR 242. The -Q output of flip flop 234 feeds one input of gate 240. The out-put of register 204 feeds the other input of gate 240. The out- --puts of gates 240 and 241 feed the inputs of NOR gate 242, and the output of NOR gate 242 feeds the serial data input of register 208.
With this logic, data is recirculated around register 208 when gate 241 is enabled. Thestates of gates 240 and 241 will be the complement of each other because one is con-lO~Z34 nected to til~ Q OlJ~ )Ut of flip-flop 2~s4 and thc oth~r is connectcd to the ~ ou-tE)ut Or ~h~ 1ip-I]op.
With thc fc,reguir,g loyic it is ~ppar~nt that up to and including NCIocK=XXXlllO1~ the output of gate 236 will be high. During this time, flip-flop 234 is at its 0 state so that its Q output i~ low as shown in the timing dia-gram of Figure 12. The output of gate 237 wi]l therefore be high, allowing the signal ~rom N~ 236 to propagate through N~ gate 238.
With flip-flop 234 in its 0 state, the low on its Q output inhibits gate 240 to block passage of new data to register 208, and the high on its Q output enables gate 241.
Binary data from the output of register 208 will therefore be recirculated through gates 241 and 242 by pulsing the clock input of the register.
When NCLocK advances one count to XXX1111102, the output of gate 236 goes low. This causes the output of gate 238 to go high as shown in Figure 12. However, flip-flop 234, will remain in its 0 state because the transition at its cloc~
input was positive going rather than negative going.
;20 When NCLocK is advances to XXX1111112, the output of gate 236 again goes high. When this happens, the output of gate 238 goes low, thus setting flip-flop 234 to the 1 state.
The Q and Q outputs of flip-flop 234 therefore change states to 1 and 0 respectively.
Now gates 240 will be enabled to pass new data from register 204 to register 208, and gate 241 will be inhibited to block recirculation of data around register 208. When the first shift pulse arrives at the clock input of register 208 after flip-flop 234 is set to its 1 state, the new data bit from register 204 will be entered in register 208, and the existing data in register 208 will be shifted right, thus causing the oldest data bit to be dropped or destroyed.
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The arrival o~ t~e first 'rl~sT/2 master clock pul~;e after flip-flop 234 is set tv its 1 state CaUL:e5 the output of gate 238 to go high as shown in Fic~ure 12. ~l~he termination of this TF~ST/2 clock pulse causes the output o gate 238 to change from the 1 state to the 0 state to change flip-flop 234 to its 0 state. Flip-flop 234 will remain in its 0 state until the next transition of NCLocK from XXX1111012 to XXX1111102. With flip-flop 234 in its 0 state, gate 241 will be enabled to allow recirculatian of data around register 208, and gate 240 will be inhibited to block application of new data to the input of register 208.
As shown in Figure 11, the jog control circuit 218 includes a JK flip-flop 250, a pair of NAND gates 252 and 253, a pair of AND gates 254 and 255 and a NOR gate 256. Flip-flop 250 is wired to reYerse state on each falling clock pulse at its clock input. The J and K inputs of flip-flop 250 are tied to a suitable source of positive d.c. voltage representing the logic 1 state. The Q and Q outputs of flip-flop 250 will --therefore complement on the falling or negative going edge of each incoming clock pulse at the flip-flop's clock input.
The inputs of gate 252 are connected to the TFAST
output of master clock 210 and the Q output of flip-flop 250.
The inputs of gate 253 are connected to the output of gate 252 and to the output of gate 236. The inputs of gate 254 are connected to the Q output of flip-flop 250 and the TFAST/2 output of master clock 210. The inputs of gate 255 are con-nected to the Q output of flip-flop 250 and the TFAST output of master clock 210.
When flip-flop 250 is set to its 1 state, making its Q output high and its Q output low, gate 254 will be enabled D ~s~ -.

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and gate 255 will he disabled. Whcn flip-flop 250 is cleared to its 0 state, making its Q output low an~ its Q output high, gate 255 will bc enabled and gate 254 ~Jill be disabled.
When gate 255 i5 enabled, master clock pulses having a period of TFAST ~re gated to the clock or shift input of register 208 to shift the register contents. When gate 254 is enabled master clock pulses having a period of TFAST/2 are gated to the clock input of register 208 to shift the register contents.
Flip-flop 250 will be in its 0 state up to the transition of NcLocK from XXX1111102 to XXX1111112. As a result, gate 255 will be enabled and gate 254 will be dis-abled as NcLocK is advanced from XXX0000002 to XXX1111102.
During this time, the TFAST clock pulses will be gated to the clock input of register 208 to shift the register contents.
Throughout this interval it will be recalled that gate 241 is enabled and gate 240 is disabled. Thus, throughout this interval, data will be circulated around register 208 at the rate of l/TFAsT, and supply of fresh data to register 208 will be blocked.
Because of the previously described circuit connec-tions to the inputs of gates 252 and 253, the clock input of flip-flop 250 (i.e., the output of gate 253) will remain low as NCLocK is advanced from XXX0000002 up to the transition of NCLocK XXX1111102 as shown in Figure 12. At this transi-tion the clock input of flip-flop 250 goes high to its 1 state ` and remains high until the transition of NCLocK from XXX1111102 to XXX1111112. Then, the clock input of flip-flop 250 goes low, setting flip-flop 250 to its 1 state. When the TF~ST
clock output rises to its 1 state at NCLocK = XXX1111112, the clock input of flip-flop 250 again goes hlgh, but this action will not clear flip-flop 250 to its 0 state because the 2Z;~4 flip-flop w;ll triyger orlly on thc f~lllin(~ e a~e of a clock input pulse.
Flip-flop 250 therefore reJnains in its 1 state until the transition of NcLocK from XXX1111112 to XXXG000002.
At this time the clock input of flip-flop 250 goes low to rever~e flip-flop 250 to its 0 state. Flip-flop 250 will now remain in its 0 state unti] the next transition of NcLocK from XXX1111102 to XXX1111112.
For the interval in which flip-flop 250 is in its 1 state, gate 254 will be enabled and gate 255 will be disabled.
During this interval two clock pulses having a period of TFAST/2 will therefore be fed to the clock input of register 208 in place of tne single TFAST clock pulse. Thus, for the interval in which flip-flop 250 is in its 1 state, the pulse frequency at the clock input of register 208 becomes twice the normal rate.
Since flip-flop 250 is put in its 1 state only for one period of TFAST~ only two clock pulses at the doubled fre-quency of 2/TFAST will be gated to the clock input of register 208 to shift the register contents. These two TFAST/2 clock pulses are indicated at 260 and 261 in Figure 12.
From the foregoing description it is clear that the transition of NCLocK from XXX1111102 to XXX1111112 causes both of the flip-flops 234 and 250 to concomitantly ke set to their 1 states. At the time the first TFAsT/2 clock pulse 260 arrives at the clock input of register 208, therefore, -gates 240 and 241 will respectively be enabled and disabled.
j Thus, at NCLocK = XXX111111.02 clock pulse 260 will shift the ` contents of register without recirculation to enter a fresh I data bit into register 208 and to drop the oldest data bit which formally occupied the last stage in the register.

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lO!~Z~4 I~eforc tllc occ~rrcn(f,~ o~ thc second ~l~r"~ ,/2 clock pulse 261, flip-f~op 2~4 i5 ~eveSrsed ~0 its 0 s1,~ e, th~re~,y enabling th~ recirculating loop through gate 241 and blocking passage of new data from registcr 204 to register 208. Thus~ , -when clock pulse 261 arrives at the clock input of registcr 208, the contents of the register 208 will shift right, re-circulating one binary bit.
From the foregoing description it will be appreciated that each time the partial word represented by the six least significant digits of NCLocK becomes equal to 2 (where i=6 in the previous numerical example), a new data bit is injected into register 208 followed by the insertion of the extra regis-ter-shifting clock pulse 261.
The youngest data bit entered into register 208 by clock pulse 260 will therefore be shifted one stage to the right by clock pulse 261 so that at NcLocK=XXXO000002, it will occupy the second register stage which is indicated at bin #1 in Figure 14. The relative age of the youngest data in bin #l will be 2n-1 (511 for n=9).
In Figure 14, the numerical values assigned to the bits in register 204, 208, 220 and 222 are indicative of the relative ages of the bits at NCLocK=ooooooooo2~ with the largest numerical value, 2n+2n 1_l representing the youngest bit, and the smallest numerical value, 0, (not shown), repre-senting the oldestbit. In other words, the numercial values assigned to the bits in the registers in Figure 14 are in in-'' verse order of the relative ages of the bits. The formula that represents shift register 208 bin location according to < data bit k', where O~k'~2 -1 at NCLocK=o is ~1+(2n-1-k')(2i+1)]
mod 2n.
` . S~7 _~ , ~' ' 10~ 4 Tlle sccor)d youn-~<t bit ;n ~egister 208 has a rc-lative a~Je of 2 -2 ~5]-J for n--9) and occupies the register stage ~hich is designate(l at bin #~lJ(2 +1)]. For i--6, this will be bin #66. Irhe thild youngest bit in register 208 is 2n-3 (or 509 for n=~) and occupies the register stage indicated at bin ~[1+2(2i+1)] at NcLocK=000000000 . For i=5, this will be bin ~131.
As shown in Figure 10, flip-flop 206 is clocked by the TFAST master cloc~ pulses to delay the supply of data to gate 66 by one TFAsT bit time. This operation prevents the oldest data bit which is dropped from register 208 at the occurrence of pulse 260 from being fed to gate 66. The data bit dropped from register 208 by the application of pulse 260 to the register's clock input will therefore not be presented to correlator 44.
From the relative age designations sho~ in Figure 14, the youngest data bit in register 208 (namely, 2n-1) is spaced 2i+1 bins from the second youngest data bit 2n-2 in the register because of the insertion of the extra clock pulse 261 Since 2n has no common factor with 2i+1 and since the value of i was selected to be greater than zero, but less than n, register 208 will eventually become completely loaded with data bits whose relative ages are not in serial order. Instead, the relative ages of data bits in register 208 will be in a scrambled, pre-determined order. -In comparison~ the relative ages of data bits in register 222 are in serial order. Accordingly, the difference between ages of the bits in the pairs successively fed to gate 66 will not vary progressively as in the preceding embodiment, but instead will be related to the scrambled order of bits in register 208. -'', ,~'; ' ~~ j .

22~4 The a~c difer.~nce o channcl ~ arld 1~ bit~ ~rc~s~nt~
to yate 66 is .illdicativc of the v.lria~lc t~ C del~y ~ the chanJlel ~ data relative to the channel B at the input of gatc 66. In other words, the aye difference is indicative of the net variable delay produced by registers 208 and 222. The age difference between channel A and channel B bits at the input of gate 66 is therefore indicative of the location of pipe 26 being scanned. For example, when the age difference is zero the location of pipe 26 being scanned will be midway between geo-phones 22 and 24 and when the age difference is a maximum, the pipe location being scanTIed will be the farthest away from the midway location.
Although the age differences of channel A and.channel B bits presented to gate 66 are in scrambled order, they bear a ` ~ predetermined relationship to the values of NCLocK~ This factor,: .' . as will be explained in detail later, enables the ordered read-out of data to establish the location of the leak.
For the scrambled order of bit ages in register 208, the relative ages of data bits fed to gate 66 will recurrently :`
repeat a pattern every 2 counts of TFAST clock pulses if tne : . data channel B is not recirculated but instead is advanced once every 2i counts of TFAST~ that is, TSLow. However, by employing the recirculating register 222 in channel B and by making register 222 2 i bits lon~, the pattern is advantageously repeated every -2 counts of the TFAST clock pulses where 2 is much greater than 2i. In this way data bits of 2n relative ages will be compared at corxelator 44 in time 2nTFAST~
The parallel load circuit 224 a synchronously parallel ~ loads register 222 with the contents of register section 230 : 30 between the transition of NCLocK from 1111111112 to 2 and the transition of NcLocK from 2 to 0000000012.
. Circuit 224 may be of any suitable design for accomplishing the parallel loading function without interrupting circulation of .~
f 10~2~4 data around register 222. One eY~ample of a suitable circui~
~esi~n is shown in I;i~ure 11 ,lhere circuit 224 coinprises a ~K
~lip-flop 270, a pair of N~ND gates 272 and 273 and an invcrter 274.
Flip-flop 270 has its J and K inputs connected to a suitable course of d.c. voltage representing the 1 state. The Q and Q complement in response to the application of clock pulses at its clock input. Flip-flop 270 is wired to respond to the negative going or falling edge of the clock input as indica-ted by the bubble at the flip-flop's clock input.
As shown, the inputs of gate 272 are fed by the TFAST/2 output of the master clock 210 and by the Q output of flip-flop 270. The output of gate 272 feeds one input of gate 273. The 512TFAST output clock 210 is connected by way of inver-ter 274 to the other input of gate 273. This clock output, it will be recalled, represents the most significant digit in N
The output of gate 273 is connected to the clock input of flip-flop 270 for triggering the flip-flop, and the ` Q output of flip-flop 270 feeds the parallel load control pin of register 222.
With the foregoing logic it will be appreciated that the output of inverter 274 changes from a logic 0 to a logic 1 only on the transition of NcLocK from 1111111112 to 2 ` Up to this transition flip-flop 270 will be set to its 0 state so that its Q output will be low. The output of gate 272 will `~ therefore be in the 1 state which allows the 512 TFAST signal to propagate through the NAND 273 as shown in Figure 13. -When this -~
happens flip-flop 270 will be set to its 1 state, making Q low and its Q output high.

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Z2~4 T~le 0 st~tc on the Q ou~pu~ o ~:lip-flop 2/r) causcs the contents of register section 2~0 to hc parall~l lo~dcd into register 222, thus repl~cin~ the contcnts tha~ wer~ prc-viously in register 222. The first TF~ST/2 clock pulse (indica-ted at 278 in Figure 13) occurring after ~lip-flop 270 is set to its 1 state is gated through gates 272 and 273 to the clock input of flip-flop 270. At the falling edge of this clock pulse, flip-flop 270 will be switched to its 0 state. This occurs at the transition of NCLocK from 2 to -12 as shown in Figure 13.
Changing flip-flop 270 causes its Q output to once again go high, thus permitting data to be circulated around register 222 without interruption. Flip-flop 270 will remain -` in its 0 state until the next transition of NCLocK from ; 1111111112 to 2 Since registers 208 and 222 and flip-flop 206 are all clocked at the same rate from the same output (namely TFAST) of clock 210, the flow of data in channels A and B will be syn-chronized so that each pair of data bits to be compared at cor- --relator 44 will arrive at the two inputs of gate 66 at the same time. As previously described the output of gate 66 will be high (a logic 1) if the channel A and channel B bits at the gatels inputs are either both high or both low. Conversely, the output of gate 66 will be low (a logic 0) when there is inequality between the two incoming data bits. That is, the out-put of gate 66 will be low if one of the incoming data bits of a given pair is high and the other data bit of the pair is low.
The output of gate 66 is employed to control the out-put of a write signal circuit 280 (see Figure 15) in memory section 228 in a manner to be described in detail later on.
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In addition to the wxite cont~ol signal circuit ~Y,0, mem~ry section 22~ is shown in FicJure lS ~o inclu~ ~ random, access memory module 282, a multiplexer 28~ for addressing the memory array in module 282 either with ordered memory addres.ses, or encoded memory addresses, a latch 28~ connected to the memory output pins of module 282, and a binary adder 286 connected to the output of latch 284 and feeding the memory input pins of module 282.
Memory module 282 may be any suitable type having a non -destructive read that enables a stored binary word to be read out of memory without being destroyed and, consequently, without requiring the read-out word to be written back into the memory. A RAM (random access memory) semiconductor memory with ` non-destructive read is suitable for accomplishing the objec-tives of this in~ention. It will be understood that, in addi-tion to the memory array (i.e., the memory storage devicesl, module 282 includes decoders, buffers and drivers that are customarily incorporated into the memory package.
The memory array in module 282 is selected to be ~` 20 large enough to store 2 words or 512 words where 9 is selected as the value of n in accordance with the previous nu-merical example. The memory word length (i.e., the number of bits in each word) is preferably selected to be large enough -` to insure accurate location of the leak. For example, a memory ` module having a word length of 16 bits is satisfactory.
As will be explained in detail shortly, a different pre-selected location is addressed in memory 282 for each of the 512 different bit time delays produced by register 20~ as NCLoCK is advanced through one cycle. 512TFAST bit time per-iods constitute one cycle of NCLocK~ starting with NcLOcK=
2 an~ ending with NCLocK=1111111112.
r ,~ ,A S ~

10.~ 22~4 Z~s previc~ sly e~plairled, a (~ ferent p~e(letermined location on th~ pipe(indicatcd at 26 in F.igure .l) is s,c~nr~ed for each o~ t~le 512 different bit time del~ys prGduced by register 208 in channel A. Accordingly, the different pre-selected address locations in memory 282 in one cycle of NClocK correspond to different predetermined locations on pipe 26 or, in other words, different pre-selected distances from one or the other of geophones 22 and 24, such as geophone 24.
The output of correlator 44 is determined for each of the 512 bit time delays, and if it is high, 12 is added by adder 286 to the word at the address corresponding to the bit time delay that produced the correlator output. If the output of correlator 44 is low, there will be no addition to the word at the address corresponding to the bit time delay that produced the low.
After all 512 locations in memory 282 are addressed, the scanning or de].ay operation is repeated, using the same addresses for the 512 different bit time delays produced by register 208. In this second scanning or delay line operation, the output of correlator 44 is once again determined for each of the 512 different bit time delays, adding a binary 1 at the appropriate addresses only when the correlator output is high.
The foregoing scanning or delay line operation is preferably repeated a large number of times not exceeding the memory's word length. In this embodiment, the number of the repetitive scanning operations is selected to be equal to the memory's word length to utilize the full capacity of memory 282.
~ fter the repetitive scanning operations are comple-ted the binary words stored in memory 282 are read out in such an order that, upon display in analog form, they indicate the location of the leak.

s~
--56-- ' ' ' ' . ' .' ' . . . .

Z~

T/`.T',l,}i' T

P~l.AGE(~T~OE ~l.AOE~
Cloc]cOF DA~rA ) OF D~r~ Gæ- B~G~ ~Ncor~Er> ~c~r-~r AT F/F 206 ~ O~VT A~r~ss ADDI~SS
_ OF SR 222___ (D~CIM~L) ~B~`J~;~Y) 000000000 448 256 192 4~8 111000000 000000001 385 257 128 384 11000n00() 322 258 6~ 320 101000000 11 259 259 0 256 100000~00 100 196 260 -64 192 0~1000003 1010 330 258 72 328 lolooloon ` 1011 267 259 8 264 100001U00 : .1100 204 260 -56 200 011001000 : 1101 141 261 -120 136 010001000 1110 78 262 -184 72 001001~J00 1111 15 263 -248 8 00~001000 ~ .10001 401 257 144 400 110010000 ,;10010 338 25g 80 336 lololooon ~:10011 275 259 16 272 100010000 10101 149 261 ~112 1~4 010010000 ` `10110 86 262 -176 80 001010000 , '11000 472 256 216 472 111~11000 . ~11001 409 257 152 408 110011000 ~.,11010 346 258 88 344 101011000 ,` `11011 283 259 24 280 100011000 :11100 220 260 -40 216 011011000 ' 11101 157 261 -104 152 010011000 `11110 94 262 -168 88 001011000 ~11111 31 263 -232 24 000011000 i ~100000 480 256 224 .480 111100000 '100001 417 257 160 416 110100000 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 111101 189 261 -72 lg4 010111000 ~ ~ 111110 126 262 -136 120 001111000 ': 111111 63 263 -200 ` 56 000111000 ` 1000000 449 256 193 449 111000001 ` 1000010 323 258 65 321 101000001 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~

~ 1111101 190 261 -71 185 010111001 `. `~ 1111110 127 262 -135 121 001111001 : 1111111 64 263 -19 57 000111001 ` 10000000 450 256 194 450 111000010 ------------_ _ _ _ _ ~.
,, 5-~ .

,. , ,, ,, ., ' .:

T~ULI_I k~Jntirlu~cl) 1(3~Z~34 Clock or~ D,~Jl~ ~ OI lAr~r~ ~' ~ , J3~0~D ~K~ ~T F/F 206 ~T ~n~ur ' ~DDI~SS ~r~
_ _ OF SR 222 _ _ (D~c~l) ~in.~ri~

~ 100 255 260 -5 ~1 01111~0l]
11111101 192 261 -69 1~7 010111nll 11111110 129 2~2 -133 123 0011110]1 11111111 66 253 -197 59 000~1011 100000n00 452 256 196 452 1110001()0 __________________________________ ________________________________________ 100000011 263 259 4 260 10000~010 ___________________________________________________________________________ 111111~01 196 261 -65 191 0101111~1 1~.1111110 133 262 -129 127 001111111 Before explaining operation of memory section 228 ` in greater detail, the memory addresses and the manner in which they are obtained will first be considered. In this regard, it will be recalled that there is a different, unique, predeter-mined value of NCLocK for each of the 512 different bit time ~- delays produced by register 208. This factor enables NcLocKto be used as the memory address register by encoding NcLocK~ The manner in which NCLocK is encoded is shown in Table I above.
In the first column of Table I consecutive, binary - values of NCLocK are listed in order of their occurrence. Some of the NcLocK values have been omitted to shorten the length of the table.
The relative ages of channel A data bits appearing at the output of flip-flop 206 (and hence one input of gate 66) at the values of NCLocK set forth in the first column of Table I are listed in the second column of the Table. The numbers 0 through 2n-1 (i.e., 511 where n=9) are used in numerical order to represent the 512 different bit ages, with 0 being assigned ` the designate the oldest data bit and 511 being assigned to de-signate the youngest data bit similar to the relative age de-signations used in Figure 14. Thus~ the relative age ~: ' ~ . .. .

r r . . , ~ .

10!~234 o~ ~hc ~ rlr~ bit ~-~ N~lo(1K-()()()Ot)OO~z i.~ , t~
relativc a~e o tl-lc ch~nncl A data },:it at NcL~cK-OOOOGO~012 is 385 and so on.
In a sirnilar fashion the relative ages of channel B
data bits appearing at the output of reyister 222 (and hcnce at the second input of gate 66) for the listed values of NCLocK~
are set forth in the third column of Table I. For this purpose, the numbers 2n 1 (i.e., 256 for n=9~ through 2n 1~2n i_l (i.e., 263 for n=9 and i=h) are used in numerical order to represent the different relative ages of the channel B data bits that are fed to gate 66 in each cycle of NcLocK~ Reading this part of the Table it is apparent that the relative age of the channel B
data bit at NCLocK=ooooooooo2 is 256, the relative age of the ;channel B data bit at NCLocK=0000000012 is 257 and so on.
From the contents of the Table thus far described it will be appreciated that the relative ages of the channel A
and channel B data bits which are applied at the same time to the inputs of ~ate 66 at NCLocK-ooooooooo2 will be 448 and 256, respectively. Likewise, the relative ages of the channel A
and channel B data bits simultaneously at the inputs of gate 66 at NcLocK=OOOOOOOOl will be 385 and 257 respectively.
Furthermore, it will be observed that at the begin-ning of an NcLOcK cycle where NCLocK=ooooooooo2~ the relative age of the channel A data bit will be (2i)(2n i-l) or 2n-2i, while the relative age of the channel B data bit will be 2n 1.
Listed in the fourth column of Table I is the differ-ence between the channel A and channel B data bit ages (namely, the relative age of the channel B data bit subtracted from the channel A data bit) for each value of NCLocK. This difference, as previously mentioned, is a mathematical function of the net variable time delay that is imparted to the data in channel A, ; ~
r _~_ i~223~
wh~r~ the n~t vari.~le 'iim~ dela~ is the time ~3cl.ly ir~parte-3 to cli~nn~ ta by reyi!;~er 2~1~ ]ess t~le time delay impar~cd to channel B data by r~gist~r 2~.
Thc encoded melnory addr~ss for each value of NCL~cK
is obtained by suhtractillg the given relative age of the channel B data bit from thc relative age of the coexisting channel A
data bit and by adding 2n 1 in order to obtain only positive numbers from 0 to 2n-1 for convenience in decoding the scrambled relative age, Hence the encoded memory address is a mathematical function of the time delay of channel A data relative to the delay of channel B data and is equal to Aage~Bage~256. The encoded address for each value of NcLocK is listed in decimal form in the fifth column of Table I and in binary form in the sixth ; column of Table I.
` At NCLocK=1111111112, for example, the encoded ad- -dress is equal to 70-263~256 which gives 631o or 0001111112.
Taking a second example at MCLocK=ooooooooo2~ the encoded address will be 448-256+256 which gives 4481o or 1110000002.
The encoded addresses for the remaining values of NCLocK are determined in the same way.
Examination of the first and last columns of Table I
reveals a predetermined relationship between the values of NCLocK and the encoded addresses. This relationship is demon- ;
strated by using positional notations to represent the digit ~-positions in NcLocK and the encoded binary address number as shown in Figure 15. In the binary system~ it is understood that the least significant digit of a binary number has a positional notation of 2 or 1, the second least significant digit of the binary number has a positional notation of 21 or 2, the third least significant digit of the binary number has a positional notation of 22 or 4, and so on, ' . ~ s7 .

~zz~4 From Ir~ble I it wi~l bc obscrve~ that inversions of binary valucs at the positional nota'cions of 1, 2 ~nd 4 in NcLocK are respectively iderltical to ~he binary values at the positional notations 64, 128 and 25~ in the encoded binary address number. Additionally it wlll be observed that the binary values at the positional notations 64, 128, 256, 8 16 and 32 in NCLocK are respectively the same as the binary values at the positional notations 1, 2, 4, 8, 16 and 32 in the encoded binary address number.
Based upon the foregoing relationship between NcLocK

and the encoded binary address number, NcLocK may be encoded into the encoded binary address by employing three inverters 294, 295, and 296 and by making appropriate connections between the master clock's NcLocK outputs and one set of input pins of multiplexer 284 in the manner shown in Figure 15.
Refer~ing to Figure 15, multiplexer 284 has two sets of input pins, one for receiving the encoded binary address as mentioned above and the other for receiving an ordered binary address which is represented by NcLocK~ Multiplexer 284 may be of any suitable type for connecting only one of its two sets of inputs to its output pins when the state of the signal at its control input is one binary value and for connecting only the other set of inputs to its output when the control input is in the other binary state.
; In Figure 15, the input pins making up one of the two ~ -sets of the multiplexer's inputs are represented by the positional notations of NcLocK~ The inputs making up the other of the two ~-input sets are represented by the positional notations of the encoded binary address.
The nine outputs of NcLocK are fed in parallel and without change to the nine inputs of one input set of multiplexer ~8 284 to furr)ic;~l t]lC or~ercd a~dre~s ~or melrlory 282.
To ~llrnish thc ~ncoded acldress, t~l( follo~JincJ
connections are made betwcen NcLocK and the sccond set o~ inputs of multiplexer 284; the NCLocK outputs having the nota~ional positions 1, 2 and 4 are respectively connected by way of in-verters 294, 295 and 296 to the multiplexer inputs of represen~-ing the 64, 128 and 265 positional notations in the encoded bina^y address; and the NCLocK outputs having the positional notations 64, 128, 256,8, 16 and 32 are respectively connected directly to the multiplexer inputs representing the 1, 2, 4, 8, 16 and 32 positional notations in the encoded binary address.
When the signal state at the control input of multi-plexer 284 is high, the encoded address, and not the ordered address (i-e-, NcLOcK), is fed to the multiplexer's output for addressing memory 282. When the signal state at the control input of multiplexer 284 is low, the ordered address (i.e., NcLocK)I and not the encoded address, is fed to the multiplexer's output to address memory 282.
The encoded address is used during the scannin g or time delay operation to store the digital information at the proper locations in memory 282. The ordered address is used -in the ensuing read-out operation for reading the information out -- in the order needed to determine the location of the leak in pipe 26.
As shown in Figure 15, the control input signal for multiplexer 284 is supplied by the Q output of a JK flip-flop 298. The J and K inputs of flip-flop 298 are connected to a positive d.c. voltage source representing the logic 1 state; - ~
thusthe flip-flop is wired to complement itself on each falling -~ -pulse edge arriving at its clock input.
The clock input of flip-flop 298 is fed by a NAND

'' ' Z~4 gate 300. One input oI yatc 300 is cd by the outpu~ o~ a start circuit 302. The other input of c3ate 30() i s fed by another ~ND
gate 30~. The inputs o~ gate 30~ are respectively cor~necte~ to the Q output of flip-flop 298 and to an output of a counter 30~.
Start circuit 302 may be of any suitable construction which is manually energized by closure of a switch 308 to start operation of the leak detector system. Circuit 302 responds to the closure of switch 308 by supplying a negative going pulse at an appropriate time that automatically puts all of the control or operating signals in synchronism to ensure fault-free operation of the system.
As soon as start circuit 302 is energized its output goes high to the logic 1 state as shown in the timing diagram of Figure 17. Master clock 210 may be turned on concomitantly with or before start circuit 302 is energized. At the appropriate time after circuit 302 is energized, its output changes from the logic 1 state to a logic 0 and then returns to the logic 1 ~ -state to develop a negative going pulse (indicated at 310 in Figure 17) which clears all counters, including clock 210, in -the system.
The rising edge of pulse 310 causes the output of gate 300 to go from a logic 1 state to a logic 0 state, thus setting flip-flop 298 to its 1 state. As a result, the Q output of flip-fl~p 298 goes high to cause multiplexer 284 to connect the multi- -plexer's upper set of inputs to the multiplexer's output for ~ -feeding the enco~ed binary addresses to the memory input of memory 282. Thus, as long as flip-flop 298 remains in its 1 state, multi- ~
plexer 284 will be conditioned to feed the encoded binary address ~, numbers to memory 282, and not the ordered addresses.
Flip-flop 298 will remain in its 1 state until NCLocK
has made 2j cycles where j is the number of bits in each memory word, here j=16. For the previously ~ c~

, 10~2~4 given numerical example, flip-flop Z98 will remain in its 1 state for 216 complete cycles of NCLocK~ The first cycle is used to clear the memory contents. The 216-1 remaining cycles of NCLocK
make up the scanning operation in which new data is stored in memory. At the completion of the 216th cycle of NCLocK~ flip-flop 298 will be triggered to its 0 state by operation of counter 206 and NAND gate 304.
For accomplishing the foregoing operation, counter 306 may be a binary counter which is fed from 512TFAST of clock to count the 2j number of NCLocK cycles-With the foregoing logic it will be appreciated that as soon as flip-flop 298 is set to its 1 state, the output of gate 300 goes from low to high to condition the flip-flop's clock input for triggering at the completion of the 216 cycle of NCLocK. Thus, when the output of counter 306 goes low at the completion of the 2 th cycle of NcLOcK, the output of gate 304 will go high. When this happens the output of gate 300 changes from high to low (a - logic 1 to a logic 0) to set flip-flop 298 to its 0 state. This marks the end of the scanning operation and, as will be explained in detail presently, automatically initiates the read-out operation in which the data stored in memory 282 is read out to establish the location of leak in pipe 26.
For each cycle of NcLOcK in the scanning operation the encoded addresses will successively be applied to the memory input of memory 282 in the order in which they are listed in the last column of Table I.
In the embodiment shown in Figure 15, the control circuit 280 for writing information into memory 282 comprises a NAND gate 320, and OR gate 322~ an inverter 324, and an erase flip-flop 326 of the JK type. The J and K inputs of flip-flop ~ !
, , .
.: ' ' ' ' ': , , ', l~ZZ3~

326 are connecled to a po~:itive d.c. ~oltayc ~ource represc~ting the logic 1 state; thus t~ flip-f]o~ i5 wired to complement itself on each falling pu]se edye arriviny at its c]ock input.
The clock input of flip-flop 326 is fed by a NAND
gate 328. The two inputs of NAND gate 328 are, in turn, fed by the start circuit 302 and by the output of a further NAND gate 330. The inputs of gate 330 are fed by the Q output of flip-flop 326 and by the 512TFAST output of master clock 210. As shown, the inputs of OR gate 322 are fed by the Q output of flip-` 10 flop 326 and by the output of gate 66.
NAND gate 320 has four inputs. Three of the gate'sinputs are respectiYely fed by the output of OR gate 322, the Q
output of the scan flip-flop 298, and by the TFAST output of master clock 210. The TFAST/2 output of clock 210 feeds the ~ ~ fourth input of gate 320 by way of inverter 324. ~ -E ~ The OUtpllt of gate 320 feeds the write input of memory 282. Gate 320 therefore furnishes the write signal to ` memory 282.
If the output of gate 320 goes low (i.e., a logic 0) ~ 20 the data pxesented to the input pins of memory 282 will be written the memory at the addressed location in place of the original word -~stored at that location. On the other hand, if the output of gate 320 remains high, the binary word presented to the input pins ` of memory 282 will not be written into the memory, and the original word will remain stored in the memory, In order for the output of gate 320 to go low to write data into the memory, either the output of gate 66 or the Q
, output of flip-flop 326 must be hi~h (i.e., a logic 1~. The output of gate 66 will be high on]y when the pair of data ., ,9 6~

r. :

r . . .

5' h,Z~

bits concorllitancly presented to the inputs o~ yate 66 are both hiyh or both low, establishing parity. The er~se operation for ~r~sinc3 thc contents in memory 282 now will be explaincd followed by an explanation of the write operation.
Fo~ each cycle of NCLocK in the combined erase and scanning operations the encoded address in the last column of Table I will successively be applied to the address input of memory 282 in the order in which they are listed in Table I.
The binary words at these addresses will therefore be non-des-10 tructively and successively read out and placed in latch 284 in the order in which they are addressed by the encoded addresses.
Latch 284 is conveniently of the type that allows data to pass right through when unlatched, but latches onto, and thus saves, the last data upon latching. In this embodiment, the latch signal is supplied by the TFAST output of master clock 210. In absense of a clear signal to the latch's clear pin latch 284 will latch onto and retain the binary data presented to its input on the rising edge of each TFAST pulse. Latch 284 will be cleared when the Q output of flip-flop 326 is high.
Adder 286 may be any suitable binary adder capable of -adding whatever binary state exists at the Q output of the erase flip-flop 326 to the word that is presented from latch 284. If latch 284 is cleared, it presents 2 or zero to adder 286. Thus, when flip-flop 326 is in its 1 state, making its Q output a binary 0, and when latch 284 is cleared, 2 will be added to 2 so that the binary value of the word fed back to the input pins of memory 282 will be zero.
` Before the start circuit output pulse 310 occurs, flip-flop 326 will be in its 0 state. Then on the rising edge 30 of the start circuit output pulse 310, the output of NAND gate 328 goes from high to low setting flip-flop 326 to its 1 state.

.
t G~ ~

, .
:
- ' '' ~ ~
. . .

l~Z~;~4 ~5 a resu],t, the Q ou~put of flip-flop ~Z6 ~oes low to a lo~ic 0, conditionin~ the ci,rcuitry for the erase operation.
Witll flip-~lop 326 in its 1 state, its Q output will be high, thus setting the outpu-t of OR 322 to a logic 1.
Additionally, the rising edge of the start circuit output pulse ~, causes the scan flip-flop 298 to be set to its 1 sta'e at the same time that flip-flop 326 is set to its 1 state. The Q
output of flip-flop 298 will therefore be high or a logic 1.
Under these conditions the output of NAND gate 320 will change from high to low each time the TFAST/2 output goes low and the TFAST output goes high. This occurs on the rising edge of the TFAST output pulse and the simultaneously occurring falling edge of the TFAST/2 output pulse. The output of NAND gate 320 then remains in its 0 state for the duration of the time that TFAST/2 is low and then goes high to the 1 state on the rising edge of the next TFAST/2 output pulse to produce the write signal which, ~-as shown in Figures 15 and 16, is in the form of a negative going pulse. It therefore is apparent that one write signal occurs for each state or value of NCLocK if flip-flop 326 is in r 20 its 1 state or if the output of correlator 44 is high.
In addition to setting flip-flops 298 and 326 to their 1 states, the start circuit output pulse also clears the master clock counter stage so that the state of NCLocK goes to 2 '~
to initiate a complete cycle of NCLocK for the erase operation.
AS NCLocK is advanced from 2 to and including 1111111112, the 512 stored data words in memory 282 will successively be read out in the order of the addresses listed in the last column of Table I.

Thus, at NCLocK=ooooooooo2r the word at address 1110000002 will be read out of memory 282 and fed to latch 284.
Latch 284, however, will be cleared by the 1 state on the Q

1~3'32Z34 . . .

- OUtptlt of f~ f lop 3'~ SO that ~ will hc prescnted to add-r 286 re(Ja~dle~:-; of the hillary valuc of thc word read O1~t of memory.
Since flip-flop 326 is set to its 1 state, the ou~put of adder 286 will also be zero. Tllus, when the write signal is produced in the period of NcLOcK=0000000002, a binary zero will be written back into memory 282 at address 1110000002 in place of the original word at that location.
en NcLocK advances to its next state, 0000000012, the word at address 1100000002 will be read out of memory 282 and fed to latch 284. Flip-flop 326, however, is still in its 1 state so that binary zeros wili be applied to the inputs of adder 286. The binary word fed back to the memory inpu~ pins of memory 282 is therefore zero. Thus at the occurrence of the write signal during the period in which NCLocK=0000000012, the value of the word written into memory at address 1100000002 in place of the original word will be zero.
The remaining words will successively be read out of memo-y 282 in the order of the addresses in the last column of Table I, and on each occasion a binary zero will be written into the memory in the same manner as described above. Thus, when . NcLocx reaches the end of its cycle at 1111111112, the entire contents of memory 282 will be erased or dumped in preparation for the scanning operation in which new data is written into memory.
When the state of NCLocK advances to 12 during the erase cycle of NCLocK~ the output of gate 330 goes low. As a result, the clock input of flip-flop 326 goes from the 0 ~ -state to the 1 state. Now, upon the transition of NCLocK from 1111111112 to 2' at the end of the erase operation, the output of gate 330 goes high again. This causes the output of gate 328 to go from high to low, and the falling pulse edge ~ 65~
~.

. . ' .
. . ' ' , :

lO.~Z2~
clears ~]ip-f~o,f) 32Ç to ;ts 0 stal~.
~ hus, ur~n ~hc comL~le~ion ot the sirlgl~ erase cycle f NCLOCK~ the ~ output of flip-flop 326 will ~Jo low to the logic 0 state, and the Q ~utput o flip-flop 326 will C3O high to the logic 1 state. The state of the signal at the clear input of latcll 2~4 thus goes low to permit latch 284 to la~ch in a data word on the rising edge of the next occurring ~FAST pulse.
Additionally, a binary 1 will be presented to adder 286 for summing with whatever word is latched in latch 284. The circuit is now conditioned for writing new data into memory in a scanning operation which, as is apparent from the foregoing explanation, is automatically initiated upon the completion of the single erase cycle of NCLocx.
During the scanning operation adder 286 will add 12 to each binary word non-destructively read out of memory, but the sum of these binary values will now be written into memory 282 only if the output of the correlator gate 66 is high.
When the output of gate 66 is a logic 1 during any of the NCLocK states, the output of gate 320 will go low on the rising edge of the TFAST pulse and the coinciding falling edge of the TFAST/2 pulse. The output of gate 320 then goes high again on the next occurring positive going TFAST/2 pulse edge to produce the write signal for writing into memory 282 whatever binary word adder 286 presents to the memory input. ~`
The state of NCLocK starts with 2 at the beginning of the scanning operation, will advance to 1111111112, and then will recycle as long as the scan flip-flop 298 remains in its 1 state. With NCLocK=ooooooooo2 at the start of each - cycle, the binary word stored in memory 282 at address 1110000002 will non-destructively be read out and latched in latch 284. As ; an example, assume that the value of the word read out of , ~, ..
~6 ~a~234 memory at this add~css is 1n ~dde~ 2~6 ad(ls 12 to tl-.is ~inary word, makincf the va1ue of th~ binary word fed ~,ack to t~ie mernory input of memory 282 llo. If t:he output of the correlato-r: gate 66 is high at NcLOcK=0000000002, the write signal occurs, causin~ llo to be written into memory 282 at address 1110000002 in place o the original word.
If instead of being high at NCLocK-ooooooooo2t the output of the correlator gate 66 is low, adder 286 will still add 12 to the binary word read out of memory at address 1110000002.
Now, however, a write signal will not be produced at NcLocR=
2 with the result that the original word will remain in memory at address 1110000002.
When NcLocK is advanced to its next state, 0000000012, the data word at address 1100000002 will be read out and latched in latch 284 in place of the preceding word. Assume, as an example, that t~e value of the word read out from this location of memory is 310. Adder 286 adds the count f 12 to this read-out number so that the value of the word presented to the memory input pins will be 410 If during NCLocK=ooooooool2l the output of correlator 44 is high, the write control signal will cause 410 to be written --into memory 282 at address 1100000002 in place of the original --word. If, on the other hand, the correlator output is low, the original word, namely 310 will remain at address 1100000002.
This process is repeated for each state of NCLocK.
Adder 286 will add a 12 to each word read out of memory, but the ` resulting sum is written back into the memory only if the output of correlator 44 is high at the particular time in question.
; When NCLocK reaches the end of its first cycle, it ; 30 will repeat, starting again with the state 2 because at this time flip-flop 298 is still in its 1 state. When NcLocK

- ~7 7~-~"
' ", ' ' ". '~ ' ' ' ' ' ~, ZZ3~

completes its 21Gtl~ ~ycle in the scanning operatioll, flip--fl~
298 will bc cleared to its 0 state, thus terminatin-j the scarning operation and initiating the read-out operation. The mann~r in wich this is accomplished is as follows.
At the middle of the 2 cycl~ of NCLocK in the scanning operation, the output of counter 306 goes high, causiny the output of gate 304 to go low. The output of gate 300 therefore goes high in preparation for clearing flip-flop 298. At the end of the 216th cycle, signalling the end of the cycle, the output of counter 306 goes low. As a result, the output of gate 304 goes high, causing the output of gate 300 to change from a higll to a low, thus producing the falling pulse edge that sets flip-flop 298 to its 0 state.
With flip-flop 298 in its 0 state, the output of gate 320 can no longer yo low, thus preventing the writing of any further data into memory for the remainder of the overall operation. In addition to having this effect, the return of b flip-flop 298 to its 0 state causes the control input of multi-plexer 284 to go low.
As a result, multiplexer 284 will connect the ordered -address at its lower set of input pins (see Figure 15) to its output in place of the upper set of inputs. Now, the states of NcLocK (i.e., the ordered addresses) will be applied in numerical order to the address input of memory 282. Thus, the words in memory 282 will be read out to a digital to analog converter 340 (see Figure 15) in the numerical order of the NCLocK addresses as listed in the first column of Table I, starting with NcLocK=
2 and going to 1111111112.
Accordingly, at the start of the read-out operation, the data word at address 2 will first be read out of memory 282 and fed to converter 340. Upon the transition of GY

: ' : , , 22.34 NCLocK to oo~or~ 2~ tllc data ~ord at address O~r)~ J(~(),l,~ wi!J
be read out and fed to conv~rtcr 3~0. Th~s ~ NCLoK advance, in nu~erical ord~r from 000000000~ to 1111111112, the data words at addresses 2 to 1111111112 will successively be read out in the numerical order of the addresses.
Converter 340 may be any suitable type, such as the one shown in Figure 1, for converting each read-out binary word into an analog value that is representative of the binary ; word's value. The analog output of converter 3~0 is fed to a display 342, such as an oscilloscope or a strip chart reader (such as the one shown in Figure 1) which displays all of the analog values for the binary words that are read out of memory .
282 in a continuous wave form or curve. If display 342 is an ~ ' oscilloscope, it will be appreciated that the continuous wave form generated from the analog output of converter 340 will be -retraced each time NCLocK is recycled in the read-out operation.
Recycling will continue to repeatedly read out the data stored in memory 282 until power is removed from the circuit.
From the foregoing description it is clear that the relative data ages (columns 2 and 3 of Table I) associated with the bits in any given word in memory will be the same. Accord- ,, -' -' ~ ingly, the age difference (column 4 or column 5 of Table I) associated with all the bits in any given words in memory will ';~
be identical. This signifies that all of the bits in any given word in memory will be the result of scanning the same location ` of pipe 26.
' A comparison of the fourth and last columns in Table I ~
establishes that the encoded addresses select the locations for ;~ -storing data in memory 282 in such a way that the age differences "
(column 4 of Table I) associated with the stored data incremently decreases from a maximum in one direction to zero and then 3~

increment:ally incrcase to J maximum in the oi~o-;ite dir~c~ion, all in numerical order o the adclre~; cs.
Accordingly, the fi~3ures ~n -the fifth cGl~n of T~ble I represent the time delay of the channel A relative to channel B bits in each pair of bits that are concomitantly fed to the CG~-relator gate 66. Thus, a zero delay is associated with each bi~
in the word at address 12 to signify that the bits in this data word were obtained by scanning the location of pipe 26 exactly between geophones 22 and 24. As shown in the fifth column of Table I, the total net delays (i.e., fixed plus variable ` delays) associated with the memory's addresses progressively and numerically increase in the numerical order of the addresses, ` thus indicating the scanning of pipe 26 incrementally progresses from near geophone 24 to near geophone 22 in the numerical order of the addresses.
The read-out of the stored words in memory 282 in ` numerical order of the memory's address, as is done in the read-out operation by the "ordered addresses", thus provides the dis-play of a continuous curve that initiates from a point at ; 20 geophone 24 and progresses along pipe 26 to a point at geophone 22. As the variable time delay between channel A and B data is incrementally, but non-progressively, changed by shift register -208 the extent of correlation between the channel A and B data will vary from some minimum value to a maximum. The value of ; each data word in memory 282 will be a function of and vary with the extent to correlation that is associated variable time delay established between the channel A and B data. Consequently, ` the stored data word associated z~

associated with the variable time delay that produces maximum correlation between the channel A and channel B data will have the maximum value.
The maximum analog value at the output of converter 340 and, hence, the high point or region on the curve generated by display 342 will therefore be indicative of the pipe location where the maximum correlation occurs and hence of the location of the leak in a manner similar to the first embodiment.
Figure 16 shows an example of the display curve or wave form that is generated on the screen of an oscilloscope in response to the outputs of converter 340. The location of the leak is established by reading off the distance from the midpoint between the extremities to the high point on the displayed curve.
This distance can be converted into feet or other units of measurement knowing that d=c(tAA-tBB)/2 ~Formula 3).
In both of the embodiments shown in Figures 1 and 10, it will be appreciated that the vibration produced by the leak is intercepted at se~ected spaced apart points along the path of the pipe by microphones or other transducers, that the inter- ~
cepted vibration at each of these points is converted into a ~ ~ -digital signal to provide two digital signals that are miscorre-lated to an extent determined by the location of the leak from the - -two interception points, and that the extent of corre~ation of the two signals is varied by variably time delaying one of the digital signals relative to the other to determine the leak's - -location from the occurrence of maximum correiation between the - -two signals. In the first embodiment, a variable length delay line _ 71 -D

.. . . . . . . . . . . . .

is used and pro(lllc~s a p~o~l~c:siv~]y ch(1ngirlg limc d~ y. Ir, the se~oncl ~m},o~liment vari~l~]~ time delay line is circu]clting and prod~lces a t;me de1ay that chang~s n a non-prog~(ssive marlr~r with respect to the relative age of thc digital siynal data. In both embodiments the results are the same in that both embodime,l~s accumulate a record of data signal comparisons between the two data signals and then graph or display the conparisons as a function of relative age be~ween the two data signals used to produce the signal comparisons.
In addition to being faster in operation than ~he first embodiment, the second embodiment also enhances the displayed output wave form because there is less variation due to noise; that is noise in the second embodiment affects all re-lative correlations the same way.
It will be appreciated that the modification shown in Figure 7 of the drawings is applicable to the embodiment shown in Figure 10 as well as the embodiment of Figure 1.
The term "correlator" as ùsed in the patent claims here-in is intended to cover an exclusive NOR gate, an exclusive OR
gate, or any other circuit that compares a pair of data bits and produces an output of one binary state when the binary values of the compared data bits are the same and an output of the other binary state when the binary values of the compared data bits are not the same.
It also will be appreciated that time delay, analyzing, ~ -memory storage and memory addressing circuitry shown in Figures 10 and 15 may be employed for purposes other than locating a leak in a pipeline. This part of the illustrated apparatus may be used for treating any data where it is desirable to variably time delay the data signals in one data channel relative to data in another channel and to store data relating to the signals at memory locations that have a predetermined relationship to the relative data ages.
D ~

ZZ3~
When this part of the circuit~y i,s us~-~d fox pu~r~vr,,es oth(r 1kar~
locating a fluid leak gate 66 will not necesGari,ly be an exclusivfS
OR or an exclusi~e NOR gate, but may b~ any other type vf' logic gate (such as an AND gate, a NANI> gate, arl OR ~ate or a NOR gate) depending upon the particular requiremcnts for a given application.
In the embodiment shown in Figure 10, it will be -appreciated that the time required to replace all old data in shift register 208 with all new data is 512TSLow. In other words the time delay between adjacent bits in time is TSLow. Accord-ingly, it will be appreciated from the previously given formula ~, (3) that Qd=cTsLow/2 where ~d is the spacing between adjacent scanned locations along the pipe or, more generally, the distance over which the sound propagates in a time period equal to the -~
period of the TsLow pulse wave form; and c is the speed of sound in theselected medium (e.g., water). -~
From this formula it is e~ident that TSLow sets the resolution of pipe locations scanned by the apparatus of,Figure 10.
If l/TsLow is increased, then it is apparent from thé formula that -~d becomes smaller, thus increasing the resolution per unit length - ~
' of pipe. For con~enience, an adjustable resolution may be - '' provided as shown in Figure 18. ~ ~ ' Referring to Figure 18, the circuit for adjusting the resolution comprises a multiplexer 350, à pair of tens counters ,~... . ..
352 and 354 each having -2 and '.5 outputs, a pair of JK flip-flops 356 and 358 and a square wave oscillator 360. In this ' ,' embodiment, multiplexer 350 has six inputs and is operated by a suitable multiple position switch 362 to connect any selected one ' of the six inputs to the multiplexer's output.

- 30 The output of multiplexer 350 feeds the TFAST/2 counter stage of master clock 210 which in turn feeds the TFAST counter stage, and so on. As shown, the'.2 output of counter 352 is connected to the first input ~000) of multiplexer 350, the .5 , output of counter 352 is connected to the second input (001) of --;4;-- i . , i~2~

multiple;~er 35r), the ~ output o~ 1ip~flop 356 i.s connectc~ . o thc~ ~hird input ~010) of multiple~er 35~, the .2 output of counter 354 is connec~cd to the fourth input (011) of multiple~er 350, the 5 output of counter 35~ is connected to the fiftn input (100) multiple~er 352, and the Q output of flip-10p 358 is connected to the sixth input (101) of multiplexer 350.
Counters 352 and 354 may be of the 7490 type. As shown, oscillator 360 feeds the A and B inputs of counter 352, and the -5 output of counter 352 is used to feed the clock input of flip-flop 356. The Q output of flip-flop 356 is used to feed the A and B inputs of counter 354, and the .5 output of counter 354 feeds the clock input of flip-flop 358. The J and K inputs of each of the flip-flops 356 and 358 are connected to a positive d.c. voltage source representing the logic 1 state, and each flip-flop is wired to complement on each falling pulse edge at its clock input.
With these circuit connections it is apparent that the frequency of the pulse wave form at the multiplexer's input 000 is the oscillator frequency divided by two, that the fre~uency of the pulse wave form at the multiplexer's input 001 is the os-cillator frequency divided by five, that the frequency of the pulse wave form at the multiplexer's input 010 is the oscillator frequency divided by 10 and so on. Hence, the periods of pulse wave forms at the inputs to multiplexers 350 increase in numerical order of the addresses shown for the multiplexer's six inputs.
Operation of switch 362 selects any one of these pulse wave forms.
The periods of the pulse wave forms at the master clock's outputs TFAsT/2 through 512TFAST will be determined by the period of the selected pulse wave form that is fed from one of the inputs of multiplexer 350 to the multiplexer's output. In this fashion the scanning resolution is adjustable to any selected one of six different values that are respectively determined by the frequencies of the pulse wave forms at the six inputs of multi-~_ :
: , , . , . .. :

- lC3~Z~

plexer 350. The rc~solt1tion for a given pipe spclrl is f~hown in each of the multiplexer's SiY~ inp~ts i.n l~igure 1~.
The invention may be embodic-~d in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rathern than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
What is claimed and desired to be secured by Letters . Patent i5:

-- .

Claims (41)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In an apparatus for locating a fluid leak in an underground or unexposed pipe or conduit, first means effective upon receipt of a vibration caused by the leak for producing an electrical signal corresponding in phase and frequency to the received vibration, second means effective upon receipt of the vibration for producing a further electrical signal corresponding in phase and frequency to the received vibration, electrical time delay circuit means electrically connected to said first means for variably time delaying one of said electrical signals relative to the other to cause maximum mutual time correlation between the two signals, and means providing an indication of the time correlation between the time delayed one of said signals and the other of said electrical signals.

2. The apparatus defined in claim 1 wherein said electrical time delay circuit means comprises a recirculating time delay line.

3. The apparatus defined in claim 1 wherein said electrical time delay circuit means comprises a variable length, non-recirculating time delay line.

4. In an apparatus for locating a fluid leak in an underground or un-exposed pipe, first means for intercepting a vibration produced by the leak at two spaced apart points and for converting the vibration intercepted at each of said points into an electrical signal to provide two electrical signals that are miscorrelated in time to an extent determined by the location of the leak from said points, an electrical circuit electrically connected to said first means and including time delay means for varying the extent of time correlation between at least samples of said two signals to cause maximum time correlation therebetween and means providing an indication of the variation of the extent of time correlation between the samples to enable the leak's location to be determined from the occurrence of the maximum time correlation.

5. The apparatus defined in claim 4 wherein said first means comprises a pair of stationarily positioned microphones adapted to be located one at each of said interception points to intercept said vibration

6. The apparatus defined in claim 4 wherein said interception points are selectively located along the path of said pipe, and wherein said first means comprises a pair of microphones adapted to be located one at each of said interception points.

7. The apparatus defined in claim 4 wherein said time delay means comprises a time delay line for variably time delaying at least samples of one said signals relative to the other.

8. The apparatus defined in claim 4 wherein said time delay means comprises a recirculating time delay line for variably time delaying at least samples of one of said signals relative to the other.

9. The apparatus defined in claim 4 wherein said signals are digital signals and wherein said time delay means comprises a recirculating time delay line for variably time delaying samples of one of said signals relative to samples of the other of said signals, means for periodically entering samples of said one of said signals into said delay line at a first predetermined rate, and means for recirculating the samples in said delay line at a rate that is faster than said first predetermined rate.

10. The apparatus defined in claim 4 wherein said signals are digital signals, and wherein said time delay means comprises a first circulating shift register for variably time delaying samples of one of said signals relative to the other, means for periodically entering samples of said one of said signals into said first register at a first predetermined rate, means for circulating the contents in said first register at a second pre-determined rate that is faster than said first predetermined rate, and a second circulating shift register for delaying samples of the other of said signals, said second shift register being clocked to circulate the samples of said other of said signals at said first predetermined rate, and said second register having a bit length that is shorter than that of said first register.

11. The apparatus defined in claim 4 wherein said time delay means comprises a variable length delay line for variably delaying at least samples of one of said signals relative to the other, and means for progressively varying the length of said delay line to cause the variation in the extent of correlation between the signals.

12. The apparatus defined in claim 11 wherein said electrical circuit comprises a further delay line of fixed, pre-selected length for delaying at least samples of the other of said signals.

13. In an apparatus for locating a fluid leak in an underground or unexposed pipe, first means for intercepting a sound wave produced by the leak at two separate points spaced apart along the path of the pipe and for producing two electrical signals having a phase difference which is related to the difference in time required for the wave to propagate to the intercep-tion points, said first means having a pair of microphones adapted to be positioned one at each of said interception points to intercept said sound wave, an electrical circuit connected to said first means and including time delay means for progressively phase shifting at least one of said signals to cause at least momentarily maximum mutual phase correlation between the two signals, means providing an indication which is a function of the degree of mutual phase correlation between the phase shifted signal and the other of said signals as said one of said signals is progressively phase shifted to indicate the occurrence of maximum mutual phase correlation between the two signals, and means providing a measurement which is a function of the distance of the leak from a known predetermined point at the time maximum mutual phase correlation occurs when the leak is located between the two microphones or at either one of the microphones.

14. The apparatus defined in claim 13 wherein said electrical circuit further includes selectively adjustable delay means for delaying the other of said signals by a fixed selected amount.

15. In an apparatus for locating fluid leak in an underground or unexposed pipe, first and second trans-ducers adapted to be positioned at spaced apart regions along the path of the pipe to intercept a vibration produced by the leak and propagating along the pipe, each of said transducers being effective to convert the intercepted vibration into an electric wave, a circuit for modifying the electric waves pro-duced by said transducers into first and second pulse signals having a phase difference which is related to the location of the leak from said transducers, means in said circuit for pro-gressively phase shifting one of said pulse signals relative to the other pulse signal to cause at least momentarily maximum mutual phase correlation between said first and second pulse signals, means electrically connected to said circuit for producing a further pulse signal which is a measure of the degree of mutual phase correlation between the phase shifted pulse signal and other pulse signal, and means controlled by said further pulse signal for providing an indication which is a function of the degree of mutual phase correlation between the phase shifted pulse signal and said other pulse signal to indicate the occurrence of maximum mutual phase correlation between the phase shifted pulse signal and the other pulse signal.

16. The apparatus defined in claim 15 comprising means providing a distance measurement which is a function of the location of the leak from a known predetermined point at the time maximum mutual phase correlation occurs between the phase shifted pulse signal and the other of said first and second pulse signals.

17. In an apparatus for locating a fluid leak in an underground or unexposed pipe, first means for intercepting a vibration produced by the leak at two spaced apart points and for converting the intercepted vibration into first and second electrical signals having a phase difference which is function of the difference in time required for the vibration to propagate to said points, selectively operable switching means electrically connected to said first means, a variable time delay line electrically connected to said switching means, a phase correlation measuring means electrically connected to said time delay line and to said switching means, said switch-ing means having a first switching position in which it feeds said first signal to said time delay line and in which it bypasses said second signal around said time delay line and feeds the second signal to said measuring means, said switching means having a second switching position in which it feeds said second signal to said time delay line and in which it bypasses said first signal around said delay line and feeds the first signal to said measuring means, means for varying the delay of said delay line to delay the signal fed to the delay line by said switching means, and said measur-ing means being effective to produce a further signal which is a function of the extent of phase correlation between the delayed signal from said delay line and the other signal which is bypassed around said delay line by said switching means.

18. In an apparatus for locating a fluid leak in an undergroud or unexposed pipe, first and second circuits each having (a) a microphone for intercepting the vibration produced by the leak to produce an a.c. signal, and (b) a polarity detector for detecting each alternation of one pre-selected polarity of said signal to produce a pulse wave form, at least one of said first and second circuits having a time delay line for delaying the pulse wave form developed by the polarity detector in one of said circuits relative to the pulse wave form developed by the polarity detector in the other of said first and second circuits, means for varying the delay of said delay line over a pre-selected range, and phase correla-tion measuring means electrically connected to said first and second circuits for producing a signal which is a function of the phase difference between the pulse wave form which is delayed by said delay line and the pulse wave form developed in said other of said first and second circuits.

19. In an apparatus for locating a fluid leak in an underground or unexposed pipe, means for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at each of said points into an electrical digital signal to provide two signals that are miscorrelated to an extent determined by the location of the leak from said points, means variably time delaying one of the signals relative to the other of said signals for varying the extent of correlation between said signals to achieve maxi-mum correlation between the signals, and means for displaying the variations of the extent of correlations between the time delayed signal and the other of said signals to enable the location of the leak to be determined from the place at which the maximum correlation occurs.

20. The apparatus defined in claim 19 wherein said means for time delaying said one of said signals comprises a recirculating delay line.

21. The apparatus defined in claim 19 wherein said means for time delaying said one of said signals comprises a variable length time delay line and means for incrementally and progressively varying the length of said delay line.

22. In an apparatus for locating a fluid leak in an underground or unexposed pipe, means for intercepting a vibration produced by said leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at each of said points into a digital signal to pro-vide two digital signals that are related in phase to the location of the leak from said points, a circulating time delay line for time delaying samples of one of said signals relative to the other, a correlator for comparing the time delayed samples of said one of said signals with at least samples of the other of said signals, and means responsive to the output of said correla-tor for enabling the location of said leak to be established.

23. The apparatus defined in claim 22 wherein said time delay line comprises a circulating shift register, and means for periodically entering samples of said one of said signals into said shift register at a rate that is slower than the rate at which the samples are recirculated by said shift register.

24. The apparatus defined in claim 22 wherein said signal samples are in the form of binary bits and wherein said correlator comprises a logic gate that produces a binary output of one logic state when the compared signal samples have the same logic state and a binary output of the other logic state when the logic states of the compared signal samples are not the same.

25. The apparatus defined in claim 24 wherein said delay line non-progressively variably delays samples of said one of said signals in a scrambled, but predetermined order, and wherein said means responsive to the output of said correlator comprises a memory having a multiplicity of addresses for storing binary data, means for addressing said memory for storing data determined by the output of said logic gate at addresses in the memory that are determined by the time delays of the samples of said first signal relative to the samples of said second signal, and means for reading the data out of said memory in a predeter-mined order that is different from the order in which the data is written into the memory.

26. In an apparatus for locating a fluid leak in an underground or unexposed pipe, means for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at said points into two digital signals that are related to the location of the leak from said interception points, means for variably time delaying one of said signals relative to the other to vary the extent of correlation between the two signals, and means for indicating the varied extent of correla-tion to provide an indication of the location of the leak.

27. The apparatus defined in claim 26 wherein said means for variably time delaying said one of said signals comprise a circulating time delay line and means for circulating samples of said one signal through said delay line at a rate that is faster than the rate at which samples of said one signal are entered into said delay line.

28. An apparatus for locating a fluid leak in an underground or unexposed pipe comprising means for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of the pipe and for converting the vibration intercepted at said points into two digital signals that are related in phase to the location of the leak from said points, and means for scanning at least a portion of said pipe between said points for the location of said leak by variably time delaying samples of one of said signals relative to samples of the other of said signals.

29. The apparatus defined in claim 28 wherein said scanning means scans spaced apart locations of said pipe portion for said leak, and wherein means are provided for selectively adjusting the scanning resolution of said scanning means.

30. A method of locating a fluid leak in an underground or unexposed pipe comprising the steps of intercepting the vibration produced by the leak at two spaced apart points and converting the vibration intercepted at each of said points into an electrical signal to provide two electrical signals that are miscorrelated in time to an extent determined by the location of the leak from said points, electrically processing at least one of said signals by varying the extent of time correlation between the two signals to cause maximum time correlation between the signals, and deter-mining the location of the leak from the occurrence of said maximum corre-lation.

31. A method of locating a fluid leak in an underground or unexposed pipe comprising the steps of intercepting the vibration produced by the leak at two selected points spaced apart along the path of the pipe and con-verting the vibration intercepted at each of said points into an electrical signal to provide two electrical signals that are miscorrelated in time to an extent determined by the location of the leak from said points, elec-trically processing at least one of said two signals by variably time delay- ---ing one of said signals relative to the other without changing the selected points at which the vibration is intercepted to vary the extent of time correlation between the signals, and determining the location of the leak from the variation of the extent of time correlation between the signals.

32. The method defined in claim 31 comprising the step of locating said interception points on opposite sides of the suspected site of the leak.

33. The method defined in claim 32 comprising the step of time delay-ing the other of said signals by a fixed selected amount during the course of variably time delaying said one of said signals.

34. The method defined in claim 33 comprising the step of time delay-ing the other of said signals during the course of variably delaying by a fixed time equal to the time required for said vibration to propagate the length of the pipe between the two interception points.

35. The method defined in claim 32 comprising the step of imparting no delay to the other of said signals.

36. In an apparatus for locating a fluid leak in an underground or unexposed pipe, first means including a pair of transducers for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at each of said points into a digital signal to provide two digital signals that are miscorrelated to an extent determined by the location of the leak from said points, a recirculating time delay line, means for electrically connecting said delay line to a part of said first means and for entering digital bits of one of said signals into said delay line at a first predetermined rate, means for circulating the digital bits entered into said delay line at a second predetermined rate to variably time delay the bits of said one of said signals relative to digital bits of the other of said signals and to thereby vary the extent of correlation between the bits of said one of said signals and the bits of the other of said signals to achieve maximum correlation between the bits of said one of said signals and the bits of the other of said signals, said second predetermined rate being faster than said first predeter-mined rate, and means providing a read-out of the variations of the extent of correlation between the bits of said one of said signals and the bits of said other of said signals to enable the location of the leak to be determined from the occurrence of the maximum correlation between the bits of said one of said signals and the bits of the other of said signals.

37. In an apparatus for locating a fluid leak in an underground or unexposed pipe, first means including a pair of transducers for intercepting a vibration produced by the leak at two selected points that are spaced apart along the path of said pipe and for converting the vibration intercepted at each of said points into a digital signal to provide two digital signals that are miscorrelated to an extent determined by the location of the leak from said points, a recirculating shift register having a pre-selected bit length, means electri-cally connecting said shift register to a part of said first means for entering digital bits of one of said signals into said shift register every time the shift register completes a pre-selected number of shifts, where said pre-selected number of shifts and said pre-selected bit length of said shift register have no common factors to enable said shift register to be filled up with digital signal bits of different relative ages, means for cir-culating the bits entered to said shift register at a predeter-mined rate to variably time delay the bits of said one of said signals relative to digital bits of the other of said signals and to thereby vary the extent of correlation between the bits of said one of said signals and the bits of the other of said signals to achieve maximum correlation between the bits of said one of said signals and the bits of the other of said signals, said predetermined rate being faster than the rate at which bits of said one of said signals is entered into said shift register, and means providing a read-out of the variations of the extent of correlation between the bits of said one of said signals and the bits of said other of said signals to enable the location of the leak to be determined from the occur-rence of the maximum correlation between the bits of said one of said signals and the bits of the other of said signals.

38. In an apparatus for locating a fluid leak in an underground or unexposed pipe, first and second circuits each having (a) a microphone for intercepting the vibration produced by the leak to produce a first a.c. signal, (b) an envelope detector responsive to said first a.c signal for developing a further a.c. signal which follows the envelope of said first a.c. signal and (c) a polarity detector for detecting each alternation of one pre-selected polarity of said further signal to produce a pulse wave form, at least one of said first and second circuits having a time delay line for variably time delaying the pulse wave form developed by the polarity detector in one of said circuits relative to the pulse wave form developed by the polarity detector in the other of said first and second circuits to vary the extent of correla-tion between the pulse wave forms and means for indicating the variation of the extent of correlation between the pulse wave forms to enable the location of the leak to be determined from the occurrence of maximum correlation between the two pulse wave forms.

39. An apparatus for locating a fluid leak in an undergroud or unexposed pipe or conduit, said apparatus comprising first means effect-ive upon receipt of a vibration caused by the leak for producing an electrical digital signal corresponding in phase and frequency to the received vibration, second means effective upon receipt of the vib-ration for producing a further electrical digital signal corresponding in phase and frequency to the received vibration, electrical circuit means for variably time delaying one of said electrical signals relative to the other to cause maximum mutual correlation between the two signals, and means providing an indication of the correlation between the time delayed signal and the other signal, said electrical circuit means comprising a recirculating time delay line.

40. An apparatus for locating a fluid leak in an underground or un-exposed pipe or conduit, said apparatus comprising first means effective upon receipt of a vibration caused by the leak and producing an electrical digital signal corresponding in phase and frequency to the received vibration, second means effective upon receipt of the vibration for produc-ing a further electrical digital signal corresponding in phase and frequency to the received vibration, electrical circuit means for variably time delay-ing one of said electrical signals relative to the other to cause maximum mutual correlation between the two signals, and means providing an indication of the correlation between the time delayed signal and the other signal, said electrical circuit means comprising a variable length, non-recirculating time delay line.

41. An apparatus for locating a fluid leak in an underground or un-exposed pipe comprising first and second electrical circuits each having (a) a microphone for intercepting the vibration produced by the leak and (b) means connected to the microphone for producing an electrical digital signal related in phase and frequency to the vibration received by the microphone, said microphones being adapted to be located at two spaced apart points on opposite sides of the leak to cause said signals to be miscorrelated in time to an extent determined by the location of the leak between said points, at least one of said first and second circuits having a time delay line for variably time delaying one of said digital signals relative to the other to cause maximum mutual time correlation between the two signals, and means electrically connected to said first and second circuits and providing an indication of the extent of time correlation between said signals to enable the leak's location to be determined from the occurrence of the maxi-mum mutual time correlation between the two signals.