Device and method for multi-level charge/storage and reading out

United States Patent

[19]

Montanari et al.

US006115285A [ii] Patent Number: [45] Date of Patent:

6,115,285 Sep. 5,2000

§ 102(e) Date: Dec. 14, 1998 [87] PCT Pub. No.: WO97/48099 PCT Pub. Date: Dec. 18, 1997

Related U.S. Application Data

[60] Provisional application No. 60/019,812, Jun. 14, 1996, and provisional application No. 60/020,037, Jun. 21, 1996.

[51] Int. C I. G11C 16/04

[52] U.S. CI 365/185.03; 365/185.2;

365/185.26

[58] Field of Search 365/185.29, 185.03,

365/185.2, 185.26, 185.28, 185.14, 185.01

[56] References Cited

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OTHER PUBLICATIONS

Etiemble et al., "Coneption Avec Regies En Lambda D'une Rom 4-Valuee", Revue de Physique Appliquee, vol. 20, No. 2, pp. 71-75.

Primary Examiner—David Nelms

Assistant Examiner—-Thong Le

Attorney, Agent, or Firm—Hill & Simpson

The present invention discloses a memory device having memory cells capable ol storing three or more charge leves in said memory cell. The cells can be programmed according to a method including a single pulse charge level injection mechanism in said cells. The method does not require a program verify scheme, permits increased speed during programming, and reduces the area necessary for storing one bit of information. The memory device of the present invention further includes information write or storage or programmation means, information erase means and information read-out means. Another object of the present invention is to provide a method and a circuit that implements said method for determining the charge level of a memory cell having t possible levels (t being larger than or equal to three). The circuit measures the similarity of the memory cell drain current with the drain current of each of n references, determines the one reference which is the most similar to the memory cell and thereby identifies the charge level of said memory cell.

15 Claims, 12 Drawing Sheets