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(12) United States Patent ao) Patent No.: Us 7,036,106 Bi

Wang et al. (45) Date of Patent: Apr. 25,2006 Page 2

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5,544,067 A 8/1996 Rostoker et al 364/489

5,555,201 A 9/1996 Dangelo et al 364/489

5,572,437 A 11/1996 Rostoker et al 364/489

5,613,098 A 3/1997 Landau et al 395/500

5,623,418 A 4/1997 Rostoker et al 364/489

5,696,956 A 12/1997 Razdan et al 395/568

5,748,875 A 5/1998 Tzori 395/183.05

5,748,979 A 5/1998 Trimberger 395/800.37

5,801,958 A 9/1998 Dangelo et al 364/489

(Continued)
FOREIGN PATENT DOCUMENTS
EP 0 743 599 11/1996

(Continued)

OTHER PUBLICATIONS

Fauth et al., "Describing Instruction Set Processors Using nML," ED&TC 1995, Proceedings, Paris, France Mar. 6-9, 1995, Los Alamitos, CA, USA, IEEE Comput. Soc. US, Mar. 6, 1995, pp. 503-507.

(Continued) Primary Examiner—Thuan Do

(74) Attorney, Agent, or Firm—Pillsbury Winthrop et al

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A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

38 Claims, 12 Drawing Sheets

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U.S. PATENT DOCUMENTS

5,819,064 A 10/1998 Razdan et al 395/500

5,832,205 A 11/1998 Kelly et al 395/185.06

5,857,106 A 1/1999 Barbour et al 395/709

5,867,399 A 2/1999 Rostoker et al 364/489

5,887,169 A 3/1999 Lacombe 395/681

5,889,990 A 3/1999 Coleman et al 395/682

5,896,521 A 4/1999 Shackleford et al 395/500

5,918,035 A 6/1999 Van Praet et al 395/500

5,933,356 A * 8/1999 Rostoker et al 703/15

5,995,736 A 11/1999 Aleksic et al 395/500.19

5,999,730 A 12/1999 Lewis 395/702

6,006,022 A 12/1999 Rhim et al 395/500.02

6,028,996 A 2/2000 Sniderman et al 395/500.49

6,031,992 A 2/2000 Cmelik et al 395/705

6,035,123 A 3/2000 Razdan et al 395/709

6,052,524 A 4/2000 Pauna 395/500.43

6,058,466 A * 5/2000 Panwar et al 712/15

6,075,938 A 6/2000 Bugnion et al 395/500.48

6,078,736 A 6/2000 Guccione 395/500.17

6,216,216 Bl 4/2001 Bonola 712/28

6,230,307 Bl 5/2001 Davis et al 716/16

6,269,409 Bl 7/2001 Solomon 709/329

6,275,893 Bl 8/2001 Bonola 710/262

6,282,633 Bl 8/2001 Killian et al 712/208

6,295,571 Bl 9/2001 Scardamalia et al 710/129

6,321,323 Bl 11/2001 Nugroho et al 712/34

6,385,757 Bl* 5/2002 Gupta et al 716/1

6,415,379 Bl 7/2002 Keppel et al 712/209

6,477,683 Bl 11/2002 Killian et al 716/1

6,477,697 Bl* 11/2002 Killian et al 716/18

6,496,847 Bl 12/2002 Bugnion et al 709/1

6,615,167 Bl 9/2003 Herzl et al 703/28

6,658,578 Bl * 12/2003 Laurenti et al 713/324

FOREIGN PATENT DOCUMENTS

EP 0 772 140 5/1997

OTHER PUBLICATIONS

Hartoog et al., "Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign," Proceedings of the Design Automation Conference, Anaheim, CA, USA, Jun. 9-13, 1997, pp. 303-306. Fauth et al., "Generation of Hardware Machine Models from Instruction Set Descriptions," VLSI Signal Processing, VI, 1993, Workshop on Veldhoven, Netherlands, Oct. 20-22,

1993, New York, NY, USA, IEEE, Oct. 20, 1993, pp. 242-250.

Lecarme et al., Software Portability, 201 1996 McGraw-
Hill, Inc.

Singh et al., "Accelerating Adobe Photoshop with
Reconfigurable Logic," FPGAs for Custom Computing
Machines, 1998, pp 236-244, XP-010298165.
Cygnus Solutions: "eCos Reference Manual—Version 1.2.
1" eCos Project Documentation, 'Online! May 17, 1999,
XP-002192658.

Bursky, "Tool suite enables designers to craft customized embedded processors" Electronic Design, Feb. 8, 1999, Penton Publishing, USA 'Online! vol. 47, No. 3, XP002192659.

Stewart et al., "The Chimera II real-time operating system
for advanced sensor-based control applications," IEEE
Transactions on Systems, Man and Cybernetics, vol. 22,
Issue 6, Nov./Dec. 1992, pp 1282-1295.
Box, "Field programmable gate array based reconfigurable
preprocessor," IEEE Workshop on FPGAs for Custom
Computing Machines, Proceedings, 10-13 1994 pp. 40-48.
Gonzalez, "Configurable and Extensible Processor Change
System Design," Tensilica, Inc., Hot Chips 1999.
"Accelerated Technology and Tensilica Alliance Provide
Comprehensive Hardware and Software Solution with
Nucleus PLUS Support for the Extensa Processor," Feb. 29,
2000, Press Release at Embedded Systems Conference,
Spring 2000.

Compton et al., "Confgurable Computing: A Survey of
Systems and Software," Technical Report, Northwestern
University, Dept. of ECE, 1999.

Hauck et al., "The Chimaera Reconfigurable Functional Unit," Proceedings of the IEEE Symposium on FieldProgrammable Custom Computing Machines, 1997. Razdan et al., "A High-Performance Microarchitecture with Hardware-Programmable Function Units," Proceedings of MICRO-27, Nov. 1997.

Wang et al., "Hardware/Software Instruction Set Configurability for System-on-Chip Processors," Proceedings of Design Automation Conference, 2001.

* cited by examiner

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