Method and system for executing a context-altering instruction without ...

United States Patent [w]

Golla et al.

US005898864A [ii] Patent Number: [45] Date of Patent:

5,898,864 Apr. 27, 1999

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OTHER PUBLICATIONS

IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1988, "Fast Parallel Processor Notification".

Primary Examiner—Kenneth S. Kim

Attorney, Agent, or Firm—Casimer K. Salys; Antony P. Ng;

Andrew J. Dillon

[57] ABSTRACT

A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register. Finally, the first state of the machine state register is altered to the second state in response to a completion of the context-altering instruction. As a result context synchronization operations are avoided.

12 Claims, 6 Drawing Sheets

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