Universal buffered interface for coupling multiple processors, memory units ...

United States Patent [w]

Garcia

US005870572A [ii] Patent Number: [45] Date of Patent:

5,870,572 Feb. 9, 1999

[54] UNIVERSAL BUFFERED INTERFACE FOR COUPLING MULTIPLE PROCESSORS, MEMORY UNITS, AND I/O INTERFACES TO A COMMON HIGH-SPEED INTERCONNECT

[75] Inventor: Armando Garcia, Yorktown Heights, N.Y

[73] Assignee: International Business Machines Corporation, Armonk, N.Y.

[21] Appl. No.: 798,186

[22] Filed: Dec. 23, 1996

Related U.S. Application Data

[62] Division of Ser. No. 260,107, Jun. 15, 1994, Pat. No. 5,588,122, which is a continuation of Ser. No. 734,206, Jul. 22, 1991, abandoned.

[51] Int. CI. G06F 15 16

[52] U.S. CI 395/309

[58] Field of Search 395/200.43, 200.75,

395/291, 200.3, 309

[56] References Cited

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FOREIGN PATENT DOCUMENTS

0513519A1 11/1992 European Pat. Off. .

Primary Examiner—David Y. Eng

Attorney, Agent, or Firm—Perman & Green, LLP

A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least one shared global memory with memory banks, and a number of bus interfaces each coupled between one of a set of local buses and a global bus. Each interface includes a number of input queues and output queues coupled between the local bus and the global bus. The interface supports the use of an interprocessor communication (IPC) mechanism that allows any processor to send an interrupt to any other processor in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, with the interrupt mask identifying the processor or processors to be interrupted for interprocessor communication.

14 Claims, 33 Drawing Sheets