DEVICE AND METHOD FOR INTERFACING PCI AND VMEBUS WITH A BYTE SWAPPING CIRCUIT
 Inventors: Jeff Goode, 141 Loworn La.,
Huntsville, Ala. 35805; Stevens Robert, 128 Park Meadow Dr., Madison, Ala. 35758
 Appl. No.: 08/911,564  Filed: Aug. 14, 1997
 Int. CI.7 G06F 12/10; G06F 13/00
 U.S. CI 710/129; 710/128; 710/100
 Field of Search 395/500, 325,
395/309; 71/129, 128, 100, 106
 References Cited
U.S. PATENT DOCUMENTS
4,447,878 5/1984 Kinnie et al. .
5,083,259 1/1992 Maresh et al 395/325
5,255,374 10/1993 Aldereguia et al. .
5,265,237 11/1993 Tobias et al 395/500
5,313,231 5/1994 Yin et al 345/199
5,335,340 8/1994 Strong .
5,4i6,907 5/1995 Polzin et al. .
5,428,763 6/1995 Lawler .
5,522,050 5/1996 Amimi et al. .
5,796,963 8/1998 Odom 395/308
Black, John, "A Few Words From the Editor Byte Ordering Problems: Don't Let Them Catch You by Surprise", VMEbus System, Mar-Apr. 1987, pp. 31-36.
A byte-swapping circuit is provides for interlacing PCI systems to VMEbus systems. The circuit allows the PCI bus to selectively enable or disable byte swapping whether the VMEbus system is in master mode or slave mode. Also, the circuit delays the assertion ol the DS0/DS1 VMEbus signals until alter the byte swapping circuit has completed its operation, thus avoiding violations ol the VMEbus timing specification. Finally, the circuit optimizes its performance during block transler operations by maintaining its byteswapping configuration constant during each bus cycle in a given block transler. Thus, the circuit configures itself for the first bus cycle, but eliminates the reconfiguration delay for each bus cycle afterwards. The circuit can also byte-swap data bytes being transferred on the address bus during multiplexed block transfer cycles.
18 Claims, 10 Drawing Sheets