A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments...http://www.google.ca/patents/US7949978?utm_source=gb-gplus-sharePatent US7949978 - Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit
