A method for debug control in a pipelined data processor where an offset is determined for the program counter (PC) based on the state of the pipeline. The offset is subtracted from the PC value at the end of a debug session. The resultant PC value restarts fetching of a last unsuccessfully completed...http://www.google.ca/patents/US6591378?utm_source=gb-gplus-sharePatent US6591378 - Debug controller in a data processor and method therefor
