A memory controller features programmable delay buffers that allow the memory interface signals to be automatically adjusted. By fine tuning the delay values, the memory controller can compensate for impedance characteristics that affect the memory interface timing. The memory controller includes a built-in...http://www.google.ca/patents/US6137734?utm_source=gb-gplus-sharePatent US6137734 - Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals
