Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay...http://www.google.ca/patents/US7434187?utm_source=gb-gplus-sharePatent US7434187 - Method and apparatus to estimate delay for logic circuit optimization
