A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output...http://www.google.ca/patents/US20020057624?utm_source=gb-gplus-sharePatent US20020057624 - Delay-locked loop with binary-coupled capacitor
