A microprocessor cache configuration for reducing database cache misses and improving the processing speed, comprising a level-1 data cache, and a page prefetch cache. The page prefetch cache is adjacent the level-1 data cache. The page prefetch cache is configured to receive and store one or more database...http://www.google.ca/patents/US6848028?utm_source=gb-gplus-sharePatent US6848028 - Microprocessor having a page prefetch cache for database applications
