A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of...http://www.google.ca/patents/US5969986?utm_source=gb-gplus-sharePatent US5969986 - High-bandwidth read and write architectures for non-volatile memories
