An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller,...http://www.google.ca/patents/US5493684?utm_source=gb-gplus-sharePatent US5493684 - Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility
