An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request....http://www.google.ca/patents/US7149212?utm_source=gb-gplus-sharePatent US7149212 - Apparatus, method and limited set of messages to transmit data between scheduler and a network processor
