A test control circuit and method for performing a standardized test in a semiconductor memory device which has a structure such that it is difficult to perform a test operation using a standardized test mode. The test control method of a semiconductor memory device includes the steps of: arranging in...http://www.google.ca/patents/US5617366?utm_source=gb-gplus-sharePatent US5617366 - Method and apparatus for a test control circuit of a semiconductor memory device
