A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of...http://www.google.ca/patents/US5898864?utm_source=gb-gplus-sharePatent US5898864 - Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors
