An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment...http://www.google.ca/patents/US6782521?utm_source=gb-gplus-sharePatent US6782521 - Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
