A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments...http://www.google.ca/patents/US20040019891?utm_source=gb-gplus-sharePatent US20040019891 - Method and apparatus for optimizing performance in a multi-processing system
