An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder...http://www.google.ca/patents/US7890694?utm_source=gb-gplus-sharePatent US7890694 - Latched address multi-chunk write to EEPROM
