A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors...http://www.google.ca/patents/US6510533?utm_source=gb-gplus-sharePatent US6510533 - Method for detecting or repairing intercell defects in more than one array of a memory device
