An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus...http://www.google.ca/patents/US6604159?utm_source=gb-gplus-sharePatent US6604159 - Data release to reduce latency in on-chip system bus
