In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM...http://www.google.ca/patents/US5546346?utm_source=gb-gplus-sharePatent US5546346 - Semiconductor memory device
