A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and...http://www.google.ca/patents/US20020160628?utm_source=gb-gplus-sharePatent US20020160628 - Process for reducing the critical dimensions of integrated circuit device features
