WO2015169054A1

WO2015169054A1 - Method and device for realizing data consistency, and computer storage medium

Info

Publication number: WO2015169054A1
Application number: PCT/CN2014/088637
Authority: WO
Inventors: 寇楠; 刘卫; 李瑛�
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-05-07
Filing date: 2014-10-15
Publication date: 2015-11-12
Also published as: CN105095254B; CN105095254A

Abstract

Disclosed are a device and method for realizing data consistency, and a computer storage medium. The method comprises: when it is determined that a protocol corresponding to a received data consistency request is not supported, conducting protocol conversion processing on the received data consistency request; according to the data consistency request after the protocol conversion processing, determining a corresponding data consistency operation apparatus, and conducting a data consistency operation on the data consistency operation apparatus.

Description

Method, device and computer storage medium for realizing data consistency

Technical field

The present invention relates to the technical field of data storage consistency, and in particular, to a method, an apparatus, and a computer storage medium for implementing data consistency.

Background technique

Currently, multiple processors in an on-chip multiprocessor system have their own caches that affect system performance when guaranteeing data consistency between multiple caches and between cache and shared memory. And the accuracy of the system, therefore, how to more effectively ensure the consistency of data storage in the on-chip multiprocessor system is an important issue that needs to be solved urgently.

Summary of the invention

In view of the problems existing in the prior art, embodiments of the present invention provide a method and apparatus for implementing data consistency.

An embodiment of the present invention provides an apparatus for implementing data consistency, where the apparatus includes: a slave interface unit and a listening control unit;

The slave interface unit, configured to determine a protocol corresponding to the received data consistency request, performs protocol conversion processing on the received data consistency request, and sends the data conversion request processed by the protocol conversion to the monitoring control unit;

The monitoring control unit is configured to determine, according to the data consistency request sent by the slave interface unit, a corresponding data consistency operation device, and perform data consistency operation on the data consistency operation device.

In the above solution, the interception control unit is further configured to perform execution of two or more data consistency requests received when the received data consistency request is more than two data consistency requests. Arbitration is performed to determine a corresponding data consistency operation device according to the data consistency request after the arbitration, and perform data consistency operation on the data consistency operation device.

In the above solution, the slave interface unit is further configured to send the received data consistency request to the interception control unit when determining that the protocol corresponding to the received data consistency request is supported.

In the above solution, the slave interface unit includes: a first slave interface unit and a second slave interface unit; wherein

The first slave interface unit is configured to send the received first read data consistency request from the first master unit to the intercept control unit;

The second slave interface unit is configured to perform a protocol conversion process on the received data consistency request from the second master device unit, and send the protocol conversion processed data consistency request to the interception control unit.

In the above solution, the second slave interface unit is configured to: convert the data consistency request sent by the received second master unit to the Advanced Entity Interface (AXI) protocol into data supporting the ACE_Lite protocol. Consistency request; converts the number of bytes of the data-consistent request after the protocol conversion into the full cache data line Full Cache Line bytes.

In the above solution, the second slave interface unit includes: a protocol conversion subunit, a read operation conversion subunit, a read interface subunit, a write operation conversion subunit, and a write interface subunit; wherein

The protocol conversion subunit is configured to convert a data consistency request sent by the received second master unit to support the AXI protocol into a data consistency request supporting the ACE_Lite protocol;

The read operation conversion subunit is configured to convert, when the data consistency request sent by the second master device unit is the second read data consistency request, the number of bytes of the second read data consistency request after the protocol conversion is converted into Full cache data line Full Cache Line bytes;

The read interface sub-unit is configured to distribute a second read data consistency request channel for the second read data consistency request after the byte number conversion, and multiplex the read data channel;

The write operation conversion subunit is configured to convert, when the data consistency request sent by the second master device unit is the second write data consistency request, the number of bytes of the second write data consistency request after the protocol conversion is converted into Full cache data line Full Cache Line bytes;

The write interface sub-unit is configured to distribute a second write data consistency request channel for the second write data consistency request after the byte number conversion, and cache the write data response channel.

In the above solution, the second slave interface unit further includes: an arbitration subunit configured to: when receiving the data consistency request sent by the read interface subunit and the write interface subunit simultaneously, the byte Arbitration of the second read data consistency request after the number conversion and the execution of the second write data consistency request after the byte number conversion, and according to the second read data consistency request or the second write data after the arbitration The sexual request sends a corresponding data consistency request to the interception control unit.

In the above solution, the read interface sub-unit is further configured to block the transmission inter-transaction sequence.

In the above solution, the write interface sub-unit is further configured to block the transmission inter-transaction sequence, handle the write-before-write WAW, and the post-write RAW conflict.

In the above solution, the first slave interface unit is further configured to send a first write data consistency request from the first master unit to the interconnect unit, and directly initiate a write operation to the interconnect unit.

In the above solution, the interception control unit includes a mark control subunit and a data exchange subunit; wherein

The tag control subunit is configured to receive a first read and/or first write data consistency request sent by the first slave interface unit, a second read and/or a second write consistency request sent by the second slave interface unit And the invalidation request invalidate sent by the data exchange subunit, and arbitrate the execution of the requests; when the arbitrated request is the first read data consistency request or the second read data consistency request, according to the first read data consistency The request or the second read data consistency request looks up the tag memory. If the tag memory is found, the hit result is generated according to the full cache data line in the tag memory; if the full cache data line in the hit result is Full Cache Line If the status is valid, the monitoring request is sent to the data exchange sub-unit to obtain the read data; if the full cache data line in the hit result is a valid Cache Line, the full cache data line does not exist in the full cache data line, Then using the interconnection unit to obtain read data;

The data exchange sub-unit is configured to send the interception request to the first main device unit according to the hit information, receive the intercept response and the intercept data returned by the first main unit, and send the intercept data to the first slave interface unit. Or after the second slave interface unit, send a data consistency request operation completion indication to the first slave interface unit or the second slave interface unit.

In the above solution, the tag control subunit is further configured to acquire read data by using the interconnect unit when the snoop request is unresponsive.

In the above solution, the data exchange sub-unit is further configured to: after receiving the invalid request sent by the second slave interface unit, return an invalid request response to the second slave interface unit; and send corresponding tag storage to the tag control sub-unit Invalid request;

Correspondingly, the tag control subunit is further configured to: after receiving the invalid request of the data exchange subunit, set the corresponding tag memory to an invalid state, and update the tag memory according to the update message in the received writeback request;

The second slave interface unit is further configured to initiate a write operation to the interconnect unit after receiving the response of the data exchange subunit.

In the above solution, the intercept control unit further includes an arbitration subunit configured to: arbitrate the read external memory memory request sent by the mark control subunit and the execution of the read external memory request sent by the data exchange subunit, and The read request after arbitration is sent to the interconnect unit to receive the read data returned by the interconnect unit.

The embodiment of the invention further provides a method for implementing data consistency, the method further comprising:

When determining that the protocol corresponding to the received data consistency request is not supported, performing protocol conversion processing on the received data consistency request;

Determine the corresponding data consistency operation according to the data consistency request after the protocol conversion process The device performs data consistency operations on the data consistency operating device.

In the foregoing solution, the performing a protocol conversion process on the received data consistency request includes:

The received data consistency request supporting the AXI protocol is converted into a data consistency request supporting the ACE_Lite protocol; and the number of bytes of the data-consistent request after the protocol conversion is converted into the full cache data line Full Cache Line byte number.

In the above solution, when the received data consistency request is a read consistency request, the data consistency request device according to the protocol conversion process determines a corresponding data consistency operation device, and performs data on the data consistency operation device. Consistent operations, including:

According to the read data consistency request after the protocol conversion process, the tag memory is searched, the tag memory is found, the main device unit corresponding to the tag memory is found to be monitored to obtain the read data, and the tag memory is not found. The interconnect unit acquires read data.

In the above solution, the method further includes:

When the listener is not responding, the read unit is used to acquire the read data.

In the above solution, when the received data consistency request is a write consistency request, the data consistency request device according to the protocol conversion process determines a corresponding data consistency operation device, and performs data on the data consistency operation device. Consistent operations, including:

Sending an invalidation request to the interception control unit of the device implementing data consistency according to the write data consistency request after the byte number conversion;

The interception control unit returns an invalid request response;

A write operation is initiated to the interconnect unit of the device implementing data consistency based on the invalid request response.

In the above solution, the method further includes:

Blocking the order of transmission transactions; and/or,

Handles WAW and RAW conflicts.

The embodiment of the present invention further provides a computer storage medium, the computer storage medium comprising a set of instructions, when executed, causing at least one processor to execute the implementation number According to the method of consistency.

The device, the method, and the computer storage medium for implementing data consistency provided by the embodiment of the present invention determine a protocol corresponding to the received data consistency request, perform protocol conversion processing on the received data consistency request, and perform conversion processing according to the protocol. The data consistency request determines the corresponding data consistency operation device, performs data consistency operation on the data consistency operation device, and thus can solve the problem that the ACE_Lite protocol is incompatible in most systems through protocol conversion processing, thereby Effectively solve the problem of shared data consistency in the on-chip multiprocessor system.

DRAWINGS

In the drawings, which are not necessarily to scale, the Like reference numerals with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

1 is a schematic structural diagram of an apparatus for implementing data consistency according to Embodiment 1 of the present invention;

2 is a schematic structural diagram of another apparatus for implementing data consistency according to Embodiment 1 of the present invention;

3 is a schematic structural diagram of an apparatus for implementing data consistency according to an embodiment of the present invention;

4 is a schematic structural diagram of a second slave interface unit according to Embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of an interface sequence when a read data consistency request is provided according to

Embodiments

1 and 2 of the present invention;

6 is a schematic diagram of an interface timing when a write data consistency request is converted according to Embodiment 1 of the present invention;

FIG. 7 is a schematic structural diagram of a snoop control unit according to Embodiment 1 of the present invention;

FIG. 8 is a schematic flowchart of a method for implementing data consistency according to Embodiment 2 of the present invention.

detailed description

In order to better understand the content of the embodiments of the present invention, the method for maintaining data consistency commonly used in the prior art is first introduced; the prior art generally includes a method for maintaining software consistency and a method for maintaining consistency of hardware; Although the method of maintaining consistency is easier to implement, the accuracy is not high, and the system performance is degraded during the maintenance process. Although the hardware maintenance consistency method is complicated in design, it can improve system performance; for example, a type released by ARM The architecture of hardware maintenance consistency is implemented based on the bus monitoring and ACE (AXI Coherency Extensions) protocol of Advanced Microcontroller Bus Architecture (AMBA); among them, the ACE protocol is extended in terms of AXI protocol consistency. The ACE_Lite protocol is a subset of the ACE protocol. In general, a processor with its own cache can support the ACE protocol, while a processor or other device that does not have a cache supports the ACE_Lite protocol.

However, since there are currently few processors supporting the ACE protocol, and most of the input and output (IO, Input Output) devices only support the AXI protocol, the ACE_Lite protocol is not supported. Therefore, in most of the on-chip multiprocessor systems, the ACE_Lite protocol is not compatible, resulting in the problem of shared data consistency in the on-chip multiprocessor system.

Based on this, in various embodiments of the present invention, when determining that the protocol corresponding to the received data consistency request is not supported, performing protocol conversion processing on the received data consistency request, and converting the processed data consistency request according to the protocol, Determining a corresponding data consistency operation device, and performing data consistency operation on the data consistency operation device.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and specific embodiments.

Embodiment 1

The embodiment provides a device for implementing data consistency. As shown in FIG. 1 , the device includes: a slave interface unit 11 and a monitoring control unit 12;

The slave interface unit 11 is configured to determine a protocol corresponding to the received data consistency request, perform protocol conversion processing on the received data consistency request, and send the protocol conversion processed data consistency request to the Monitoring control unit 12;

The monitoring control unit 12 is configured to determine a corresponding data consistency operation device according to the data consistency request sent from the interface unit 11, and perform data consistency operation on the data consistency operation device.

Here, the slave interface unit 11 is further configured to directly send the received data consistency request to the intercept control unit 12 when the protocol corresponding to the received data consistency request is determined, so that the intercept control unit 12 is configured according to The data consistency request sent from the interface unit 11 determines a corresponding data consistency operation device, and performs data consistency operation on the data consistency operation device. The data consistency request includes a read data consistency request and a write data consistency request.

In actual application, the protocol conversion processing is performed on the received data consistency request, specifically:

Performing conversion processing of the AXI protocol to the ACE_Lite protocol on the received data consistency request.

The intercept control unit 12 is further configured to, when the received data consistency request is more than two data consistency requests, arbitrate the execution of the received two or more data consistency requests, according to the data after the arbitration. The data request determines a corresponding data consistency operation device, and performs data consistency operation on the data consistency operation device.

Specifically, as shown in FIG. 2, the slave interface unit 11 includes a first slave interface unit 111 and a second slave interface unit 112;

The first slave interface unit 111 is configured to send the received first read data consistency request from the first master unit 21 to the intercept control unit 12;

The second slave interface unit 112 is configured to receive the received from the second master unit 22 The second read data consistency request ReadOnce performs protocol conversion processing, and sends the protocol conversion processed second read data consistency request ReadOnce to the interception control unit 12;

The intercept control unit 12 is configured to arbitrate the execution of the first read data consistency request and the second read data consistency request ReadOnce, according to the first read data consistency request or the second read data after the arbitration When the request ReadOnce determines that the corresponding tag memory tag_ram is not found, the read data operation instruction is sent to the interconnect unit 23 to acquire the read data; when it is determined that the corresponding tag memory tag_ram is found, the tag memory tag_ram is found. The corresponding master device unit initiates monitoring to obtain read data; here, since the intercept control unit 12 can only process one consistency request at the same time, the intercept control unit 12 needs to send the first slave interface unit 111. The first read data consistency request and the execution of the second read data consistency request ReadOnce sent by the second slave interface unit 112 are arbitrated.

If the request after the arbitration control unit 12 is arbitrated is the first read data consistency request, after the first read data consistency request is processed, the second read data consistency request ReadOnce is also performed. Processing; or, if the request after the arbitration control unit 12 arbitrates is the second read data consistency request ReadOnce, after the second read data consistency request ReadOnce is processed, the first read is still required. Data consistency requests are processed.

Here, the interception control unit 12 can arbitrate the execution of the first read data consistency request and the second read data consistency request ReadOnce. For example, the method can be based on polling arbitration. The first read data consistency request and the second read data consistency request ReadOnce are performed for arbitration, and may be arbitrated according to the least recently accessed or pseudo-random arbitration method.

In practical application, as shown in FIG. 3, the interconnection unit 23 may include five main interface units and six slave interface units; wherein the six slave interface units respectively connect the first slave corresponding to the first master unit 21 The interface unit 111, the second slave interface unit 112 corresponding to the second master unit 22, and the interception control unit 12; one main interface unit is used to connect each register, and the other four main interface lists The element is connected as an output to the slave device unit 31; wherein the registers include: an invalid tag memory tag_ram register, an early wresp control register, a timeout threshold register, an interrupt status register, a debug debug control register, and an interrupt mask register;

In practical applications, the apparatus provided in this embodiment is operated under the enable of each register; for example, when the apparatus is initialized, the invalid tag memory tag_ram register provides an invalid enable signal to the intercept control unit 12, so that the The monitoring control unit presets the corresponding tag memory tag_ram to an invalid state according to the invalid enable signal; the early wresp control register provides a control signal to the first slave interface unit 111, so that the first slave interface unit 111 The control signal selects a write response to return an early response or a write response to return a normal response normally; the timeout threshold register provides a count threshold period to the first slave interface unit 111 to pass the first slave interface unit 111 Counting detection to determine whether each stage of data transmission is timed out; when it is determined to be timeout, the first slave interface unit 111 generates a timeout interrupt according to the timeout interrupt signal provided by the interrupt status register; the debug debug control register is configured to be Status letter of the corresponding module in the device that implements data consistency The number is debugged; the interrupt mask register is configured to mask out the interrupt status signal of the corresponding module in the device that implements data consistency.

The specific function of the debug debug control register is not the content of the embodiment of the present invention.

Correspondingly, the first main unit unit 21 may include at least two equipment units cluster, and the cluster may be an ACE master supporting the ACE protocol; for example, it may be ARM Cortex A15 and ARM Cortex A7 of ARM.

The second master unit 22 may include at least one master device, and may be a master device ACE_Lite master supporting the ACE_Lite protocol, or a master device AXI master supporting the AXI protocol; for example, an IO master device and a graphics processor (GPU). Graphic Processing Unit), Direct Memory Access (DMA), and AXI subsystem.

The slave device unit 31 may include at least one slave device, which may be a slave device AXI slave supporting the AXI protocol, and the slave device may also include an external memory memory.

In actual application, the number of the second main unit unit 22 and the slave unit 31 may be expanded or cut according to system requirements.

The second slave interface unit 112 is further configured to: perform protocol conversion processing on the received second write data consistency request WriteUnique from the second master unit 22, and write the second write data consistency request according to the protocol. The invalidation request invalidate is sent to the snoop control unit 12, and after receiving the invalid request response returned by the snoop control unit 12, a write operation is initiated to the interconnect unit 23.

Here, as shown in FIG. 4, the second slave interface unit 112 includes: a protocol conversion subunit 1121, a read operation conversion subunit 1122, a read interface subunit 1123, a write operation conversion subunit 1124, a write interface subunit 1125, and arbitration. Subunit 1126; wherein

The protocol conversion sub-unit 1121 is configured to convert the received data consistency request sent by the second main device unit 22 to support the AXI protocol into a data consistency request supporting the ACE_Lite protocol;

The read operation conversion subunit 1122 is configured to: when the data consistency request sent by the second master device unit is the second read data consistency request, the protocol read converted second read data consistency request Read Once bytes Convert the number to the full cache data line Full Cache Line bytes;

The read interface sub-unit 1123 is configured to distribute a second read data consistency request ReadOnce channel for the second read data consistency request ReadOnce after the byte number conversion, multiplex the read data channel, and convert the byte number The second read data consistency request ReadOnce is sent to the arbitration sub-unit 1126;

The write operation conversion subunit 1124 is configured to: when the data consistency request sent by the second master unit is the second write data consistency request WriteUnique, the second write data consistency request WriteUnique byte after the protocol conversion Convert the number to a full cache data row Full Cache Line number of bytes;

The write interface sub-unit 1125 is configured to distribute a second write data consistency request WriteUnique channel for the second write data consistency request WriteUnique after the byte number conversion, buffer the write data response channel, and convert according to the number of bytes The second write data consistency request WriteUnique sends an invalid request invalidate to the arbitration sub-unit 1126;

The arbitration sub-unit 1126 is configured to, when receiving the data consistency request sent by the read interface sub-unit 1123 and the write interface sub-unit 1125, consistent with the second read data after the byte number conversion The ReadOnce request and the execution of the second write data consistency request WriteUnique after the byte number conversion are arbitrated, and the ReadOnce or the second write data consistency request WriteUnique is requested according to the second read data consistency after arbitration. The intercept control unit 12 sends a corresponding data consistency request; specifically, when the arbitrated data consistency request is the second read data consistency request ReadOnce, the second read data consistency request ReadOnce is sent after the byte number conversion The intercept control unit 12 is configured to send an invalidation request invalidate to the intercept control unit 12 when the arbitrated data consistency request is the second write data consistency request WriteUnique. The second read data consistency request ReadOnce after the byte number conversion refers to a request to read the shared data and the read shared data is not cached.

Here, when the arbitration subunit 1126 simultaneously receives the data consistency request sent by the read interface subunit 1123 and the write interface subunit 1125, if the arbitration subunit 1126 arbitrates the request is the second read After the data consistency request ReadOnce, after the second read data consistency request ReadOnce is sent to the intercept control unit 12, the invalid write request invalidate is sent to the intercept control unit 12 according to the second write data consistency request WriteUnique. ;or,

When the arbitrated request by the arbitration sub-unit 1126 is the second write data consistency request WriteUnique, after the second write data consistency request WriteUnique sends the invalid request invalidate to the intercept control unit 12, the Second read data consistency request ReadOnce is sent to the snoop control unit 12.

Specifically, when the second master unit 22 includes an AXI master, the protocol conversion subunit 1121 is specifically configured to: generate different ACE_Lite transmission types according to different AXI addresses in the AXI master, and support the AXI protocol. The second read or write data consistency request is converted into a second read or write data consistency request supporting the ACE_Lite protocol, so that the second read or write data consistency request sent by the AXI master can be effectively sent, in other words, to enable AXI The second read or write data consistency request sent by the master obtains a corresponding response of the intercept control unit 12; wherein the transport type includes: a listen request AWSNOOP of the write address channel, a listen request ARSNOOP of the read address channel; the AXI The mapping between addresses and ACE_Lite transport types can be pre-configured.

When the second data consistency request sent by the second master unit 22 is the second read data consistency request ReadOnce, the read operation conversion subunit 1121 is specifically configured to: use the content addressed memory (CAM, Content) The addressable memory, the splitting algorithm, and the control logic convert the number of bytes of the second read data consistency request ReadOnce of the protocol conversion into a full cache data line Full Cache Line byte number; specifically, the read operation conversion subunit 1122, the received second protocol read data consistency request ReadOnce is byte-combined, and the extra bytes are filtered to meet the requirement of the original command data volume burst; here, because the intercept control unit 12 requires reading data. The number of bytes of the consistency request is the same as the number of bytes of the full cache data row of the cache data row, and the number of bytes of the second read data consistency request ReadOnce after the protocol conversion has no similar limitation, so Perform a conversion of the number of bytes;

The number of bytes of the Full Cache Line of the full cache data line is usually 32 bytes or 64 bytes; the original command data volume burst includes: a data bit width, a data type, and a data length, and the data bit width is generally 32 bits, 64 bits or 128 bit; the data type includes: fixed type, increased type incr and wrap-around wrap; the data length includes at least one piece of data, and the number of storage units of the CAM can be configured according to system requirements.

For example, suppose the full cache data line requires a full Cache Line byte number of 32 bytes and a data bit width of 128 bits. The corresponding original command data volume burst has a data bit width of 128 bits, and the data type is wraparound type and the wrap length is 2 ( Wrap2); The interface timing of the second read data consistency request Read Once conversion is as shown in FIG. 5.

As can be seen from FIG. 5, the byte-converted second read data consistency request ReadOnce has a lower address of 12'h18, a data bit width of 64 bits, and a data type of incr4 is split into a lower address of 12'h10. The data bit width is 128 bit, the wrap2 and the lower address are 12'h20, the data bit width is 128 bit, and the wrap2 is the two original command data volume burst; wherein, when the first original command data volume burst data is not needed, the second data is not needed. When the skip second data is skipped, the first data of the second original command data volume burst is held for two periods, corresponding to the data of the addresses s side of 12'h20 and 12'h28 respectively; The s side pulls rlast_s high when receiving the fourth data;

Here, the byte-converted second read data consistency request ReadOnce low-order address is 12'h18, data bit width is 64bit, wrap4 burst is split into two low-order addresses are 12'h10, data bit width The 128-bit, wrap2 original command data volume burst. The second data of the first original command data volume burst is held for two periods, corresponding to the data of the 12'h00 and 12'h08 addresses on the s side, and the rlast_s is pulled when the s side receives the fourth data. High, wherein when the second data of the second original command data volume burst is not needed, the skip second data is skipped; the s side refers to the interface signal of the slave device, and the m side refers to The interface signal of the second master unit 22, the information on the s side corresponds to the information on the m side of the output after the read operation conversion subunit 1122 converts.

The information on the s side includes: araddr_s, arvalid_s, arready_s, rdata_s, rlast_s, rvalid_s, and rready_s; the araddr_s refers to an address of the s-side read address channel; and the arvalid_s refers to a request of the s-side read address channel; The arready_s refers to the s-side read address channel request response; the rdata_s refers to the read data of the s-side read data channel; the rlast_s refers to the last s-side The indication signal of the read data; the rvalid_s refers to the request of the s side read data channel; the rready_s refers to the request response of the s side read data channel;

The information on the m side includes: araddr_m, arvalid_m, arready_m, rdata_m, rlast_m, rvalid_m, and rready_m; the araddr_m is an address of an m-side read address channel; and the arvalid_m is a request of an m-side read address channel; Arready_m refers to the request response of the m-side read address channel; the rdata_m refers to the read data of the m-side read data channel; the rlast_m refers to the indication signal of the last read data of the m side; the rvalid_m refers to the m-side read The request of the data channel; the roughy_m refers to the request response of the m-side read data channel; the beat_complete refers to the end of the current data; the last_match refers to the last data; the above araddr_s, arvalid_s, arready_s, rvalid_s, rlast_s Rdata_s, rready_s, araddr_m, arvalid_m, arready_m, rvalid_m, rlast_m, rdata_m, and rready_m respectively correspond to standard signals in the AXI protocol.

After the read operation conversion subunit 1122 converts the second read data consistency request ReadOnce byte number converted by the protocol conversion subunit 1121, the read interface subunit 1123 is specifically configured to: use the buffer buffer cache. The read operation conversion subunit 1122 converts the second read data consistency request ReadOnce, and distributes the read data for the read operation conversion subunit 1122 byte number converted second read data consistency request ReadOnce a consistency request channel, the multiplexed read data channel; wherein the multiplexed read data channel is: when the snoop control unit 12 and the interconnect unit 23 simultaneously return read data, return to the snoop control unit 12 first Reading data.

In order to avoid deadlock, the read interface sub-unit 1123 is further configured to block transmission inter-transaction ordering; the blocking transmission inter-transaction ordering includes: after all the consistent transmission data requests are completed, the current non-consistent transmission data request Can be issued; or, after all non-consistent transmission data requests are completed, the current request to transmit data consistently can be issued.

When the second data consistency request sent by the second master unit 22 is the second write data one When the write request is made to the WriteUnique, the write operation conversion subunit 1124 is specifically configured to: convert the byte number of the second write data consistency request WriteUnique after the protocol conversion into the full cache data by using the CAM, the split algorithm, and the control logic. The number of bytes of the Full Cache Line is set; here, because the snoop control unit 12 designed in the embodiment of the present invention requires the number of bytes of the write data consistency request WriteUnique to be the same as the number of bytes of the full cache data line Full Cache Line, and the protocol conversion After the second write data consistency request WriteUnique has no similar limit on the number of bytes, so the number of bytes needs to be converted, and the second write data consistency request WriteUnique after the protocol conversion is split, after splitting. The total number of bytes of each raw command data volume burst is less than or equal to the full cache data line Full Cache Line bytes, and the received write responses are merged to meet the requirements of the original command data volume burst;

Specifically, similar to the conversion of the second read data consistency request ReadOnce, for example, if the full cache data line Full Cache Line number of bytes is required to be 32 bytes, and the data bit width is 128 bits, the corresponding data width of the burst is also 128bit, the data type is wraparound, and the wrap length is 2 (wrap2); then the interface timing of the write data consistency request WriteUnique conversion is shown in Figure 6.

It can be known from FIG. 6 that the original command data volume burst of the second write data consistency request WriteUnique of the byte conversion is 12'h18, the data bit width is 64 bit, and the data type is incr4 can be separately divided into The lower address is 12'h18, the data bit width is 64bit, the incr1 and the lower address are 12'h20, the data bit width is 64bit, the intr3 is the original data volume burst; and the two write channel data responses returned by the m side are Bresp merges into a write channel data response bresp and sends it from the s side;

Here, the byte-converted second write data consistency request WriteUnique has a lower address of 12'h10 and a data bit width of 128 bits, and the original command data amount burst of the wrap4 is split into a lower address of 12'h10. The data bit width is 128bit, the burst of incr1, the lower address is 12'h20, the data bit width is 128bit, the burst and lower address of incr2 are 12'h00, the data bit width is 128bit, the burst of incr1; and the m side is returned Three write channel data response bresp And a write channel data response bresp is sent from the s side; wherein the m side is the interface of the main device unit; the awaddr_s refers to the address of the s side write address channel; the awvalid_s refers to the s side write address channel The awready_s refers to the request response of the s side write address channel; the wdata_s refers to the write data of the s side write data channel; the wlast_s refers to the indication signal of the last write data of the s side; the bvalid_s Refers to the s side write response channel request; the wholesale_s refers to the s side write response channel request response; the awaddr_m refers to the m side write address channel address; the awvalid_m refers to the m side write address channel request; The awready_m refers to a request response of the m side write address channel; the wdata_m refers to write data of the m side write data channel; the wlast_m refers to the last write data indication signal of the m side; the bvalid_m refers to the m side Write a response channel request; the wholesale_m refers to the request response of the m side write response channel; the above awaddr_s, awvalid_s, awready_s, wdata_s, wlast_s, bvalid_s, bready_s, awaddr_m, awvalid_m, awready_m, wdata_m, w Last_m, bvalid_m, and bready_m correspond to standard signals in the AXI protocol, respectively.

After the write operation conversion sub-unit 1124 completes the byte conversion of the second write data consistency request WriteUnique, the write interface sub-unit 1125 is specifically configured to: first use the buffer buffer to buffer the byte-converted second Write a data consistency request WriteUnique, and distribute a write data consistency request channel for the second write data consistency request WriteUnique; and then adjust the number of bytes of the invalid request invalidate to be consistent with the second write data after the byte conversion Requesting the WriteUnique byte number is equal, sending the invalid request invalidate to the intercept control unit 12, receiving the invalid request response inv_done returned by the snoop control unit 12, initiating a write operation to the interconnect unit 23, buffering the write data response channel;

Here, since the invalid request response inv_done returned by the snoop control unit 12 may be out of order, in order to ensure the second write data consistency request and the second master unit 22 after the byte conversion of the write operation conversion subunit 1124 The second write data consistency request sent is consistent with the WriteUnique order, and the write interface subunit 1125 identifies the invalid inv_id of the invalid request invalidate In addition to the write address channel identifier awid of the second master unit 22, a buffer number is added to the second write data consistency request WriteUnique after the byte number conversion, and is saved in the buffer; if the returned inv_id The second write data consistency request WriteUnique converted by the byte conversion of the write operation conversion subunit 1124 is sent to the interconnection unit 23 in accordance with the saved buffer number.

In order to avoid deadlock, the write interface sub-unit 1125 is further configured to block the transfer order sequential ordering, the write-before-write WAW, and the post-write RAW conflict;

The ordering ordering of the blocking transmission transaction includes: after all the consistent transmission data requests are completed, the current non-consistent transmission data request can be sent; or, after all the unconsistent transmission data requests are completed, the current consistency transmission data is The request can be issued.

For the WAW conflict, the write interface sub-unit 1125 sends the byte-converted second write data consistency request WriteUnique address to the first slave interface unit 11, if it is between the first write data consistency request If there is a conflict, the write interface sub-unit 1125 blocks the byte-converted second write data consistency request WriteUnique until the first write data consistency request after the byte conversion of the first slave interface unit 111 completes the operation; The WAW conflict refers to that after the first master device unit 21 performs a write operation on the address region, the second master device unit 22 performs a write operation on the address region; or the second master device unit 22 performs a write operation on the address region. Thereafter, the first master device unit 21 performs a write operation on the address region.

For RAW conflict, the write interface sub-unit 1125 uses the CAM to save the write address channel identifier awid and the write address channel address of the unprocessed second write data consistency request, and the snoop control unit 12 will read the data consistency request miss The address is sent to the write interface sub-unit 1125. The write interface sub-unit 1125 determines whether the miss address of the read data consistency request is the same as the pending address. If they are the same, the conflict control signal hazard is returned to the intercept control unit 12 to ensure the word. The second write data consistency request WriteUnique after the node conversion completes the operation, and the listen control list is only after the second write data consistency request WriteUnique completes the operation after the byte number conversion The element 12 initiates a read data consistency operation to the interconnect unit 23; wherein the miss address refers to an address without a hit result; the write address channel identifier awid is used to look up the write response channel identifier bid and read from the CAM The RAW means that after the first master unit 21 performs a write operation on the address area by the first slave interface unit 111, the second master unit 22 reads the address area through the second slave interface unit 112. Or after the first master device unit 21 performs a write operation on the address region, the second master device unit 22 performs a read operation on the address region.

When the second master unit 22 simultaneously sends the second read data consistency request ReadOnce and the second write data consistency request WriteUnique, the arbitration subunit 1126 is specifically configured to convert the byte The second read data consistency request ReadOnce and the byte-converted second write data consistency request WriteUnique are arbitrated; here, because the consistency request interface between the second slave interface unit 112 and the snoop control unit 12 has only one Therefore, the arbitration sub-unit 1126 needs to arbitrate the second read data consistency request ReadOnce and the second write data consistency request WriteUnique, and then send the second read data consistency request ReadOnce or the second write data to the intercept control unit 12. Consistency request WriteUnique.

In addition, when the slave interface unit 11 determines the protocol corresponding to the data consistency request received, the protocol conversion processing of the received data consistency request is not required, and the received data consistency request is directly sent to the listener. Control unit 12.

Specifically, in the case that there is a consistent data transmission requirement, the first slave interface unit 11 is specifically configured to: according to a first in first out (FIFO) cache transfer type, a data address conflict, and a transfer transaction. In the sequential ordering situation, the first read data consistency request of the first master unit 21 is sent to the snoop control unit 12, or the first write data consistency request of the first master unit 21 is sent to the interconnect unit 23 Directly initiating a write operation to the interconnect unit 23;

Here, the first slave interface unit 111 supports a write response provided by the early wresp register to select a write response to return an early response or a write response to return normally. The way of response. Returning the early response mode to the write response, returning the write response after completing the write operation according to the write data consistency request; if the actual write response has an error error, the first slave interface unit 111 records the address and the ID of the error transmission. The normal write response is returned to the first master unit 21 for the write response to return to the normal response mode.

Here, when the first master unit 21 performs other consistency maintenance operations other than reading and writing, the first slave interface unit 111 is further configured to: update the rewritten dirty data to the memory and keep the copy. The only CleanUnique request or the CleanInvalid request for the CleanShared request or the invalid copy shared by the duplicate is sent to the snoop control unit 12 to clean the copy; and only the copy of the unique MakeUnique request or only the invalid copy is retained. The MakeInvalid request is sent to the snoop control unit 12 to perform a make operation on the replica. The first slave interface unit 111 further has a data transmission timeout detection function. During the data transmission process, it is determined by counting detection whether each phase of the data transmission is timed out; specifically, the first master device unit 21 moves to the slave through the handshake mechanism. The device unit 31 sends a valid signal, and when the first slave interface unit 111 determines that the read signal returned by the slave device unit 31 is not received within the timeout threshold period, the data transmission is considered to be timed out, and a timeout interrupt is generated; the timeout threshold period may be Pre-configured according to actual conditions.

In addition, in the case of the non-conforming data transmission requirement, the first slave interface unit 111 sends the first read sent by the first master unit 21 according to the FIFO buffer transmission type, the data address conflict, and the order of the order between the transmission transactions. Or a write data consistency request is sent to the interconnect unit 23; the second slave interface unit 112 sends the second read or write data consistency request of the second master unit 22 directly to the interconnect unit 23 for access A corresponding slave unit 31; wherein the slave unit 31 includes at least one.

When the first slave interface unit 21 and the second slave interface unit 112 simultaneously send the first read data consistency request, the second read or write data consistency request to the intercept control unit 12, the intercept control unit 12 specifically Configured as: according to the first read data consistency request or the number of bytes converted The second read data consistency request ReadOnce determines that the tag memory tag_ram is found, sends a snoop request to the hit target first main device unit 21, and acquires access data; if the first main device unit 21 does not respond to the snoop request, the snoop control unit 12 Then, the read data operation is sent to the interconnect unit 23 to obtain the read data; if it is determined that the tag memory tag_ram is not found, the read data operation is sent to the interconnect unit 23; or

In response to the invalid request invalidate sent by the second slave interface unit 112, the second slave interface unit 112 initiates a write operation to the interconnect unit 23.

Specifically, as shown in FIG. 7, the interception control unit 12 includes: a flag control subunit snoop_tag_ctl 121, a data exchange subunit snoop_ddi 122, and an arbitration subunit snoop_arb123;

The tag control sub-unit 121 is configured to receive a first read or write data consistency request sent by the first slave interface unit 111, a second read or write consistency request sent by the second slave interface unit 112, and a data exchange. The invalid request invalidate sent by unit 121, and arbitrate the execution of these requests;

When the queried request is the first read data consistency request or the second read data consistency request ReadOnce, the mark control sub-unit 121 is specifically configured to: according to the first read data consistency request or the second read data consistent The request ReadOnce finds the tag memory tag_ram. If the tag memory tag_ram is found, the hit result is generated according to the full cache data line in the tag memory tag_ram; wherein, if the full cache data line in the hit result is Full Cache Line is valid Status, the interception request is sent to the data exchange sub-unit 122 to obtain the read data; if the full cache data line in the hit result is Full Cache Line is invalid or the complete cache data line Full Cache Line does not exist in the hit result, the mark The control sub-unit 121 then uses the interconnection unit 23 to send a read memory request to the external memory memory; the operation type is ReadClean, the ReadClean refers to reading the shared data and the read shared data is not cached, the tag memory tag_ram Recorded full cached data accessed Whether the Full Cache Line exists in the cache of the first main device unit 21; the second slave interface unit 112 can also determine whether the access data can be acquired by listening to the first slave interface unit 111; if the second master device unit 22 The data to be accessed is in the cache of the first main unit unit 21, and the access data can be directly obtained from the cache of the first main unit unit 21 without accessing the slave unit 31, so that the access time can be reduced. Improve access efficiency.

If the data consistency requests issued by the first slave interface unit 111 and the second slave interface unit 112 have the same identification ID, the flag control sub-unit 121 is further configured to ensure the order consistency of processing the requests.

In addition, if the first main equipment unit 21 performs other consistency maintenance operations except reading and writing, the marking control sub-unit 121 is specifically configured to: according to the duplicate unique CleanUnique request or the duplicate, the CleanShared request or the complex The invalid CleanInvalid request finds the tag memory tag_ram, and if the tag memory tag_ram is found, the hit result is generated according to the full cache data line in the tag memory tag_ram; wherein, if the full cache data line in the hit result is Full Cache Line In the active state, a snoop request is sent to the data exchange sub-unit 122 to obtain read data and data status. Wherein, for the ditry data that needs to be written back, the snoop control unit 12 sends a write operation to the interconnect unit 23.

When the tag control sub-unit 121 sends a snoop request to the data exchange sub-unit 122, the data exchange sub-unit 122 is configured to: send the snoop request to the first main device unit 21 according to the hit information, and receive The listener response cresponse and the monitor data cdata returned by the first master unit 21, and send the monitor data cdata to the first slave interface unit 111 or the second slave interface unit 112, to the first slave interface unit 111 or the second slave interface The unit 112 sends a data consistency request operation completion indication; when the monitoring request is not responding, the label control sub-unit 121 is further configured to use the interconnection unit 23 to send a read external memory memory request to the external memory memory; the hit information includes : Hit result and operation type.

When the write operation conversion subunit 1124 sends an invalid request invalidate, the data The switching subunit 122 is further configured to, after returning the invalid request response inv_done to the write operation conversion subunit 1124, send an invalid request corresponding to the tag memory tag_ram to the tag control subunit 121, so that the tag control subunit 121 sets the corresponding tag memory tag_ram Invalid state, while updating the tag memory tag_ram according to the update message written back to the WriteBack request; wherein the write back WriteBack request refers to the request sent by the first slave interface unit 111 to the snoop control unit 12 to write data back to the memory. Here, since the tag memory tag_ram may change from the inactive state to the active state during the operation of the device, the tag control unit 121 is also required to reset the required tag memory tag_ram to the inactive state.

In addition, when the dirty data needs to be written to the external memory memory, the mark control sub-unit 121 is further configured to use the interconnect unit 23 to send a write operation to the external memory memory to write the dirty data into the external memory memory.

When the tag control sub-unit 121 and the data exchange sub-unit 122 simultaneously send a read memory request, the arbitration sub-unit 123 is specifically configured to: read the external memory memory request sent by the tag control sub-unit 121 and the data exchange. The execution of the read external memory memory request sent by the subunit 122 is arbitrated, and the arbitrated read memory request is sent to the interconnect unit 23 to receive the read data returned by the interconnect unit 23;

When the arbitration sub-unit 123 receives the read data sent by the data exchange sub-unit 122 and the read data returned by the interconnection unit 23, the arbitration sub-unit 123 is further configured as the intercept data sent to the data exchange sub-unit 122. After the read data returned by the interconnection unit 23 is arbitrated, the read data is transmitted to the first slave interface unit 111 or the second slave interface unit 112.

Here, since the snoop control unit 12 is configured to maintain data consistency between the two clusters in the first main unit unit 21, to record the method of recording the full cache data line Full Cache Line state in the prior art, The Full Cache Line state of each full cache data line needs to consume a very large resource, and the method is complicated and difficult to implement; therefore, in this embodiment, the snoop control unit 12 uses a segment address counting method to record each cluster. Medium The existence status of the Full Cache Line of the full cache data line is not only easy to implement, but also can accurately record the state of the Full Cache Line of the full cache data line.

The method includes two basic characteristics: (1) if the record in the snoop control unit 12 indicates that a full cache data line Full Cache Line exists in a certain cluster, but in reality, due to the inaccuracy of the interception algorithm, the method The full cache data line Full Cache Line is likely to be in an invalid state in the cluster; (2) If the record in the snoop control unit 12 indicates that there is no full cache data line Full Cache Line in the cluster, then the cluster certainly does not The full cache data line Full Cache Line is included, that is, the full cache data line Full Cache Line is definitely in an invalid state in the cluster; therefore, the state of the full cache data line FullCache Line can be accurately recorded.

In practical applications, the slave interface unit 11 can provide a physical interface and an ASIC (Application Specific Intercrated Circuit) or a programmable logic array (FPGA) in the device for implementing data consistency. Implementation, the snoop control unit 12 can be implemented by an ASIC or FPGA in a device that implements data consistency.

This embodiment is based on the AMBA4ACE protocol, combined with the function of interconnect unit and data consistency, solves the problem of shared storage data consistency in multi-processor systems from hardware, reduces software intervention and external memory access times, and improves the system. Access efficiency reduces power consumption from memory access.

Moreover, the device of the embodiment of the invention has a monitoring filtering function, which reduces unnecessary monitoring operations and further improves system performance.

Embodiment 2

Corresponding to the first embodiment, the embodiment of the present invention further provides a method for implementing data consistency. As shown in FIG. 8, the method mainly includes the following steps:

Step 801: When it is determined that the protocol corresponding to the received data consistency request is not supported, perform protocol conversion processing on the received data consistency request.

Here, when it is determined that the protocol corresponding to the received data consistency request is supported, the received data consistency request is not subjected to protocol conversion processing.

In this step, when determining that the protocol corresponding to the received data consistency request is not supported, performing protocol conversion processing on the received data consistency request, including:

Converting the received data conformance request supporting AXI protocol into a data consistency request supporting the ACE_Lite protocol;

The method also includes:

Converting the number of bytes of ReadOnce of the read data consistency request after the protocol conversion into the full cache data line Full Cache Line bytes;

Reading data consistency request ReadOnce for the byte number conversion to read the read data consistency request ReadOnce channel, multiplexing the read data channel;

Converting the number of bytes of the write data consistency request WriteUnique after the protocol conversion into the full cache data line Full Cache Line bytes;

WriteUnique distribution write data consistency request WriteUnique channel for byte data conversion write data consistency request, cache write data response channel;

Arbitrating the read data consistency request ReadOnce of the byte number conversion and the execution of the write data consistency request WriteUnique after the byte number conversion; wherein the read data consistency request ReadOnce after the protocol conversion is A request to read shared data and read out shared data that is not cached.

Specifically, in the case of a consistent data transmission requirement, when the master device corresponding to the data consistency request includes the AXI master, different ACE_Lite transmission types are generated according to different AXI addresses in the AXI master, and the AXI protocol is supported. The read or write data consistency request is converted to a read or write data consistency request that supports the ACE_Lite protocol so that the read or write data consistency request sent by the AXI master can be effectively sent, in other words, to enable the AXI master to send a read or The write data consistency request is correspondingly responded; wherein the transmission type includes: a write address The listener of the channel requests AWSNOOP, the listen request ARSNOOP of the read address channel; the mapping relationship between the AXI address and the ACE_Lite transport type can be pre-configured.

Here, when the transmitted data consistency request is a read data consistency request ReadOnce, the CAM, the split algorithm, and the control logic convert the byte number of the read data consistency request ReadOnce of the protocol conversion into a full cache data line Full Cache Line number; specifically, the read data consistency request ReadOnce of the received protocol conversion is byte-merged, and the extra bytes are filtered to meet the requirement of the original command data volume burst; here, because the interception control The number of bytes required by the unit to read the data consistency request is the same as the number of bytes of the full cache data line of the cache data row, and the number of bytes of the read data consistency request ReadOnce after the protocol conversion has no similar limit, so Need to convert the number of bytes;

For example, suppose the full cache data line requires a full Cache Line byte number of 32 bytes and a data bit width of 128 bits. The corresponding original command data volume burst has a data bit width of 128 bits, and the data type is wraparound type and the wrap length is 2 ( Wrap2); then read the data consistency request interface timing when ReadOnce conversion is shown in Figure 5.

It can be known from FIG. 5 that the lower address of the read data consistency request after the byte number conversion is 12'h18, the data bit width is 64 bit, and the burst of the data type incr4 is split into the lower address of 12'h10, and the data is The bit width is 128bit, the wrap2 and the lower address are 12'h20, the data bit width is 128bit, and the wrap2 is the original two command data volume burst; wherein, the first original command data volume burst data does not need to be returned. When the data is skipped, the second data of skip is skipped, and the first data of the second original command data volume burst is kept for two periods, corresponding to the addresses in the s side. 12'h20 and 12'h28 data; and, the s side pulls rlast_s high when receiving the fourth data;

Here, the read data consistency request in the byte number conversion can be read as the lower address of 12'h18, the data bit width is 64 bit, and the original command data volume of wrap4 is burst into two low-order addresses, which are 12'. H10, the data bit width is 128bit, and the wrap2 burst. The second data of the first original command data volume burst is held for two periods, corresponding to the data of the 12'h00 and 12'h08 addresses on the s side, and the rlast_s is pulled when the s side receives the fourth data. High, wherein when the second data of the second original command data volume burst is not needed, the second data of skip is skipped; wherein the s side refers to an interface signal of the slave device, the m side Refers to the interface signal of the master device unit, and the information on the s side is the information on the m side that is output after being converted from the interface unit;

The s-side information includes: araddr_s, arvalid_s, arready_s, rdata_s, rlast_s, rvalid_s, and rready_s; the araddr_s refers to an address of the s-side read address channel; and the arvalid_s refers to a request of the s-side read address channel; Arready_s refers to the s-side read address channel request response; the rdata_s refers to the read data of the s-side read data channel; the rlast_s refers to the indication signal of the last read data on the s side; and the rvalid_s refers to the s-side read data. The request of the channel; the ready_s refers to the request response of the s-side read data channel;

The information on the m side includes: araddr_m, arvalid_m, arready_m, rdata_m, rlast_m, rvalid_m, and rready_m; the araddr_m is an address of an m-side read address channel; and the arvalid_m is a request of an m-side read address channel; Arready_m refers to the request response of the m-side read address channel; the rdata_m refers to the read data of the m-side read data channel; the rlast_m refers to the last read data consistency request signal of the m side, and the rvalid_m refers to the m side The request for reading the data channel; the ready_m refers to the request response of the m-side read data channel; the beat_complete refers to the end of the current data; the last_match refers to the last data; the above araddr_s, arvalid_s, arready_s, rvalid_s, Rlast_s, rdata_s, rready_s, araddr_m, arvalid_m, arready_m, rvalid_m, rlast_m, rdata_m, and rready_m respectively correspond to standard signals in the AXI protocol.

After the read data consistency request ReadOnce byte number conversion is completed, the read data consistency request ReadOnce is converted by the buffer buffer byte number conversion, and the ReadOnce is distributed for the read data consistency request after the byte number conversion. a consistency request channel, the multiplexed read data channel; wherein the multiplexed read data channel is: when the monitoring control unit of the device implementing data consistency and the interconnecting unit of the device implementing the data consistency simultaneously return the read data At the same time, the read data of the interception control unit is returned first.

In order to avoid deadlock, it is also necessary to block the sequential ordering of the transmission transactions; the ordering of the blocking transmission transactions includes: after all the consistent transmission data requests are completed, the current non-consistent transmission data request can be issued; or, all the non-uniform After the sexual transmission data request is completed, the current request for consistent data transmission can be issued.

In addition, when the data consistency request sent is a write data consistency request WriteUnique, the number of bytes of the write data consistency request WriteUnique converted by the protocol is converted into a full cache data line Full Cache by using CAM, split algorithm and control logic. Line number of bytes;

Here, the interception control unit designed by the embodiment of the present invention requires that the number of bytes of the write data consistency request WriteUnique be the same as the number of bytes of the full cache data line Full Cache Line, and the write data consistency request after the protocol conversion The number of bytes in WriteUnique has no similar restrictions, so the number of bytes needs to be converted, and the write data consistency request WriteUnique after the protocol conversion is split. After the split, the original command data volume is the total word of the burst. The number of sections is less than or equal to the full cache data line Full Cache Line bytes, and the received write response is merged to meet the requirements of the original command data volume burst;

Specifically, it is similar to the read data consistency request ReadOnce. For example, if the full cache data line requires a full Cache Line byte number of 32 bytes and a data bit width of 128 bits, the corresponding burst data bit width is also 128 bits. The data type is rewind type, and the wrap length is 2 (wrap2); then the interface timing of the write data consistency request WriteUnique conversion is as shown in FIG. 6.

It can be known from FIG. 6 that the byte-converted write data consistency request can be obtained. The lower address of WriteUnique is 12'h18, the data bit width is 64bit, and the original command data volume burst of data type incr4 is split into low-order address of 12'h18, data bit width of 64bit, incr1 and low-order address of 12'h20. The data bit width is 64 bit, incr3 two original command data volume burst; and the two bresp returned from the m side are merged into one bresp and then sent from the s side;

Here, the byte address conversion write data consistency request WriteUnique low address is 12'h10, data bit width is 128bit, wrap4 original command data volume burst is split into low address 12'h10, data The bit width is 128bit, the burst of incr1, the lower address is 12'h20, the data bit width is 128bit, the burst and lower address of incr2 are 12'h00, the data bit width is 128bit, the burst of incr1; and the m side returns three The write channel data response bresp is merged into a write channel data response bresp and sent from the s side; wherein the m side is the interface of the main device unit; the awaddr_s is the address of the s side write address channel; the awvalid_s is Refers to the s side write address channel request; the awready_s refers to the s side write address channel request response; the wdata_s is the s side refers to the write data channel write data; the wlast_s refers to the s side last write data The indication signal; the bvalid_s refers to the request of the s side write response channel; the wholesale_s refers to the request response of the write response channel; the awaddr_m refers to the address of the m side write address channel; the awvalid_m refers to the m side write address The request of the channel; the awready_m refers to the request response of the m side write address channel; the wdata_m refers to the write data of the m side write data channel; the wlast_m refers to the last write data indication signal of the m side; the bvalid_m Refers to the m side write response channel request; the wholesale_m refers to the m side write response channel request response; the above corresponding awaddr_s, awvalid_s, awready_s, wdata_s, wlast_s, bvalid_s, bready_s, awaddr_m, awvalid_m, awready_m, wdata_m, wlast_m, Bvalid_m and bready_m correspond to the standard signals in the AXI protocol.

After the byte conversion of the write data consistency request WriteUnique is completed, firstly, the write data consistency request WriteUnique is converted by the buffer buffer byte number conversion, and the WriteUnique distribution is requested for the byte data conversion write data consistency request. Write data consistency request And then adjusting the number of bytes of the invalid request invalidate to be equal to the number of WriteUnique bytes of the write data consistency request after the byte conversion, sending an invalid request invalidate to the intercept control unit, and receiving the returned invalid request response inv_done, A write operation is initiated to the interconnect unit to buffer the write data response channel.

Here, since the invalid request response inv_done returned by the snoop control unit may be out of order, in order to ensure the consistency of the write data consistency request WriteUnique and the sent write data consistency request WriteUnique order after the byte number conversion, the invalid request invalidate In addition to the write address channel identifier awid of the second master unit, the identifier inv_id also adds a buffer number in the write data consistency request WriteUnique after the byte number conversion, and saves it in the buffer; if the returned identifier The inv_id is the same as the saved buffer number, and the corresponding write data consistency request WriteUnique is sent to the interconnect unit.

Step 702: Determine, according to the data consistency request processed by the protocol conversion, the corresponding data consistency operation device, and perform data consistency operation on the data consistency operation device.

In this step, when the read data consistency request ReadOnce and the write data consistency request WriteUnique are simultaneously received, the read data consistency request ReadOnce and the byte number converted write data are consistent with the byte number conversion. The execution of the write request WriteUnique is arbitrated, and the ReadOnce or Write Data Consistency Request WriteUnique is sent to the intercept control unit according to the read data consistency request after the arbitration; here, because the data consistency is achieved There is only one consistency request interface between the second slave interface unit and the snoop control unit of the device, so the second slave interface unit needs to arbitrate the execution of the read data consistency request ReadOnce and the write data consistency request WriteUnique. Sending a read data consistency request ReadOnce to the snoop control unit, or sending an invalid request invalidate to the snoop control unit according to the write data consistency request WriteUnique.

Here, if the request after the arbitration is a read data consistency request ReadOnce, after the read data consistency request ReadOnce is sent to the interception control unit, it is also required to be consistent according to the write data. The sexual request WriteUnique sends an invalidation request to the interception control unit; or,

If the request after the arbitration is a write data consistency request WriteUnique, after the write data consistency request WriteUnique sends the invalid request invalidate to the intercept control unit, the read data consistency request ReadOnce is also sent to the intercept control. unit.

There are various implementation methods for arbitrating the read data consistency request after the byte number conversion and the execution of the write data consistency request after the byte number conversion, for example, according to the polling arbitration. The method arbitrates the execution of the read data consistency request ReadOnce and the write data consistency request WriteUnique, and may also perform arbitration according to the least recently accessed or pseudo-random arbitration mode.

Here, the determining, according to the data consistency request after the protocol conversion processing, the corresponding data consistency operation device, performing data consistency operation on the data consistency operation device, including:

According to the data consistency request after the protocol conversion processing, searching for the tag memory, determining to find the tag memory, initiating the monitoring to the main device unit corresponding to the tag memory to obtain the read data; determining that the tag memory is not found, The unit gets the read data.

Specifically, when the read data consistency request ReadOnce after the protocol conversion process is received, the read data consistency request ReadOnce is determined according to the protocol conversion, and when the tag memory tag_ram is found, the first corresponding to the tag memory tag_ram is found. The master device unit sends a listening request to obtain the access data; if the first master device unit does not respond to the monitoring request, sends a read data operation instruction to the interconnect unit to acquire the read data; if it is determined that the tag memory tag_ram is not found, The interconnect unit sends a read data operation instruction to acquire read data; or,

When the received data consistency request is a write consistency request WriteUnique, the data consistency request device according to the protocol conversion process determines a corresponding data consistency operation device, and performs data consistency operation on the data consistency operation device. ,include:

When receiving the write data consistency request WriteUnique after the protocol conversion process, responding to the invalid request sent by the second slave interface unit of the write data consistency request WriteUnique Invalidate to cause the second slave interface unit to initiate a write operation to the interconnect;

Here, the read data consistency request ReadOnce looks up the tag memory tag_ram according to the protocol conversion, and if the tag memory tag_ram is found, sends a snoop request to the sending first master device unit, which specifically includes:

ReadOce looks up the tag memory tag_ram according to the read data consistency after the protocol conversion, and if the tag memory tag_ram is found, generates a hit result according to the full cache data line in the tag memory tag_ram; wherein, if the hit result is The full cache data line Full Cache Line is valid, then send a listen request to the first master unit to obtain read data; if the full cache data line in the hit result is Full Cache Line is invalid or the hit result does not exist intact Cache the data line Full Cache Line, then use the interconnection unit to send a read external memory memory request to the external memory memory; the operation type is ReadClean, the ReadClean refers to reading the shared data and the read shared data is not cached, The tag memory tag_ram records whether the accessed full cache data line FullCache Line exists in the cache of the first master unit; the second slave interface unit can also listen to the first corresponding to the first master unit Determine from the interface unit whether the number of accesses can be obtained. According to the data; if the data that the second master unit needs to access is in the cache of the first master unit, the access data can be directly obtained from the cache of the first master unit without accessing the slave unit, so that Can reduce access time and improve access efficiency.

When the intercept control unit receives the invalid request invalidate, the invalid request response inv_done is returned, and the second slave interface unit sends a write operation indication to the interconnect unit according to the invalid request response inv_done, and the intercept control unit responds according to the invalid request of the corresponding tag memory tag_ram. The tag memory tag_ram is set to an invalid state, and the tag_ram is updated according to the update message written back to the WriteBack request; wherein the write back WriteBack request refers to writing the data back to the external slave interface unit to the intercept control unit Memory memory request.

In addition, when it is determined that the protocol corresponding to the received data consistency request is supported, then no The received data consistency request is subjected to protocol conversion processing, and the received data consistency request is directly sent to the interception control unit.

Specifically, in the case of a consistent data transmission requirement, a read data consistency request that does not require protocol conversion is sent to the interception control unit according to the first-in first-out FIFO buffer transfer type, the data address conflict, and the order of the transfer transaction ordering. Sending a write data consistency request without performing protocol conversion processing to the interconnect unit, directly initiating a read operation indication to the interconnect unit, and when the intercept control unit receives the returned read data, transmitting the read data to the first slave interface unit. The processing flow of the read data consistency request for the interception control unit to the protocol conversion is the same as the processing flow of the read data consistency request after the protocol conversion.

Here, when the intercept control unit simultaneously receives the read data consistency request without protocol conversion and the read data consistency request ReadOnce after the protocol conversion, the read data consistency request and the protocol are not required for protocol conversion. The read data consistency request of the converted read data is arbitrated by the execution of the ReadOnce, and if the request after the arbitration control unit arbitrates is the read data consistency request that does not need to perform protocol conversion, the read data that does not need to be converted by the protocol is After the consistency request is processed, the read data consistency request ReadOnce is also processed; or if the interception control unit arbitrates the request is the protocol converted read data consistency request ReadOnce Then, after the ReadOnce processing of the protocol-converted read data consistency request is completed, a read data consistency request that does not need to perform protocol conversion needs to be processed.

Here, if the data consistency request sent by the first slave interface unit without protocol conversion and the data consistency request sent by the second slave interface unit requiring protocol conversion have the same ID, the intercept control unit needs to ensure Handle the order consistency of these requests.

Here, the first interface slave unit supports a manner of selecting a write response to return an early response or a write response to return a normal response by a control signal provided by an early wresp register. Returning the early response method to the write response in advance, when there is no need to perform protocol transfer After the write data consistency request completes the write operation, the write response is returned; if the actual write response has an error error, the first interface slave unit records the address and ID of the error transmission; for the write response, the normal response mode is returned. The actual write response is returned to the first master unit.

The first interface slave unit further has a data transmission timeout detection function, and during the data transmission process, it is determined by counting detection whether each phase of the data transmission times out. Specifically, the first master device unit sends a valid signal to the slave device unit by using a handshake mechanism, and when the first slave interface unit determines that the read signal returned by the slave device unit is not received within the timeout threshold period, the data transmission is considered to be timed out. A timeout interrupt is generated; the timeout threshold period can be pre-configured according to actual conditions.

In addition, if the first master unit performs other consistency maintenance operations other than reading and writing, the intercept control unit searches for the tag memory tag_ram according to the duplicate unique CleanUnique request or the duplicate CommonShared request or the duplicate invalid CleanInvalid request. If the tag memory tag_ram is found, a hit result is generated according to the full cache data line Full Cache Line information in the tag memory tag_ram; wherein, if the full cache data line Full Cache Line in the hit result is in a valid state, then the first master device is The unit sends a listening request, and receives the listening response cresponse and the listening data cdata returned by the first main device unit. When the dirty data needs to be written into the external memory memory, the monitoring control unit uses the interconnect unit to send a write operation to the external memory memory to Write dirty data to the external memory memory.

Here, since the snoop control unit is configured to maintain data consistency between the two clusters in the first main unit, but to record the full cache line status in the prior art, to record each complete Cache data line Full Cache Line status, which will consume a very large resource, and the method is complicated and difficult to implement; therefore, in this embodiment, the interception control unit uses a segment address counting method to record complete in each cluster. Cache data line The existence status of Full Cache Line is not only easy to implement, but also can accurately record the status of the full cache data line Full Cache Line.

The method includes two basic characteristics: (1) if the record in the intercept control unit indicates that a full cache data line Full Cache Line exists in a certain cluster, but in fact, due to the inaccuracy of the interception algorithm, the complete cache is caused. The data line Full Cache Line is likely to be in an invalid state in the cluster; (2) if the record in the intercept control unit indicates that there is no full cache data line Full Cache Line in the cluster, the cluster definitely does not contain the complete Cache data line Full Cache Line, that is, the full cache data line Full Cache Line is definitely in an invalid state in this cluster; therefore, the state of the full cache data line Full Cache Line can be accurately recorded.

In this step, in order to avoid deadlock, it is also necessary to block the order order between the transfer transactions, handle the conflict between the write-before-write WAW and the read-after-write RAW;

For the WAW conflict, the write data consistency request WriteUnique address of the byte number conversion is sent to the first slave interface unit, and if there is a conflict with the other write data consistency request, the other write data consistency is blocked. The request until the byte number conversion of the write data consistency request completes the operation; the WAW conflict refers to the first master device unit performing a write operation on the address area, and the second master device unit performs a read operation on the address area; Or after the second master unit writes the address area, the first master unit performs a read operation on the address area.

For RAW conflicts, use CAM to save the write address channel identifier awid and write address channel address of the unprocessed data consistency request, read the miss address of the data consistency request, and determine whether the miss address and the pending address of the read data consistency request are the same. If they are the same, the conflict signal hazard is returned to ensure that the write data consistency request after the byte number conversion request WriteUnique completes the operation, and only after the byte data conversion write data consistency request WriteUnique completes the operation, Initiating a read data operation to the interconnect unit; wherein the write address channel identifier awid is used to find the write response channel identifier bid and read data from the CAM; the RAW means that the first master device unit writes the address region After the operation, the second master device unit performs a read operation on the address region; or after the first master device unit performs a write operation on the address region, the second master device unit performs a read operation on the address region.

In addition, in this step, when it is determined that the protocol corresponding to the received data consistency request is supported, the protocol conversion processing of the received data consistency request is not required, and the received data consistency request is sent to the interception control unit. The monitoring control unit determines, according to the data consistency request, a corresponding data consistency operation device, and performs data consistency operation on the data consistency operation device.

In the case of non-conforming data transmission requirements, the data consistency request is directly sent to the interconnect unit according to the FIFO buffer transmission type, the data address conflict, and the order of the transmission transaction, to access the corresponding slave unit. .

The solution provided by the embodiment of the invention solves the problem of shared storage data consistency in the multi-processor system from hardware, reduces software intervention and external memory access times, improves system access efficiency, and reduces work brought by memory access. Consumption.

Moreover, the device corresponding to the solution of the embodiment of the present invention has a monitoring filtering function, which reduces unnecessary monitoring operations and further improves system performance.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It should be understood that the flow can be implemented by computer program instructions Each of the processes and/or blocks in the figures and/or block diagrams, and combinations of the flows and/or blocks in the flowcharts and/or block diagrams. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in Within the scope of protection of the present invention.

Claims

An apparatus for implementing data consistency, the apparatus comprising: a slave interface unit and a monitoring control unit; wherein

The slave interface unit, configured to determine a protocol corresponding to the received data consistency request, performs protocol conversion processing on the received data consistency request, and sends the data conversion request processed by the protocol conversion to the monitoring control unit;

The monitoring control unit is configured to determine, according to the data consistency request sent by the slave interface unit, a corresponding data consistency operation device, and perform data consistency operation on the data consistency operation device.
The apparatus according to claim 1, wherein the interception control unit is further configured to, when the received data consistency request is more than two data consistency requests, request the two or more data consistency requests received Performing arbitration, determining a corresponding data consistency operation device according to the data consistency request after the arbitration, and performing data consistency operation on the data consistency operation device.
The apparatus of claim 1, wherein the slave interface unit is further configured to, when configured to determine a protocol corresponding to the received data consistency request, to send the received data consistency request to the snoop control unit.
The device according to claim 3, wherein the slave interface unit comprises: a first slave interface unit and a second slave interface unit; wherein

The first slave interface unit is configured to send the received first read data consistency request from the first master unit to the intercept control unit;

The second slave interface unit is configured to perform a protocol conversion process on the received data consistency request from the second master device unit, and send the protocol conversion processed data consistency request to the interception control unit.
The apparatus of claim 4, wherein the second slave interface unit is configured to: Converting the AXI protocol-compliant data consistency request sent by the received second master unit into a data consistency request supporting the ACE_Lite protocol; and converting the number of bytes of the protocol-converted data consistency request into a full cache data line Full Cache Line Bytes.
The apparatus according to claim 5, wherein said second slave interface unit comprises: a protocol conversion subunit, a read operation conversion subunit, a read interface subunit, a write operation conversion subunit, and a write interface subunit; wherein

The protocol conversion subunit is configured to convert a data consistency request sent by the received second master unit to support the AXI protocol into a data consistency request supporting the ACE_Lite protocol;

The read operation conversion subunit is configured to convert, when the data consistency request sent by the second master device unit is the second read data consistency request, the number of bytes of the second read data consistency request after the protocol conversion is converted into Full Cache Line bytes;

The read interface sub-unit is configured to distribute a second read data consistency request channel for the second read data consistency request after the byte number conversion, and multiplex the read data channel;

The write operation conversion subunit is configured to convert, when the data consistency request sent by the second master device unit is the second write data consistency request, the number of bytes of the second write data consistency request after the protocol conversion is converted into Full Cache Line bytes;

The write interface sub-unit is configured to distribute a second write data consistency request channel for the second write data consistency request after the byte number conversion, and cache the write data response channel.
The apparatus of claim 6, wherein the second slave interface unit further comprises: an arbitration subunit configured to simultaneously receive a data consistency request sent by the read interface subunit and the write interface subunit And arbitrating the execution of the second read data consistency request after the byte number conversion and the second write data consistency request after the byte number conversion, and according to the second read data consistency after the arbitration The request or second write data consistency request sends a corresponding data consistency request to the snoop control unit.
The apparatus of claim 6 wherein said read interface subunit is further configured to block The plug transfers the order between transactions.
The apparatus of claim 6 wherein the write interface sub-unit is further configured to block the transfer inter-transaction sequence, handle the write-behind write WAW, and the post-write write RAW conflict.
The apparatus of claim 4, wherein the first slave interface unit is further configured to send a first write data consistency request from the first master unit to the interconnect unit to initiate writing directly to the interconnect unit operating.
The apparatus according to claim 4, wherein said snoop control unit comprises a mark control subunit and a data exchange subunit; wherein

The tag control subunit is configured to receive a first read and/or first write data consistency request sent by the first slave interface unit, a second read and/or a second write consistency request sent by the second slave interface unit And the invalidation request invalidate sent by the data exchange subunit, and arbitrate the execution of the requests; when the arbitrated request is the first read data consistency request or the second read data consistency request, according to the first read data consistency The request or the second read data consistency request looks up the tag memory, and if the tag memory is found, generates a hit result according to the Full Cache Line information in the tag memory; if the Full Cache Line in the hit result is a valid state, the data is The exchange subunit sends a listen request to obtain the read data; if the Full Cache Line in the hit result is in an invalid state or the Full Cache Line does not exist in the hit result, the read unit is used to acquire the read data;

The data exchange sub-unit is configured to send the interception request to the first main device unit according to the hit information, receive the intercept response and the intercept data returned by the first main unit, and send the intercept data to the first slave interface unit. Or after the second slave interface unit, send a data consistency request operation completion indication to the first slave interface unit or the second slave interface unit.
The apparatus of claim 11, wherein the flag control subunit is further configured to utilize the interconnect unit to acquire read data when the snoop request is unresponsive.
The apparatus according to claim 12, wherein said data exchange subunit is further provided After receiving the invalid request sent by the second slave interface unit, returning an invalid request response to the second slave interface unit; and sending an invalid request corresponding to the tag storage to the tag control subunit;

Correspondingly, the tag control subunit is further configured to: after receiving the invalid request of the data exchange subunit, set the corresponding tag memory to an invalid state, and update the tag memory according to the update message in the received writeback request;

The second slave interface unit is further configured to initiate a write operation to the interconnect unit after receiving the response of the data exchange subunit.
The apparatus of claim 11, wherein the snoop control unit further comprises an arbitration subunit configured to: read a read external memory request sent by the tag control subunit and a read external memory request sent by the data exchange subunit The execution is arbitrated, and the arbitrated read request is sent to the interconnect unit to receive the read data returned by the interconnect unit.
A method for achieving data consistency, the method further comprising:

When determining that the protocol corresponding to the received data consistency request is not supported, performing protocol conversion processing on the received data consistency request;

And determining, according to the data consistency request processed by the protocol conversion, the corresponding data consistency operation device, and performing data consistency operation on the data consistency operation device.
The method of claim 15, wherein the performing a protocol conversion process on the received data consistency request comprises:

The received data consistency request supporting the AXI protocol is converted into a data consistency request supporting the ACE_Lite protocol; and the number of bytes of the data conversion request after the protocol conversion is converted into the Full Cache Line byte number.
The method according to claim 16, wherein when the received data consistency request is a read consistency request, the data consistency request is determined according to the protocol conversion process, and the corresponding data consistency operation device is determined. The data consistency operation device performs data consistency operations, including:

According to the read data consistency request after the protocol conversion process, the tag memory is searched, the tag memory is found, the main device unit corresponding to the tag memory is found to be monitored to obtain the read data, and the tag memory is not found. The interconnect unit acquires read data.
The method of claim 17, wherein the method further comprises:

When the listener is not responding, the read unit is used to acquire the read data.
The method according to claim 16, wherein when the received data consistency request is a write consistency request, the data consistency request is determined according to the protocol conversion process, and the corresponding data consistency operation device is determined. The data consistency operation device performs data consistency operations, including:

Sending an invalidation request to the interception control unit of the device implementing data consistency according to the write data consistency request after the byte number conversion;

The interception control unit returns an invalid request response;

A write operation is initiated to the interconnect unit of the device implementing data consistency based on the invalid request response.
The method of claim 15 wherein the method further comprises:

Blocking the order of transmission transactions; and/or,

Handles WAW and RAW conflicts.
A computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the method of implementing data consistency as claimed in any one of claims 15 to 20.