WO2014113062A2 - Io virtualization system and method using offload processors - Google Patents

Abstract

An input-output (IO) virtualization system connectable to a network is disclosed. The system can include a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.

Description

10 VISUALIZATION SYSTEM AND METHOD USING OFFLOAD PROCESSORS

TECHN ICAL FIELD

Described embodiments relate to input/output (10) virtualization services that are provided by a memory bus connected module that can allow a single 10 device to appear as multiple 10 devices.

BACKGROUND

Virtualization is commonly seen as a process of combining hardware and software resources into a single administrative entity to simply the use of computing resources. Virtualization can be supported within a computer or server, across local clusters of computers, or as part of a larger network. Ideally, virtualized systems simplify sharing of computer resources such as storage or processing time. For example, server virtualization can allow an administrator can convert one physical server into multiple virtual machines. Each virtual server acts like a unique physical device, capable of running its own operating system (OS).

However, support of virtualization can require significant new investments in powerful processors, high bandwidth input/output fabrics, and memory upgrades to support increased utilization and computational requirements of virtualized systems. Unless additional server class processors and high bandwidth interconnects are provided in a virtualized system, a user can experience a significant reduction in access time and throughput, diminishing the value of virtualization.

SUMMARY

This disclosure describes embodiments of systems, hardware and methods suitable for high speed, energy efficient virtualization support that can involve minimal or low utilization access to computing resources of a host processor of a server, server rack system, or blade server. In certain embodiments, a first virtual switch is connected to the network and configured to direct network packets based on network identifier tags. A second virtual switch is connected to a memory bus, and an offload processor module is used to support the second virtual switch. The offload processor module includes at least one offload processor capable of modifying network packets and directing the modified network packets to the first virtual switch through the memory bus.

In other embodiments, the offload processor module includes separately addressable offload processors, and network packets can be directed to a specific memory address space. The first virtual switch can have direct memory access to the second virtual switch to act as a direct memory access (DMA) master, with the second virtual switch acting as a DMA slave. In other embodiments the master/slave relationship of the virtual switches can be reversed. The second virtual switch can also have a scheduler and an arbiter to prioritize handling of network data. In the described embodiments, the memory bus supports a data transfer protocol (such as DDR3, as but one very particular example).

In certain embodiments an input-output (10) virtualization system can include a physical 10 device and multiple virtual 10 devices. A provisioning agent is used to allocate exclusive address spaces in a main memory to each of the multiple virtual 10 devices and the physical 10 device, with each of the physical or virtual 10 devices capable of direct memory reads and writes to the respective exclusive address spaces. The address spaces can be physical or virtual, and the provisioning agent can create a mapping between virtual addresses and physical addresses. In selected embodiments, the provisioning agent creates virtual function (VF) drivers that can optionally be accessible through direct memory address (DMA) and supplied with packet descriptors to control data processing. Mapping between virtual addresses and physical addresses can be retained (e.g., stored in tables of an input output memory management unit, IOMMU). A host or server processor can be used to run the provisioning agent. In one embodiment, the second virtual switch can be supported by a memory bus attached module having multiple offload processors. The memory bus can support a data transfer protocol (such as DDR3, as but one very particular example). Further, the module can be mounted to a memory socket (such as a dual in line memory module (DIMM) socket, as but one particular example).

This disclosure also describes methods for virtualization support by improved data processing. Received data can be examined at a first virtual switch to identify a first target memory address location for the data. The data is transported to a second virtual switch using a memory bus having a defined memory transport protocol, and the data is then written to a second target memory location. The data written to the second target memory location is processed with an offload processor module. The offload processor module can include one or more offload processors, and in certain embodiments, multiple low power offload processors having a suitable architecture (such as an ARM type architecture, as but one particular example).

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 -0 shows a system according to an embodiment.

FIG. 1 -1 shows an input output memory management unit (IOMMU) that can be included in embodiments. FIG. 1-2 shows a process for providing translation with an IOMMU that can be included in embodiments. FIGS. 1 -3 and 1-4 shows a process for assigning packets for processing to various virtual machines, according to an embodiment.

FIGS. 2-0 to 2-3 show processor modules according to various embodiments. FIG. 2-4 shows a conventional dual-in-line memory module. FIG. 2-5 shows a system according to another embodiment.

FIGS. 3 shows one particular implementation of a memory bus connected offload processor capable of supporting packet conversion services for network overlay that can be included in embodiments.

FIG. 4 shows a process for locking an input output translation lookaside buffer (IOTLB) that can be included in embodiments.

FIG. 5 shows an example of a virtual switch that can be included in embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show systems, devices and methods for providing input/output (IO) virtualization services with minimal impact on a host processor device. The operation of one or more virtual switches can be supported by offload processor modules that can operate independent of any host processor devices. According to some embodiments, offload processor modules can be connected to a system memory bus and receive data via direct memory access transfers. In very particular embodiments, processing modules can populate physical slots for connecting in-line memory modules (e.g., DIMMs) to a system memory bus.

FIG. 1 -0 is a diagram of a system 100 for providing input/output (IO) virtualization services according to one embodiment. A system 100 can include a first virtual switch 106a, a second virtual switch 106b, and offload processors 120. Also shown are a host processor 130, a central processing unit (CPU) input/output (I/O) fabric 1 14, an input output memory management unit (IOMMU) 110, and a memory controller 1 16. In the particular embodiment shown, IOMMU 1 10 can be part of an I/O bridge 107.

In operation, a first virtual switch 106a can receive data packets 104 from, and transmit data packets to a data source 102. A data source 102 can include the Internet, a network cloud, inter- or intra- data center networks, cluster computers, rack systems, multiple or individual servers, personal computers, or any suitable data packet source or destination. Data packets can be packet or switch based, although in some embodiments non-packet data is generally converted or encapsulated into packets for ease of handling. In some embodiments, data packets have certain characteristics, including transport protocol number, source and destination port numbers, or source and destination IP addresses. The data packets can further have associated metadata which can help in packet classification and management.

First virtual switch 106a can include, but is not limited to, devices compatible with a host bus 108. A virtual switch 106a can include a network interface controller (N IC), a host bus adapter, a converged network adapter, or a switched or ATM network interface, as but a few examples. Such controller, interfaces and adapters can include, but are not limited to, peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with host motherboard via PCI or PCIe bus (e.g., 108).

A first virtual switch 106a can employ IO virtualization schemes to make a single network I/O device appear as multiple devices. In particular embodiments this can include a single root I/O virtualization (SR-IOV). SR-IOV permits separate access to resources among various PCIe hardware functions by providing both physical control and virtual functions. In certain embodiments, the first virtual switch 106a can support OpenFlow or similar software defined networking to abstract out of the control plane. In particular embodiments, the control plane of the first virtual switch 106a can performs functions such as route determination, target node identification etc. The forwarding plane of the first virtual switch can transport packets from a physical layer of one kind (Ethernet/IP) to a peripheral IO bus (e.g., 108).

Using IOMMU 110, I/O fabric 1 14 can interfaces with one or more memory controllers 116 to transfer the network packets to a second virtual switch 106b. The second virtual switch 106b, which is interfaced with a memory bus 118, can receive and switch traffic originating from the memory bus 1 18 to offload processors 120 and vice versa. Thus, the forwarding plane of the second virtual switch 106b can transport packets from a memory bus 118 to offload processors 120 or from the offload processors 120 back onto the memory bus 118. For certain applications, the described system architecture can allow for relatively direct communication of network packets to the offload processors 120 with minimal or no interruptions to a host processor 130.

Embodiments described herein can include busses of any suitable type suitable, preferably ones providing high speed low latency interconnection between system parts.

Bus architectures can include but are not limited to PCI, PCIe, Fibre Channel, and the like. A bus architecture can also be based on relevant JEDEC standards or include a HyperTransport (HT) architecture. Offload processors 120 can communicate over a memory bus according to any suitable memory bus standard, including but not limited to any of the double data rate (DDR) standards (i.e., DDR, DDR2, DDR3). In some embodiments, offload processors 120 can include energy efficient, general purpose processor such as those based on ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC architectures. In addition to processors, offload processors 120 can include, or operate in conjunction with, memory devices. Such memory devices can include but not limited to DDR dynamic random access memory (RAM), reduced latency DRAM (RLDRAM), or next generation stacked memory devices, such as Hybrid Memory Cube (HMC), flash, or other suitable memory. Offload processors 120 can also include embedded memory (e.g., embedded DRAM), separate logic or bus management chips, programmable units such as field programmable gate arrays (FPGAs), custom designed application specific integrated circuits (ASICs).

In some embodiments, a host processor 130 can be a general purpose processor, including those based on Intel or AMD x86 architecture, Intel Itanium architecture, MIPS architecture, SPARC architecture or the like.

Referring still to FIG. 1-0, an operating system, or the user code running on the host processor 130, may be loaded with a device model 135, one or more virtual function (VF) drivers 132 and controlling function (CF) drivers 133 using a provisioning agent 130a. The provisioning agent 130a can be an entity on the host processor 130 that can initializes and interact with virtual VF drivers 132. The VF driver 132 can be responsible for providing a VF with the virtual address of the memory space where direct memory addressing (DMA) is needed. Each VF driver can be allocated with virtual addresses that can map to physical addresses. A device model 135 can be used to create an emulation of a physical device for the host processor 130 to recognize each of the multiple VFs that are created. The device model 135 can be replicated multiple times to give the impression to VF drivers (a driver that interacts with a virtual IO device) that they are interacting with a physical device. For example, a device model to emulate a network adapter can be the Intel® Ethernet Converged Network Adapter (CNA) X540-T2. The VF driver 132 can act to connect with such an adapter. The device model 135 and the VF driver 133 can be run in either privileged or non- privileged mode. There can be no restriction with regard to which device hosts/runs the code corresponding to the device model and the VF driver. The code, however, can have the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.

An operating system of a host processor 130 can also create a defined physical address space for an application 130a supporting the VF drivers 132. Further, the host processor 130 operating system can allocate a virtual memory address space to the application or provisioning agent 130a. The provisioning agent 130a can broker with the host operating system to create a mapping between said virtual address and a subset of the available physical address space. This physical address space corresponds to the address space of the offload processors 120. The provisioning agent 130a can be responsible for creating each VF driver 132 and allocating to it a defined virtual address space. The application or provisioning agent 130a can control the operation of each of the VF drivers. The provisioning agent 130a can supply each VF driver 132 with descriptors such as an address of a next packet.

An application or provisioning agent 130a, as part of an application/user level code, can create a virtual address space for each VF 132 during runtime. Allocating an address space to a device can be supported by allocating to the virtual address space a portion of the available physical memory space. This allocates part of the physical address space to the VF. For example, if the application 130a handling the VF driver 132 instructs it to read or write packets from or to virtual memory addresses Oxaaaa to Oxffff, the VF driver may write I/O descriptors into a descriptor queue of a VF with a head and tail pointer that are changed dynamically as queue entries are filled. The data structure may be of another type as well, including but not limited to a ring structure or hash table.

A mapping between virtual memory address space and physical memory space can be stored in tables of an IOMMU 1 10. An application may supply VF drivers 132 with virtual addresses at which memory read or write is to be performed. The VF drivers 132 supply the virtual addresses to a VF. The VFs are configured to generate requests such as read and write which may be part of a direct memory access (DMA) read or write operation. A VF can read from or write data to the address location pointed to by the VF driver. The virtual addresses are translated by the IOMMU 110 to corresponding physical addresses and the physical addresses may be provided to the memory controller for access. That is, the IOMMU 1 10 can modify the memory requests sourced by the I/O devices to change the virtual address in the request to a physical address. The memory request can then be forwarded to the memory controller 116 for memory access. Further, on completing the transfer of data to the address space allocated to the VF driver 132, the VF driver can mask or disable those interrupts, which are usually forwarded to the host processor 130 to handle such data (e.g., network packets). The memory request may be forwarded to memory controller 1 16 over a high speed low latency interconnection 112 (e.g., HyperTransport, HT) 1 12. The VF in such cases can carry out a direct memory access by supplying the virtual memory address to the IOMMU 1 10.

Alternatively, an application may directly code the physical address into the VF descriptors if the VF allows for it. If the VF cannot support physical addresses of the form used by the host processor 130, an aperture with a hardware size supported by the VF device may be coded into the descriptor so that the VF is informed of the target hardware address of the device. Data that is transferred to an aperture may be mapped by a translation table to a defined physical address space in the system memory. DMA operations may be initiated by software executed by the processors, programming the I/O devices directly or indirectly to perform the DMA operations.

FIG. 1 -1 shows an IOMMU 110' that can be included in embodiments. An IOMMU 110' can be configured to translate a virtual address (DEVICE VISIBLE VIRTUAL ADDRESS) corresponding to an I/O device to its corresponding physical address in the main memory (PHYSICAL ADDRESS). The IOMMU 1 10' may include page table walker 1 10a, a translation lookaside buffer (IOTLB) 1 10b, control registers 1 10c, and control logic 110d.

FIG. 1 -2 is a flow diagram showing an IOMMU method 150 to serve I/O requests that can be included in the embodiments. A method 150 can include receiving an I/O request (for address translation) (151 ). If the address translation is already available in the IOTLB 110b (Yes from 152), the information can be sent to a memory controller (152) (thus serving the request). Otherwise (No from 152), a page table walker can be invoked (153), and a translated address can be obtained and provided to the memory controller. An IOTLB of the IOMMU can be updated with this latest translation information (154) and an event log can be created or updated (155).

FIGS 1 -3 and 1 -4 together illustrate a process flow 160 according to an embodiment. Referring to FIG. 1 -3, a process 160 can include receiving packets from a network (162). Packets can be segregated based on sessions (164). Such an action can include classifying packets based on session metadata with a virtualized network interface. In the embodiment shown, this can include operation of a first virtual switch (e.g., 106a of FIG. 1 -0). Sessions can be prioritized and queued for arbitration (166). Using session metadata, a determination can be made if sessions are to be written to offload processors (168). Such an action can use both packet metadata and session metadata. If session(s) are not to be written to offload processors (No from 168), session(s) can be queued for a host processor(s) (170). If sessions are for offload processors (Yes from 168), based on a classification, packet(s) can be assigned to one of multiple VFs (172). VFs can be supplied with virtual memory addresses by a VF driver. The VFs can use the virtual memory addresses to generate a DMA request. The request can be forwarded to an IOMMU (174). Such actions can use other details in a descriptor structure to generate the DMA request. Referring to FIG. 1-4, a process 160 can further include the IOMMU performing an address translation to identify a physical address corresponding to a supplied virtual address (176). The IOMMU can forward the DMA request to a memory controller (178). The DMA request can be targeted to the physical address generated at 176. Therefore, the packets destined to be processed by the offload processors can be written to the memory location corresponding to the offload processors by performing a DMA operation. Data (e.g., packets) written to a memory location by memory controller can be received by a second virtual switch (180). The second virtual switch can carry out traffic management to reintroduce prioritization based on metadata (182). Such actions can include classification and prioritization to create flow characteristics for packets of a session using available session metadata. Arbitration between different sessions can occur, and different sessions can be scheduled into different offload processors (184). Such action can result in traffic managed flows being written to multiple offload processors at, with execution of data processing operations determined by suitable arbiters and schedulers. In particular embodiments, such action can include offload processors operating on the packet data, where the offload processors are mounted to a memory bus subject to the DMA transfer. In one very particular embodiment, such offload processor modules can be fitted into a memory bus socket, such as a DIMM slot.

It is understood that many of the foregoing processing tasks can be implemented on multiple threads running on multiple processing cores. Such parallelization of tasks into multiple thread contexts can provide for increased throughput. Processors architectures such as MIPS may include deep instruction pipelines to improve the number of instructions per cycle. Further, the ability to run a multi-threaded programming environment results in enhanced usage of existing processor resources. To further increase parallel execution on the hardware, processor architecture may include multiple processor cores. Multi-core architectures comprising the same type of cores, referred to as homogeneous core architectures, provide higher instruction throughput by parallelizing threads or processes across multiple cores. However, in such homogeneous core architectures, the shared resources, such as memory, are amortized over a small number of processors. In still other embodiments, multiple offload or host processors can reside on modules connected to individual rack units or blades that in turn reside on racks or individual servers. These can be further grouped into clusters and datacenters, which can be spatially located in the same building, in the same city, or even in different countries. Any grouping level can be connected to each other, and/or connected to public or private cloud internets.

Memory and I/O accesses can incur a high amount of processor overhead. Further, context switches in conventional general purpose processing units can be computationally intensive. It is therefore desirable to reduce context switch overhead in a networked computing resource handling a plurality of networked applications in order to increase processor throughput. Conventional server loads can require complex transport, high memory bandwidth, extreme amounts of data bandwidth (randomly accessed, parallelized, and highly available), but often with light touch processing: HTML, video, packet-level services, security, and analytics. Further, idle processors still consume more than 50% of their peak power consumption.

In contrast, according to embodiments herein, complex transport, data bandwidth intensive, frequent random access oriented, 'light' touch processing loads can be handled behind a socket abstraction created on multiple offload processor cores. At the same time, "heavy" touch, computing intensive loads can be handled by a socket abstraction on a host processor core (e.g., x86 processor cores). Such software sockets can allow for a natural partitioning of these loads between light touch (e.g., ARM) and heavy touch (e.g., x86) processor cores. By usage of new application level sockets, according to embodiments, server loads can be broken up across the offload processing cores and the host processing cores.

FIGS. 2-0 to 2-5 describe aspects of hardware embodiments and methods useful for providing 10 virilization services using an offload processor module to support offload processing as described herein, or equivalents. In particular embodiments, such processing modules can include DIMM mountable modules.

FIG. 2-0 is a block diagram of a processing module 200 according to one embodiment. A processing module 200 can include a physical connector 202, a memory interface 204, arbiter logic 206, offload processor(s) 208, local memory 210, and control logic 212. A connector 202 can provide a physical connection to system memory bus. This is in contrast to a host processor which can access a system memory bus via a memory controller, or the like. In very particular embodiments, a connector 202 can be compatible with a dual in-line memory module (DIMM) slot of a computing system. Accordingly, a system including multiple DIMM slots can be populated with one or more processing modules 200, or a mix of processing modules and DIMM modules.

A memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200. Such data transfers can include the receipt of packet data having a particular network identifier. In some embodiments, a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module 200. In very particular embodiments, a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory bus initiated by a DMA master. In some embodiments, a DMA master can be a device different from a host processor. In such configurations, processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.

Arbiter logic 206 can arbitrate between conflicting accesses of data within processing module 200. In some embodiments, arbiter logic 206 can arbitrate between accesses by offload processor 208 and accesses external to the processor module 200. It is understood that a processing module 200 can include multiple locations that are operated on at the same time. It is understood that accesses arbitrated by arbiter logic 206 can include accesses to physical system memory space occupied by the processor module 200, as well as accesses to other resources (e.g., cache memory of offload or host processor ). Accordingly, arbitration rules for arbiter logic 206 can vary according to application. In some embodiments, such arbitration rules are fixed for a given processor module 200. In such cases, different applications can be accommodated by switching out different processing modules. However, in alternate embodiments, such arbitration rules can be configurable.

Offload processor 208 can include one or more processors that can operate on data transferred over the system memory bus. In some embodiments, offload processors can run a general operating system or server applications such as Apache (as but one very particular example), enabling processor contexts to be saved and retrieved. Computing tasks executed by offload processor 208 can be handled by the hardware scheduler. Offload processors 208 can operate on data buffered in the processor module 200. In addition or alternatively, offload processors 208 can access data stored elsewhere in a system memory space. In some embodiments, offload processors 208 can include a cache memory configured to store context information. An offload processor 208 can include multiple cores or one core.

A processor module 200 can be included in a system having a host processor (not shown). In some embodiments, offload processors 208 can be a different type of processor as compared to the host processor. In particular embodiments, offload processors 208 can consume less power and/or have less computing power than a host processor. In very particular embodiments, offload processors 208 can be "wimpy" core processors, while a host processor can be a "brawny" core processor. However, in alternate embodiments, offload processors 208 can have equivalent computing power to any host processor. In very particular embodiments, a host processor can be an x86 type processor, while an offload processor 208 can include an ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC type processor, as but a few examples.

Local memory 210 can be connected to offload processor 208 to enable the storing of context information.

Accordingly, an offload processor 208 can store current context information, and then switch to a new computing task, then subsequently retrieve the context information to resume the prior task. In very particular embodiments, local memory 210 can be a low latency memory with respect to other memories in a system. In some embodiments, storing of context information can include copying an offload processor 208 cache.

In some embodiments, a same space within local memory 210 is accessible by multiple offload processors

208 of the same type. In this way, a context stored by one offload processor can be resumed by a different offload processor.

Control logic 212 can control processing tasks executed by offload processor(s). In some embodiments, control logic 212 can be considered a hardware scheduler that can be conceptualized as including a data evaluator 214, scheduler 216 and a switch controller 218. A data evaluator 214 can extract "metadata" from write data transferred over a system memory bus. "Metadata", as used herein, can be any information embedded at one or more predetermined locations of a block of write data that indicates processing to be performed on all or a portion of the block of write data and/or indicate a particular task/process to which the data belongs (e.g., classification data). In some embodiments, metadata can be data that indicates a higher level organization for the block of write data. As but one very particular embodiment, metadata can be header information of one or more network packets (which may or may not be encapsulated within a higher layer packet structure).

A scheduler 216 (e.g., a hardware scheduler) can order computing tasks for offload processor(s) 208. In some embodiments, scheduler 216 can generate a schedule that is continually updated as write data for processing is received. In very particular embodiments, a scheduler 216 can generate such a schedule based on the ability to switch contexts of offload processor(s) 208. In this way, on-module computing priorities can be adjusted on the fly. In very particular embodiments, a scheduler 216 can assign a portion of physical address space (e.g., memory locations within local memory 210) to an offload processor 208, according to computing tasks. The offload processor 208 can then switch between such different spaces, saving context information prior to each switch, and subsequently restoring context information when returning to the memory space.

Switch controller 218 can control computing operations of offload processor(s) 208. In particular embodiments, according to scheduler 216, switch controller 218 can order offload processor(s) 208 to switch contexts. It is understood that a context switch operation can be an "atomic" operation, executed in response to a single command from switch controller 218. In addition or alternatively, a switch controller 218 can issue an instruction set that stores current context information, recalls context information, etc.

In some embodiments, processor module 200 can include a buffer memory (not shown). A buffer memory can store received write data on board the processor module. A buffer memory can be implemented on an entirely different set of memory devices, or can be a memory embedded with logic and/or the offload processor. In the latter case, arbiter logic 206 can arbitrate access to the buffer memory. In some embodiments, a buffer memory can correspond to a portion of a system physical memory space. The remaining portion of the system memory space can correspond to other like processor modules and/or memory modules connected to the same system memory bus. In some embodiments buffer memory can be different than local memory 210. For example, buffer memory can have a slower access time than local memory 210. However, in other embodiments, buffer memory and local memory can be implemented with like memory devices.

In very particular embodiments, write data for processing can have an expected maximum flow rate. A processor module 200 can be configured to operate on such data at, or faster than, such a flow rate. In this way, a master device (not shown) can write data to a processor module without danger of overwriting data "in process".

The various computing elements of a processor module 200 can be implemented as one or more integrated circuit devices (ICs). It is understood that the various components shown in FIG. 2-0 can be formed in the same or different ICs. For example, control logic 212, memory interface 214, and/or arbiter logic 206 can be implemented on one or more logic ICs, while offload processor(s) 208 and local memory 210 are separate ICs. Logic ICs can be fixed logic (e.g., application specific ICs), programmable logic (e.g., field programmable gate arrays, FPGAs), or combinations thereof.

Advantageously, the foregoing hardware and systems can provide improved computational performance as compared to traditional computing systems. Conventional systems, including those based on x86 processors, are often ill-equipped to handle such high volume applications. Even idling, x86 processors use a significant amount of power, and near continuous operation for high bandwidth packet analysis or other high volume processing tasks makes the processor energy costs one of the dominant price factors.

In addition, conventional systems can have issues with the high cost of context switching wherein a host processor is required to execute instructions which can include switching from one thread to another. Such a switch can require storing and recalling the context for the thread. If such context data is resident in a host cache memory, such a context switch can occur relatively quickly. However, if such context data is no longer in cache memory (i.e., a cache miss), the data must be recalled from system memory, which can incur a multi-cycle latency. Continuous cache misses during context switching can adversely impact system performance.

FIG. 2-1 shows a processor module 200-1 according to one very particular embodiment which is capable of reducing issues associated with high volume processing or context switching associated with many conventional server systems. A processor module 200-1 can include ICs 220-0/1 mounted to a printed circuit board (PCB) type substrate 222. PCB type substrate 222 can include in-line module connector 202, which in one very particular embodiment, can be a DIMM compatible connector. IC 220-0 can be a system-on-chip (SoC) type device, integrating multiple functions. In the very particular embodiment shown, an IC 220-0 can include embedded processor(s), logic and memory. Such embedded processor(s) can be offload processor(s) 208 as described herein, or equivalents. Such logic can be any of controller logic 212, memory interface 204 and/or arbiter logic 206, as described herein, or equivalents. Such memory can be any of local memory 210, cache memory for offload processor(s) 208, or buffer memory, as described herein, or equivalents. Logic IC 220-1 can provide logic functions not included IC 220-0.

FIG. 2-2 shows a processor module 200-2 according to another very particular embodiment. A processor module 200-2 can include ICs 220-2, -3, -4, -5 mounted to a PCB type substrate 222, like that of FIG. 2-1. However, unlike FIG. 2-1 , processor module functions are distributed among single purpose type ICs. IC 220-2 can be a processor IC, which can be an offload processor 208. IC 220-3 can be a memory IC which can include local memory 210, buffer memory, or combinations thereof. IC 220-4 can be a logic IC which can include control logic 212, and in one very particular embodiment, can be an FPGA. IC 220-5 can be another logic IC which can include memory interface 204 and arbiter logic 206, and in one very particular embodiment, can also be an FPGA.

It is understood that FIGS. 2-1/2 represent but two of various implementations. The various functions of a processor module can be distributed over any suitable number of ICs, including a single SoC type IC.

FIG. 2-3 shows an opposing side of a processor module 200-1 or 200-2 according to a very particular embodiment. Processor module 200-3 can include a number of memory ICs, one shown as 220-6, mounted to a PCB type substrate 222, like that of FIG. 2-1. It is understood that various processing and logic components can be mounted on an opposing side to that shown. A memory IC 220-6 can be configured to represent a portion of the physical memory space of a system. Memory ICs 220-6 can perform any or all of the following functions: operate independently of other processor module components, providing system memory accessed in a conventional fashion; serve as buffer memory, storing write data that can be processed with other processor module components, or serve as local memory for storing processor context information.

FIG. 2-4 shows a conventional DIMM module (i.e., it serves only a memory function) that can populate a memory bus along with processor modules as described herein, or equivalents.

FIG. 2-5 shows a system 230 according to one embodiment. A system 230 can include a system memory bus 228 accessible via multiple in-line module slots (one shown as 226). According to embodiments, any or all of the slots 226 can be occupied by a processor module 200 as described herein, or an equivalent. In the event all slots 226 are not occupied by a processor module 200, available slots can be occupied by conventional in-line memory modules 224. In a very particular embodiment, slots 226 can be DIMM slots.

In some embodiments, a processor module 200 can occupy one slot. However, in other embodiments, a processor module can occupy multiple slots.

In some embodiments, a system memory bus 228 can be further interfaced with one or more host processors and/or input/output device (not shown).

Having described processor modules according to various embodiments, operations of an offload processor module capable of interfacing with server or similar system via a memory bus and according to a particular embodiment will now be described.

FIG. 3 shows a system 301 that can receive and process packet data directed to it by IO virtualization, as described herein or equivalents. A system 301 can transport packet data requiring network overlay services to one or more computational units (one shown as 300) located on a module, which in particular embodiments, can include a connector compatible with an existing memory module. In some embodiments, a computational unit 300 can include a processor module as described in embodiments herein, or an equivalent. A computational unit 300 can be capable of intercepting or otherwise accessing packets sent over a memory bus 316 and carrying out processing on such packets, including but not limited to termination or metadata processing. A system memory bus 316 can be a system memory bus like those described herein, or equivalents (e.g., 228).

Referring still to FIG. 3, a system 301 can include an I/O device 302 which can receive packet or other I/O data from an external source. In some embodiments I/O device 302 can include physical or virtual functions generated by the physical device to receive a packet or other I/O data from the network or another computer or virtual machine. In the very particular embodiment shown, an I/O device 302 can include a network interface card (NIC) having input buffer 302a (e.g., DMA ring buffer) and an I/O virtualization function 302b.

According to embodiments, an I/O device 302 can write a descriptor including details of the necessary memory operation for the packet (i.e. read/write, source/destination). Such a descriptor can be assigned a virtual memory location (e.g., by an operating system of the system 301 ). I/O device 302 then communicates with an input output memory management unit (IOMMU) 304 which can translate virtual addresses to corresponding physical addresses with an IOMMU function 304b. In the particular embodiment shown, a translation look-aside buffer (TLB) 304a can be used for such translation. Virtual function reads or writes data between I/O device and system memory locations can then be executed with a direct memory transfer (e.g., DMA) via a memory controller 306b of the system 301. An I/O device 302 can be connected to IOMMU 304 by a host bus 312. In one very particular embodiment, a host bus 312 can be a peripheral interconnect (PCI) type bus. IOMMU 304 can be connected to a host processing section 306 at a central processing unit I/O (CPU IO) 306a. In the embodiment shown, such a connection 314 can support a HyperTransport (HT) protocol.

In the embodiment shown, a host processing section 306 can include the CPUIO 306a, memory controller 306b, processing core 306c and corresponding provisioning agent 306d.

In particular embodiments, a computational unit 300 can interface with the system bus 316 via standard inline module connection, which in very particular embodiments can include a DIMM type slot. In the embodiment shown, a memory bus 316 can be a DDR3 type memory bus. Alternate embodiments can include any suitable system memory bus. Packet data can be sent by memory controller 306b via memory bus 316 to a DMA slave interface 310a. DMA slave interface 310a can be adapted to receive encapsulated read/write instructions from a DMA write over the memory bus 316.

A hardware scheduler (308b/c/d/e/h) can perform traffic management on incoming packets by categorizing them according to flow using session metadata. Packets can be queued for output in an onboard memory

(310b/308a/308m) based on session priority. When the hardware scheduler determines that a packet for a particular session is ready to be processed by the offload processor 308i, the onboard memory is signaled for a context switch to that session. Utilizing this method of prioritization, context switching overhead can be reduced, as compared to conventional approaches. That is, a hardware scheduler can handle context switching decisions and thus optimize the performance of the downstream resource (e.g., offload processor 308i).

As noted above, in very particular embodiments, an offload processor 308i can be a "wimpy core" type processor. According to some embodiments, a host processor 306c can be a "brawny core" type processor (e.g., an x86 or any other processor capable of handling "heavy touch" computational operations). While an I/O device 302 can be configured to trigger host processor interrupts in response to incoming packets, according to embodiments, such interrupts can be disabled, thereby reducing processing overhead for the host processor 306c. In some very particular embodiments, an offload processor 308i can include an ARM, ARC, Tensilica, MIPS, Strong/ARM or any other processor capable of handling "light touch" operations. Preferably, an offload processor can run a general purpose operating system for executing a plurality of sessions, which can be optimized to work in conjunction with the hardware scheduler in order to reduce context switching overhead.

Referring still to FIG. 3, in operation, a system 301 can receive packets from an external network over a network interface. The packets are destined for either a host processor 306c or an offload processor 308i based on the classification logic and schematics employed by I/O device 302. In particular embodiments, I/O device 302 can operate as a virtualized NIC, with packets for a particular logical network or to a certain virtual MAC (VMAC) address can be directed into separate queues and sent over to the destination logical entity. Such an arrangement can transfer packets to different entities. In some embodiments, each such entity can have a virtual driver, a virtual device model that it uses to communicate with connected virtual network.

According to embodiments, multiple devices can be used to redirect traffic to specific memory addresses. So, each of the network devices operates as if it is transferring the packets to the memory location of a logical entity. However, in reality, such packets are transferred to memory addresses where they can be handled by one or more offload processors (e.g., 308i). In particular embodiments such transfers are to physical memory addresses, thus logical entities can be removed from the processing, and a host processor can be free from such packet handling.

Accordingly, embodiments can be conceptualized as providing a memory "black box" to which specific network data can be fed. Such a memory black box can handle the data (e.g., process it) and respond back when such data is requested.

Referring still to FIG. 3, according to some embodiments, I/O device 302 can receive data packets from a network or from a computing device. The data packets can have certain characteristics, including transport protocol number, source and destination port numbers, source and destination IP addresses, for example. The data packets can further have metadata that is processed (308d) that helps in their classification and management.

I/O device 302 can include, but is not limited to, peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with a host motherboard via PCI or PCIe bus (e.g., 312). Examples of I/O devices include a network interface controller (NIC), a host bus adapter, a converged network adapter, an ATM network interface, etc.

In order to provide for an abstraction scheme that allows multiple logical entities to access the same I/O device 302, the I/O device may be virtualized to provide for multiple virtual devices each of which can perform some of the functions of the physical I/O device. The IO virtualization program (e.g., 302b) according to an embodiment, can redirect traffic to different memory locations (and thus to different offload processors attached to modules on a memory bus). To achieve this, an I/O device 302 (e.g., a network card) may be partitioned into several function parts; including controlling function (CF) supporting input/output virtualization (IOV) architecture (e.g., single-root IOV) and multiple virtual function (VF) interfaces. Each virtual function interface may be provided with resources during runtime for dedicated usage. Examples of the CF and VF may include the physical function and virtual functions under schemes such as Single Root I/O Virtualization or Multi-Root I/O Virtualization architecture. The CF acts as the physical resources that sets up and manages virtual resources. The CF is also capable of acting as a full-fledged 10 device. The VF is responsible for providing an abstraction of a virtual device for communication with multiple logical entities/ multiple memory regions.

The operating system/the hypervisor/ any of the virtual machines/user code running on a host processor 306c may be loaded with a device model, a VF driver and a driver for a CF. The device model may be used to create an emulation of a physical device for the host processor 306c to recognize each of the multiple VFs that are created.

The device model may be replicated multiple times to give the impression to a VF driver (a driver that interacts with a virtual 10 device) that it is interacting with a physical device of a particular type.

For example, a certain device module may be used to emulate a network adapter such as the Intel® Ethernet Converged Network Adapter(CNA) X540-T2, so that the I/O device 302 believes it is interacting with such an adapter. In such a case, each of the virtual functions may have the capability to support the functions of the above said CNA, i.e., each of the Physical Functions should be able to support such functionality. The device model and the VF driver can be run in either privileged or non-privileged mode. In some embodiments, there is no restriction with regard to who hosts/runs the code corresponding to the device model and the VF driver. The code, however, has the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.

An application or provisioning agent 306d, as part of an application/user level code running in a kernel, may create a virtual I/O address space for each VF, during runtime and allocate part of the physical address space to it.

For example, if an application handling the VF driver instructs it to read or write packets from or to memory addresses Oxaaaa to Oxffff, the device driver may write I/O descriptors into a descriptor queue with a head and tail pointer that are changed dynamically as queue entries are filled. The data structure may be of another type as well, including but not limited to a ring structure 302a or hash table.

The VF can read from or write data to the address location pointed to by the driver. Further, on completing the transfer of data to the address space allocated to the driver, interrupts, which are usually triggered to the host processor to handle said network packets, can be disabled. Allocating a specific I/O space to a device can include allocating said 10 space a specific physical memory space occupied.

In another embodiment, the descriptor may comprise only a write operation, if the descriptor is associated with a specific data structure for handling incoming packets. Further, the descriptor for each of the entries in the incoming data structure may be constant so as to redirect all data write to a specific memory location. In an alternate embodiment, the descriptor for consecutive entries may point to consecutive entries in memory so as to direct incoming packets to consecutive memory locations.

Alternatively, said operating system may create a defined physical address space for an application supporting the VF drivers and allocate a virtual memory address space to the application or provisioning agent 306d, thereby creating a mapping for each virtual function between said virtual address and a physical address space. Said mapping between virtual memory address space and physical memory space may be stored in IOMMU tables

(e.g., a TLB 304a). The application performing memory reads or writes may supply virtual addresses to say virtual function, and the host processor OS may allocate a specific part of the physical memory location to such an application. Alternatively, VF may be configured to generate requests such as read and write which may be part of a direct memory access (DMA) read or write operation, for example. The virtual addresses is be translated by the IOMMU 304 to their corresponding physical addresses and the physical addresses may be provided to the memory controller for access. That is, the IOMMU 304 may modify the memory requests sourced by the I/O devices to change the virtual address in the request to a physical address, and the memory request may be forwarded to the memory controller for memory access. The memory request may be forwarded over a bus 314 that supports a protocol such as HyperTransport 314. The VF may in such cases carry out a direct memory access by supplying the virtual memory address to the IOMMU 304.

Alternatively, said application may directly code the physical address into the VF descriptors if the VF allows for it. If the VF cannot support physical addresses of the form used by the host processor 306c, an aperture with a hardware size supported by the VF device may be coded into the descriptor so that the VF is informed of the target hardware address of the device. Data that is transferred to an aperture may be mapped by a translation table to a defined physical address space in the system memory. The DMA operations may be initiated by software executed by the processors, programming the I/O devices directly or indirectly to perform the DMA operations.

Referring still to FIG. 3, in particular embodiments, parts of computational unit 300 can be implemented with one or more FPGAs. In the system of FIG. 3, computational unit 300 can include FPGA 310 in which can be formed a DMA slave device module 310a and arbiter 31 Of. A DMA slave module 310a can be any device suitable for attachment to a memory bus 316 that can respond to DMA read/write requests. In alternate embodiments, a DMA slave module 310a can be another interface capable of block data transfers over memory bus 316. The DMA slave module 310a can be capable of receiving data from a DMA controller (when it performs a read from a 'memory' or from a peripheral) or transferring data to a DMA controller (when it performs a write instruction on the DMA slave module 310a). The DMA slave module 310a may be adapted to receive DMA read and write instructions encapsulated over a memory bus, (e.g., in the form of a DDR data transmission, such as a packet or data burst), or any other format that can be sent over the corresponding memory bus.

A DMA slave module 310a can reconstruct the DMA read/write instruction from the memory R/W packet.

The DMA slave module 310a may be adapted to respond to these instructions in the form of data reads/ data writes to the DMA master, which could either be housed in a peripheral device, in the case of a PCIe bus, or a system DMA controller in the case of an ISA bus.

I/O data that is received by the DMA device 310a can then queued for arbitration. Arbitration can include the process of scheduling packets of different flows, such that they are provided access to available bandwidth based on a number of parameters. In general, an arbiter 31 Of provides resource access to one or more requestors. If multiple requestors request access, an arbiter 31 Of can determine which requestor becomes the accessor and then passes data from the accessor to the resource interface, and the downstream resource can begin execution on the data. After the data has been completely transferred to a resource, and the resource has competed execution, the arbiter 31 Of can transfer control to a different requestor and this cycle repeats for all available requestors. In the embodiment of FIG. 3 arbiter 31 Of can notify other portions of computational unit 300 (e.g., 308) of incoming data.

Alternatively, a computation unit 300 can utilize an arbitration scheme shown in U.S. Patent 7,813,283, issued to Dalai on October 12, 2010, the contents of which are incorporated herein by reference. Other suitable arbitration schemes known in art could be implemented in embodiments herein. Alternatively, the arbitration scheme of the current invention might be implemented using an OpenFlow switch and an OpenFlow controller.

In the very particular embodiment of FIG. 3, computational unit 300 can further include notify/prefetch circuits 310c which can prefetch data stored in a buffer memory 310b in response to DMA slave module 310a, and as arbitrated by arbiter 31 Of. Further, arbiter 31 Of can access other portions of the computational unit 300 via a memory mapped I/O ingress path 31 Oe and egress path 31 Og.

Referring to FIG. 3, a hardware scheduler can include a scheduling circuit 308b/n to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Such classification can be performed by classifier 308e.

In some embodiments, session metadata 308d can serve as the criterion by which packets are prioritized and scheduled and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. The scheduling discipline chosen for this prioritization, or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), delay jitter (temporally shifting cells of a flow by different amounts) and by not admitting a connection (e.g., cannot simultaneously guarantee existing service level agreements (SLAs) with an additional flow's SLA).

According to embodiments, computational unit 300 can serve as part of a switch fabric, and provide traffic management with depth-limited output queues, the access to which is arbitrated by a scheduling circuit 308b/n. Such output queues are managed using a scheduling discipline to provide traffic management for incoming flows. The session flows queued in each of these queues can be sent out through an output port to a downstream network element.

It is noted that conventional traffic management do not take into account the handling and management of data by downstream elements except for meeting the SLA agreements it already has with said downstream elements.

In contrast, according to embodiments a scheduler circuit 308b/n can allocate a priority to each of the output queues and carry out reordering of incoming packets to maintain persistence of session flows in these queues. A scheduler circuit 308b/n can be used to control the scheduling of each of these persistent sessions into a general purpose operating system (OS) 308j, executed on an offload processor 308L Packets of a particular session flow, as defined above, can belong to a particular queue. The scheduler circuit 308b/n may control the prioritization of these queues such that they are arbitrated for handling by a general purpose (GP) processing resource (e.g., offload processor 308i) located downstream. An OS 308j running on a downstream processor 308i can allocate execution resources such as processor cycles and memory to a particular queue it is currently handling. The OS 308j may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element 308i as a separate entity. The fact that there can be multiple sessions running on a GP processing resource, each handling data from a particular session flow resident in a queue established by the scheduler circuit, tightly integrates the scheduler and the downstream resource (e.g., 308i). This can bring about persistence of session information across the traffic management and scheduling circuit and the general purpose processing resource 308L

Dedicated computing resources (e.g., 308i), memory space and session context information for each of the sessions can provide a way of handling, processing and/or terminating each of the session flows at the general purpose processor 308L The scheduler circuit 308b/n can exploit this functionality of the execution resource to queue session flows for scheduling downstream. The scheduler circuit 308b/n can be informed of the state of the execution resource(s) (e.g., 308i), the current session that is run on the execution resource; the memory space allocated to it, the location of the session context in the processor cache.

According to embodiments, a scheduler circuit 308b/n can further include switching circuits to change execution resources from one state to another. The scheduler circuit 308b/n can use such a capability to arbitrate between the queues that are ready to be switched into the downstream execution resource. Further, the downstream execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the scheduler circuit 308b/n to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.

According to embodiments, a scheduler circuit 308b/n can schedule different sessions on a downstream processing resource, wherein the two are operated in coordination to reduce the overhead during context switches. An important factor in decreasing the latency of services and engineering computational availability can be hardware context switching synchronized with network queuing. In embodiments, when a queue is selected by a traffic manager, a pipeline coordinates swapping in of the cache (e.g., L2 cache) of the corresponding resource (e.g., 308i) and transfers the reassembled I/O data into the memory space of the executing process. In certain cases, no packets are pending in the queue, but computation is still pending to service previous packets. Once this process makes a memory reference outside of the data swapped, the scheduler circuit (308b/n) can enable queued data from an I/O device 302 to continue scheduling the thread.

In some embodiments, to provide fair queuing to a process not having data, a maximum context size can be assumed as data processed. In this way, a queue can be provisioned as the greater of computational resource and network bandwidth resource. As but one very particular example, a computation resource can be an ARM A9 processor running at 800 MHz, while a network bandwidth can be 3 Gbps of bandwidth. Given the lopsided nature of this ratio, embodiments can utilize computation having many parallel sessions (such that the hardware's prefetching of session-specific data offloads a large portion of the host processor load) and having minimal general purpose processing of data.

Accordingly, in some embodiments, a scheduler circuit 308b/n can be conceptualized as arbitrating, not between outgoing queues at line rate speeds, but arbitrating between terminated sessions at very high speeds. The stickiness of sessions across a pipeline of stages, including a general purpose OS, can be a scheduler circuit optimizing any or all such stages of such a pipeline.

Alternatively, a scheduling scheme can be used as shown in U.S. Patent No. 7,760,715 issued to Dalai on

July 20, 2010, incorporated herein by reference. This scheme can be useful when it is desirable to rate limit the flows for preventing the downstream congestion of another resource specific to the over-selected flow, or for enforcing service contracts for particular flows. Embodiments can include arbitration scheme that allows for service contracts of downstream resources, such as general purpose OS that can be enforced seamlessly.

Referring still to FIG. 3, a hardware scheduler according to embodiments herein, or equivalents, can provide for the classification of incoming packet data into session flows based on session metadata. It can further provide for traffic management of these flows before they are arbitrated and queued as distinct processing entities on the offload processors.

In some embodiments, offload processors (e.g., 308i) can be general purpose processing units capable of handling packets of different application or transport sessions. Such offload processors can be low power processors capable of executing general purpose instructions. The offload processors could be any suitable processor, including but not limited to: ARM, ARC, Tensilica, MIPS, StrongARM or any other processor that serves the functions described herein. Such offload processors have a general purpose OS running on them, wherein the general purpose OS is optimized to reduce the penalty associated with context switching between different threads or group of threads.

In contrast, context switches on host processors can be computationally intensive processes that require the register save area, process context in the cache and TLB entries to be restored if they are invalidated or overwritten. Instruction Cache misses in host processing systems can lead to pipeline stalls and data cache misses lead to operation stall and such cache misses reduce processor efficiency and increase processor overhead.

In contrast, an OS 308j running on the offload processors 308i in association with a scheduler circuit 308b/n, can operate together to reduce the context switch overhead incurred between different processing entities running on it. Embodiments can include a cooperative mechanism between a scheduler circuit and the OS on the offload processor 308i, wherein the OS sets up session context to be physically contiguous (physically colored allocator for session heap and stack) in the cache; then communicates the session color, size, and starting physical address to the scheduler circuit upon session initialization. During an actual context switch, a scheduler circuit can identify the session context in the cache by using these parameters and initiate a bulk transfer of these contents to an external low latency memory (e.g., 308g). In addition, the scheduler circuit can manage the prefetch of the old session if its context was saved to a local memory 308g. In particular embodiments, a local memory 308g can be low latency memory, such as a reduced latency dynamic random access memory (RLDRAM), as but one very particular embodiment. Thus, in embodiments, session context can be identified distinctly in the cache.

In some embodiments, context size can be limited to ensure fast switching speeds. In addition or alternatively, embodiments can include a bulk transfer mechanism to transfer out session context to a local memory 308g. The cache contents stored therein can then be retrieved and prefetched during context switch back to a previous session. Different context session data can be tagged and/or identified within the local memory 308g for fast retrieval. As noted above, context stored by one offload processor may be recalled by a different offload processor.

In the very particular embodiment of FIG. 3, multiple offload processing cores can be integrated into a computation FPGA 308. Multiple computational FPGAs can be arbitrated by arbitrator circuits in another FPGA 310. The combination of computational FPGAs (e.g., 308) and arbiter FPGAs (e.g., 310) are referred to as "XIMM" modules or "Xockets DIMM modules" (e.g., computation unit 300). In particular applications, these XIMM modules can provide integrated traffic and thread management circuits that broker execution of multiple sessions on the offload processors.

FIG. 3 also shows an offload processor tunnel connection 308k, as well as a memory interface 308m and port 3081 (which can be an accelerator coherency port (ACP)). Memory interface 308m can access buffer memory 308a.

Having described various embodiments suitable for 10 virtualization operations, examples illustrating particular aspects of such embodiments will now be described.

FIG. 4 illustrates an example embodiment of a process 400 that can be executed by embodiments to lock the TLB entries. A process may start (402) with a determination being made to forward a packet to an offload processor (404). A memory access request can be generated (406). If the translation information is not present in a TLB (IOTLB in the embodiment shown) (No from 408), the transition information can be obtained and the TLB can be updated (410). In some embodiments, such an action can include a page table walk. If the translation information is present in a TLB (Yes from 408), a determination is made if the entry in the IOTLB of the translation information is to be locked (412). If the entry is not to be locked (No from 412), the process can terminate (416). If the entry is to be locked (Yes from 412), the corresponding TLB entry (or entries) can be locked (414), and the process can terminate (416).

FIG. 5 is a block diagram of a virtual switch 106a' based on a network interface card that can be included in the embodiments (e.g., 106a of FIG. 1-0). A virtual switch 106a' can receive (514) or transmit (512) packets or other I/O data to or from an external source. Transmitted or received data can be processed by a Layer 2 (L2) sorter 510, and held temporarily in queues (one shown as 506). In the particular embodiment of FIG. 5, virtual switch 106a' can include physical controlling functions (CFs) (502a) or virtual functions (VFs) (502) generated by the network interface card to receive a packet or other I/O data from the network or another computer or virtual machine. In addition, virtual switch 106a' can write a descriptor (one shown as 504) including details of the necessary memory operation for the packet (i.e. read/write, source/destination). Such a descriptor can be assigned a virtual memory location (e.g., by an operating system). Virtual function reads or writes data between I/O device and system memory locations can then be executed with a direct memory transfer (e.g., DMA) via a DMA controller 518. In this particular embodiment, the network interface card can be connected to a host bus 500, which can be a PCI type bus.

It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element. Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

Claims

IN THE CLAIMS

I . An input-output (IO) virtualization system connectable to a network, the system comprising:

a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and

an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.

2. The system of claim 1 wherein the second virtual switch receives network packets via memory write operations on the memory bus and sends network packets via the memory read operations on the memory bus.

3. The system of claim 1 , wherein the offload processor module comprises separately addressable offload processors, at least two of the offload processors being configured to process network packets directed to memory addresses corresponding to the offload processors.

4. The system of claim 1 wherein the memory bus supports a dual data rate (DDR) protocol.

5. The system of claim 4 wherein the protocol is DDR3.

6. The system of claim 1 wherein the first virtual switch is configured to communicate with the second virtual switch by direct memory accesses.

7. The system of claim 1 wherein the first virtual switch comprises a direct memory access (DMA) master.

8. The system of claim 1 wherein the second virtual switch comprises a direct memory access (DMA) slave.

9. The system of claim 1 wherein the second virtual switch comprises a scheduler and an arbiter to prioritize handling of network packets.

10. A method for processing data, comprising the steps of"

transporting data to a second virtual switch from a first virtual switch using a memory bus having a defined memory transport protocol,

writing the transported data to a target memory location, and

processing the data written to the target memory location with at least one offload processor included on an offload processor module.

I I . The method of claim 10, further including sending data processed by the at least one offload processor to first virtual switch via the second virtual switch.

12. The method of claim 10, wherein transporting data to the second virtual switch includes a memory write operation to a physical memory address corresponding to a virtual memory address determined by the first virtual switch.

13. The method of claim 10, wherein processing the data written to the target memory location includes processing data at specific memory addresses by offload processors corresponding to such specific memory addresses.

14. The method of claim 10 wherein transporting data to the second virtual switch includes transporting the data over a memory bus using a double data rate (DDR) protocol.

15. The method of claim 10 wherein transporting data to the second virtual switch includes operating the first virtual switch as a direct memory access (DMA) master.

16. The method of claim 10 wherein transporting data to the second virtual switch includes operating the second virtual switch as a direct memory access (DMA) slave.

17. The method of claim 10 wherein processing the data includes prioritizing from among multiple data values.

18. A memory bus connected module, connectable to a first virtual switch for providing input-output (IO) virtualization services, the module comprising:

a second virtual switch coupled to the first virtual switch via a memory bus connection,

a plurality of offload processors coupled to the memory bus connection, and

at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors.

19. The module of claim 18, further comprising an arbiter configured to prevent memory access conflicts to the at least one memory unit.

20. The module of claim 18, wherein the module is configured to receive data at the second virtual switch by memory writes of a system and to send data at the second virtual switch by memory reads of the system.

21. The module of claim 18, wherein the module is configured to receive the data by direct memory access operations.

22. The module of claim 18, wherein the module comprises a direct memory access (DMA) slave.

23. The module of claim 18, wherein the memory bus connection is compatible with a dual in line memory (DIMM) socket.