WO2014071557A1 - Vdcol control method for series mtdc system and vdcol synthesizer thereof - Google Patents

Vdcol control method for series mtdc system and vdcol synthesizer thereof Download PDF

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Publication number
WO2014071557A1
WO2014071557A1 PCT/CN2012/084148 CN2012084148W WO2014071557A1 WO 2014071557 A1 WO2014071557 A1 WO 2014071557A1 CN 2012084148 W CN2012084148 W CN 2012084148W WO 2014071557 A1 WO2014071557 A1 WO 2014071557A1
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Prior art keywords
vdcol
current
current order
synthesizer
converter
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PCT/CN2012/084148
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French (fr)
Inventor
Xiaobo Yang
Dawei YAO
Chunming YUAN
Chengyan YUE
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Abb Technology Ltd.
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Priority to PCT/CN2012/084148 priority Critical patent/WO2014071557A1/en
Priority to CN201280042508.7A priority patent/CN103814496B/en
Publication of WO2014071557A1 publication Critical patent/WO2014071557A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
    • H02J2003/365—Reducing harmonics or oscillations in HVDC
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

Definitions

  • the invention relates to the series MTDC (multi-terminal HVDC) system technical field, and more particularly to a VDCOL (Voltage Dependent Current Order Limiter) control method for series MTDC system and a VDCOL synthesizer thereof.
  • VDCOL Voltage Dependent Current Order Limiter
  • VDCOL is utilized due to the following reasons:
  • Fig. 2 shows a simplified block diagram of a typical VDCOL submodule in prior art.
  • all converters are given a closed loop current controller.
  • the rectifier controls the pole DC current and the inverter controls the pole DC voltage. This is done by adding a negative current margin l ma rgin on the current order lordjim in the inverter.
  • VST voltage setting terminal
  • VDCOL function which is designed originally for 2-terminal HVDC system, cannot be applicable directly for a series MTDC system.
  • the DC voltages in the VDCOL function are defined across the converters, and the decreased DC voltage at a VST may not be measured by the CST directly and vice versa, the current margin rule will be destroyed without additional coordination of current orders, which will result in abnormal operation point of the series MTDC system. In contrast, such situation will not happen in a 2-terminal HVDC or even parallel MTDC system.
  • Fig.3 illustrates a monopolar 4-terminal series MTDC system, which consists of two rectifiers (R1 and R2) and two inverters (11 and I2).
  • R1 , R2, 11 and I2 are serial connected via DC lines, and R1 and I2 are grounded as lower voltage converter stations.
  • R1 controls the DC current as CST while R2, 11 and I2 control respective DC voltage as VSTs.
  • the current orders for R1 , R2, 11 and I2 are lRi_ 0 rd, lR2_ord, ln_ord and l
  • the DC current reference values for current controllers of every converter have the following relationship with the updating of respective current margins:
  • Fig.4 illustrates the abnormal operation point after the DC voltage depression of R1.
  • the present invention proposes a VDCOL control method for the series MTDC system and a VDCOL synthesizer thereof.
  • the present invention proposes a VDCOL control method for the series MTDC system and a VDCOL synthesizer thereof, which set current margins for current reference of each converter during either steady state or transient state of the series MTDC; meanwhile the sequence of current margins is still unchanged.
  • the present invention provides a VDCOL control method for a series MTDC system.
  • the method comprises: calculating the current order limitation value (!ordjim) of each converter by respective VDCOL submodule; and comparing all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current order (l 0 rd_comn)-
  • the method further comprises: selecting a rectifier as the current setting terminal (CST) and enabling its VDCOL; obtaining the DC current order and measured DC voltages across converter; and sending the common current order (l 0 rd_comn) to the current controllers of voltage setting terminals (VSTs) and the CST.
  • the V/l characteristics of the VDCOL can be modified, which comprises increasing or decreasing time constants, changing voltage limitation settings or current limitation settings to improve the AC system recovery performance where there is a voltage drop during the operation of the series MTDC system.
  • the current order synchronization of the series MTDC system is always implemented by the VDCOL.
  • the method further comprises setting current margin of each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
  • all converters receive the respective current orders from CST, which updates the current margins and calculate current references via VDCOL of respective converters.
  • VDCOL synthesizer for implementing VDCOL control method for a series MTDC system.
  • the VDCOL synthesizer comprises: a calculating module, configured to calculate the current order limitation value (l or d_iim) of each converter with the input DC voltages across the respective DC converters at the CST side; and a comparison module, configured to compare all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current reference (l 0 rd_comn)-
  • the VDCOL synthesizer further comprises: a selecting module, configured to select a rectifier as the current setting terminal (CST) and enabling its VDCOL; a receiving module, configured to obtain the DC current order and measured DC voltages across the respective DC converters; and a sending module, configured to send the common current order (l or d_comn) to the current controllers of voltage setting terminals (VSTs) and the CST.
  • a selecting module configured to select a rectifier as the current setting terminal (CST) and enabling its VDCOL
  • a receiving module configured to obtain the DC current order and measured DC voltages across the respective DC converters
  • a sending module configured to send the common current order (l or d_comn) to the current controllers of voltage setting terminals (VSTs) and the CST.
  • the calculating module further comprises a plurality of VDCOL submodules whose V/l characteristics can be modified, comprising increasing or decreasing time constants or changing voltage and current limitation settings to improve the AC system recovery performance when there is a voltage drop during the operation of the series MTDC system.
  • the VDCOL synthesizer further comprises a synchronization module configured to implement the current order synchronization of the series MTDC system.
  • the VDCOL synthesizer further comprises a margin setting module in each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
  • the current margins of VSTs are different.
  • every VST comprises a receiving module to receive the common current order.
  • the current reference value of each VST is equal to the sum of the common current order and its current margin.
  • the measured DC voltages of each converter can be used as inputs of the comparison module in the VDCOL to calculate the common current order for each converter.
  • every common current order received by VSTs will be echoed back to CST by telecommunication to calculate sending time sequence of common current order from CST to different VSTs.
  • the proposed VDCOL control method for the series MTDC system and VDCOL synthesizer thereof introduces a developed VDCOL function to protect the series MTDC system during AC faults and improves the AC system stability.
  • Fig.1 illustrates a typical VDCOL characteristic for a two terminal HVDC system in prior art
  • Fig.2 illustrates a simplified block diagram of a typical VDCOL submodule in prior art
  • Fig.3 illustrates a monopolar 4-terminal series MTDC system
  • Fig.4 illustrates the abnormal operation point after the DC voltage depression of R1 ;
  • Fig.5 illustrates a flow chart of a VDCOL control method for the series
  • Fig.6 illustrates a module for calculating the current reference with different current margins according to an embodiment of the present invention
  • Fig.7 illustrates the current order calculated with inputs of DC voltages of all the converters and current order according to an embodiment of the present invention
  • Fig.8 illustrates the current order calculated with inputs of DC voltages of all the converters with same/similar nominal DC voltage across the converters and current order according to another embodiment of the present invention.
  • Fig.9 illustrates a current order synchronization module in VDCOL synthesizer according to an embodiment of the present invention.
  • Fig.5 illustrates a flow chart of a VDCOL control method for a series MTDC system according to an embodiment of the present invention.
  • the voltage dependent current order limiter (VDCOL) method 500 for a series MTDC system comprises the following steps:
  • Step 502 selecting a converter as the current setting terminal and enabling its VDCOL. Every converter involves VDCOL function, but only the CST enables VDCOL functions while VSTs will receive current references from the CST.
  • the enabled VDCOL receive current order from master controller and acquire measured DC voltage values across each converter as inputs for respective VDCOL submodule.
  • Step 504 calculating the current order limitation value (l or d_iim) of each converter by VDCOL or respective VDCOL submodules.
  • Step 506 comparing all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current order (l 0 rd_comn)-
  • Step 508 sending the common current order l 0 rd_comn to the current controllers of VSTs and said CST.
  • the V/l characteristics of the VDCOL can be modified; for instance, rising and decreasing time constants to obtain an optimized performance for the AC system when the voltage drops. Furthermore, the current order synchronization is always implemented by the CST.
  • Fig.6 illustrates a module for calculating the current reference with different current margins according to an embodiment of the present invention.
  • each VST has current margin setting module, in detail, rectifiers have positive current margins and inverters have negative current margins. All the VSTs have current regulators, which receive the current order from CST and take the current margins into consideration to calculate current references respectively.
  • the current reference constraint of each converter can be given below:
  • the rectifier with the lowest current reference re f_Ri will be taken by the CST as current reference.
  • the module for calculating the current reference with different reference margins includes but not limited to be realized in the current controller of individual VSTs; for example, such module also can be realized in a sending module.
  • Fig.7 illustrates the current order calculated with inputs of DC voltages of all the converters and current order according to an embodiment of the present invention.
  • the VDCOL synthesizer for implementing VDCOL control method for a series TDC system, and the VDCOL synthesizer comprises: a calculating module 1 , configured to calculate the current order of each converter with the input DC voltages at said CST side; and a comparison module 2, configured to compare all the current orders of each converter and the current order of master controller and choosing the minimal current order as a current reference.
  • the VDCOL synthesizer for implementing VDCOL control method for a series MTDC system further comprises: a selecting module, configured to select a rectifier as the current setting terminal and enabling its VDCOL; a receiving module, configured to obtain the DC current reference and measured DC voltages across respective converters; and a sending module, configured to send said current reference to the VSTs.
  • a selecting module configured to select a rectifier as the current setting terminal and enabling its VDCOL
  • a receiving module configured to obtain the DC current reference and measured DC voltages across respective converters
  • a sending module configured to send said current reference to the VSTs.
  • VSTs of rectifier type have positive current margins
  • VSTs of inverter type have negative current margins.
  • V/l characteristic of said VDCOL submodule 11 can be modified, which comprises increasing or decreasing time constants or changing voltage and current limitation settings to improve the AC system recovery performance where there is a voltage drop during the operation of the series TDC system.
  • the VDCOL synthesizer further comprises a synchronization module in the
  • CST configured to implement the current order synchronization of the series MTDC system
  • a margin setting module in each VST in which the rectifiers have positive current margins and the inverters have negative current margins
  • a current regulator in each VST, which receive the current order from the CST and update with the respective current margin to calculate current references respectively.
  • Fig.8 illustrates the current order calculated with inputs of DC voltages of all the converters with same/similar nominal DC voltage across the converters and current order according to another embodiment of the present invention.
  • the VDCOL synthesizer receives the current setting values. If each converter has same/similar nominal DC voltage, the measured DC voltages across each converter can be used as inputs of comparison module in the VDCOL to calculate the current reference for each converter.
  • Fig.9 illustrates a current order synchronization module in VDCOL synthesizer according to an embodiment of the present invention.
  • the current order synchronization module maintains the current margins at all times to avoid a DC power control collapse.
  • the synchronization module handles this coordination through the telecommunication link.
  • the function of the synchronization unit is to perform the following: for increase of Iord_ ⁇ mn, first increase in the rectifiers then in the inverters; for decrease of i 0 rd_ ⁇ mn, first decrease in the inverters then in the rectifiers. Every current references received by VSTs will be echoed back to CST by telecommunication to calculate proper time sequence for the sending of common current order from CST.
  • VDCOL Voltage Dependent Current Order Limiter
  • the VDCOL method for the series MTDC system is realized to protect the series MTDC system during faults and also improve the AC system stability.
  • the forced retard function can be operated normally in the series MTDC system.

Abstract

A VDCOL (Voltage Dependent Current Order Limiter) control method for a series MTDC (Multi-Terminal HVDC) system comprises calculating the current order limitation value of each converter by respective VDCOL submodule, comparing all the current order limitation values of each converter, and choosing the minimal current order limitation value as a common current order. Meanwhile a synthesizer thereof is provided. The solutions of the method and synthesizer are to protect the series MTDC system during faults and also improve the AC system stability.

Description

VDCOL CONTROL METHOD FOR SERIES MTDC SYSTEM AND VDCOL
SYNTHESIZER THEREOF
FIELD OF THE INVENTION
The invention relates to the series MTDC (multi-terminal HVDC) system technical field, and more particularly to a VDCOL (Voltage Dependent Current Order Limiter) control method for series MTDC system and a VDCOL synthesizer thereof.
BACKGROUND OF THE INVENTION VDCOL is generally used for HVDC system to reduce the DC current when
DC voltage decreases significantly. The VDCOL is utilized due to the following reasons:
1 , avoid power instability during and after disturbances in the AC network;
2, define a fast and controlled restart after clearance of AC and DC faults; 3, avoid current stresses on the thyristors at a continuous commutation failure; and
4, suppress the probability of continuous commutation failures at recovery.
In a HVDC system, DC voltage is measured to generate corresponding current limitation order with a pre-defined V/l characteristic curve. A typical VDCOL characteristic for a 2-terminal HVDC system is shown in
Fig.1. For the 2-terminal HVDC system, as the DC voltages in the VDCOL function are defined between pole lines to ground, which are almost equal along the transmission line, both rectifier side and inverter side can trigger the VDCOL function if the decrease of DC voltage is large enough during a fault. In the VDCOL logic, the current orders don't apply for the respective current controllers of the converters directly. For each converter, the VDCOL will determine the final current reference lref according to the DC voltage level and max/min current reference limitation.
Fig. 2 shows a simplified block diagram of a typical VDCOL submodule in prior art. In a two terminal HVDC transmission, all converters are given a closed loop current controller. Normally, the rectifier controls the pole DC current and the inverter controls the pole DC voltage. This is done by adding a negative current margin lmargin on the current order lordjim in the inverter.
In the series MTDC system, multiple current margins are needed to be defined. For example, if one of the rectifiers in a series MTDC system operates as a current setting terminal (CST), various current margins would be defined for voltage setting terminals (VSTs) and performed strictly.
However, the existing VDCOL function, which is designed originally for 2-terminal HVDC system, cannot be applicable directly for a series MTDC system. For series MTDC, the DC voltages in the VDCOL function are defined across the converters, and the decreased DC voltage at a VST may not be measured by the CST directly and vice versa, the current margin rule will be destroyed without additional coordination of current orders, which will result in abnormal operation point of the series MTDC system. In contrast, such situation will not happen in a 2-terminal HVDC or even parallel MTDC system. For example, in a two-terminal HVDC system, the current reference of rectifier is always higher than that of inverter, because the DC voltage of rectifier and inverter are almost the same during steady or transient state, which makes the system return to the normal operation point finally.
An example is given below to show the disorder of current margins during DC depression and the consequent abnormal system operation point of the series MTDC system.
Fig.3 illustrates a monopolar 4-terminal series MTDC system, which consists of two rectifiers (R1 and R2) and two inverters (11 and I2). R1 , R2, 11 and I2 are serial connected via DC lines, and R1 and I2 are grounded as lower voltage converter stations.
During normal operation, R1 controls the DC current as CST while R2, 11 and I2 control respective DC voltage as VSTs. The current orders for R1 , R2, 11 and I2 are lRi_0rd, lR2_ord, ln_ord and l|2_0rd respectively, and equal to the current order lord from master controller:
Figure imgf000005_0001
As the VDCOL won't be triggered during normal DC voltages, the DC current reference values for current controllers of every converter have the following relationship with the updating of respective current margins:
Figure imgf000005_0002
However, during DC voltage depression, the relationship of (2) will be no longer satisfied and an abnormal operation point may be established.
Fig.4 illustrates the abnormal operation point after the DC voltage depression of R1.
When DC line voltage depression between R1 and R2 happens, for example caused by AC voltage depression of R1 , lRi_ref will decrease determined by VDCOL of R1 ; and the DC current ldc of the system will also decrease controlled by R1. When ldc is less then ln_ref or/and Ii2_ref, the current controllers in 11 or/and I2 starts de-saturation and begins current control too. Finally, DC voltages of both 11 and I2 decrease until ln_ref equals to lRi_ref, and Ii2_ref equals to lRi_ref. A new steady operation point established when R1 , 11 and I2 operate at current control together and R1 operates at very low voltage abnormally and finally the whole pole will stop operation due to DC undervoltage protection.
Therefore, the present invention proposes a VDCOL control method for the series MTDC system and a VDCOL synthesizer thereof. SUMMARY OF THE INVENTION
To overcome the problems mentioned above, the present invention proposes a VDCOL control method for the series MTDC system and a VDCOL synthesizer thereof, which set current margins for current reference of each converter during either steady state or transient state of the series MTDC; meanwhile the sequence of current margins is still unchanged.
According to an aspect of the present invention, it provides a VDCOL control method for a series MTDC system. The method comprises: calculating the current order limitation value (!ordjim) of each converter by respective VDCOL submodule; and comparing all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current order (l0rd_comn)-
According to a preferred embodiment of the present invention, the method further comprises: selecting a rectifier as the current setting terminal (CST) and enabling its VDCOL; obtaining the DC current order and measured DC voltages across converter; and sending the common current order (l0rd_comn) to the current controllers of voltage setting terminals (VSTs) and the CST.
According to a preferred embodiment of the present invention, the V/l characteristics of the VDCOL can be modified, which comprises increasing or decreasing time constants, changing voltage limitation settings or current limitation settings to improve the AC system recovery performance where there is a voltage drop during the operation of the series MTDC system.
According to another preferred embodiment of the present invention, the current order synchronization of the series MTDC system is always implemented by the VDCOL.
According to another preferred embodiment of the present invention, the method further comprises setting current margin of each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
According to another preferred embodiment of the present invention, all converters receive the respective current orders from CST, which updates the current margins and calculate current references via VDCOL of respective converters. According to the other aspect of the present invention, it provides a VDCOL synthesizer for implementing VDCOL control method for a series MTDC system. The VDCOL synthesizer comprises: a calculating module, configured to calculate the current order limitation value (lord_iim) of each converter with the input DC voltages across the respective DC converters at the CST side; and a comparison module, configured to compare all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current reference (l0rd_comn)-
According to another preferred embodiment of the present invention, the VDCOL synthesizer further comprises: a selecting module, configured to select a rectifier as the current setting terminal (CST) and enabling its VDCOL; a receiving module, configured to obtain the DC current order and measured DC voltages across the respective DC converters; and a sending module, configured to send the common current order (lord_comn) to the current controllers of voltage setting terminals (VSTs) and the CST.
According to another preferred embodiment of the present invention, the calculating module further comprises a plurality of VDCOL submodules whose V/l characteristics can be modified, comprising increasing or decreasing time constants or changing voltage and current limitation settings to improve the AC system recovery performance when there is a voltage drop during the operation of the series MTDC system.
According to another preferred embodiment of the present invention, the VDCOL synthesizer further comprises a synchronization module configured to implement the current order synchronization of the series MTDC system.
According to another preferred embodiment of the present invention, the VDCOL synthesizer further comprises a margin setting module in each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
According to another preferred embodiment of the present invention, the current margins of VSTs are different.
According to another preferred embodiment of the present invention, every VST comprises a receiving module to receive the common current order.
According to another preferred embodiment of the present invention, the current reference value of each VST is equal to the sum of the common current order and its current margin.
According to another preferred embodiment of the present invention, if each converter has similar nominal DC voltage across the converter, the measured DC voltages of each converter can be used as inputs of the comparison module in the VDCOL to calculate the common current order for each converter.
According to another preferred embodiment of the present invention, every common current order received by VSTs will be echoed back to CST by telecommunication to calculate sending time sequence of common current order from CST to different VSTs.
The proposed VDCOL control method for the series MTDC system and VDCOL synthesizer thereof introduces a developed VDCOL function to protect the series MTDC system during AC faults and improves the AC system stability.
BRIEF DESCRIPTION OF THE DRAWINGS The subject matter of the invention will be explained in more details in the following description with reference to preferred exemplary embodiments which are illustrated in the drawings, in which:
Fig.1 illustrates a typical VDCOL characteristic for a two terminal HVDC system in prior art;
Fig.2 illustrates a simplified block diagram of a typical VDCOL submodule in prior art;
Fig.3 illustrates a monopolar 4-terminal series MTDC system;
Fig.4 illustrates the abnormal operation point after the DC voltage depression of R1 ;
Fig.5 illustrates a flow chart of a VDCOL control method for the series
MTDC system according to an embodiment of the present invention;
Fig.6 illustrates a module for calculating the current reference with different current margins according to an embodiment of the present invention;
Fig.7 illustrates the current order calculated with inputs of DC voltages of all the converters and current order according to an embodiment of the present invention;
Fig.8 illustrates the current order calculated with inputs of DC voltages of all the converters with same/similar nominal DC voltage across the converters and current order according to another embodiment of the present invention; and
Fig.9 illustrates a current order synchronization module in VDCOL synthesizer according to an embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Exemplary embodiments of the present invention are described in conjunction with the accompanying drawings hereinafter. For the sake of clarity and conciseness, not all the features of actual implementations are described in the specification.
Fig.5 illustrates a flow chart of a VDCOL control method for a series MTDC system according to an embodiment of the present invention.
As shown in Fig.5, the voltage dependent current order limiter (VDCOL) method 500 for a series MTDC system comprises the following steps:
Step 502, selecting a converter as the current setting terminal and enabling its VDCOL. Every converter involves VDCOL function, but only the CST enables VDCOL functions while VSTs will receive current references from the CST. The enabled VDCOL receive current order from master controller and acquire measured DC voltage values across each converter as inputs for respective VDCOL submodule.
Step 504, calculating the current order limitation value (lord_iim) of each converter by VDCOL or respective VDCOL submodules.
Step 506, comparing all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current order (l0rd_comn)-
Step 508, sending the common current order l0rd_comn to the current controllers of VSTs and said CST.
According to a preferred embodiment of the present invention, during the operation of the series MTDC, the V/l characteristics of the VDCOL can be modified; for instance, rising and decreasing time constants to obtain an optimized performance for the AC system when the voltage drops. Furthermore, the current order synchronization is always implemented by the CST.
Fig.6 illustrates a module for calculating the current reference with different current margins according to an embodiment of the present invention.
As shown in Fig.6, each VST has current margin setting module, in detail, rectifiers have positive current margins and inverters have negative current margins. All the VSTs have current regulators, which receive the current order from CST and take the current margins into consideration to calculate current references respectively. The current reference constraint of each converter can be given below:
^ref_Rn > •••J^ref_R2 ^ ^ref ill > ^ref ll > ^ref_I2 > ■■· > ^refjn (3)
The rectifier with the lowest current reference ref_Ri will be taken by the CST as current reference. It shall be noted that the module for calculating the current reference with different reference margins includes but not limited to be realized in the current controller of individual VSTs; for example, such module also can be realized in a sending module.
Fig.7 illustrates the current order calculated with inputs of DC voltages of all the converters and current order according to an embodiment of the present invention.
As shown in Fig.7, the VDCOL synthesizer for implementing VDCOL control method for a series TDC system is provided, and the VDCOL synthesizer comprises: a calculating module 1 , configured to calculate the current order of each converter with the input DC voltages at said CST side; and a comparison module 2, configured to compare all the current orders of each converter and the current order of master controller and choosing the minimal current order as a current reference.
In detail, the VDCOL synthesizer for implementing VDCOL control method for a series MTDC system further comprises: a selecting module, configured to select a rectifier as the current setting terminal and enabling its VDCOL; a receiving module, configured to obtain the DC current reference and measured DC voltages across respective converters; and a sending module, configured to send said current reference to the VSTs. In which VSTs of rectifier type have positive current margins whereas VSTs of inverter type have negative current margins.
The V/l characteristic of said VDCOL submodule 11 can be modified, which comprises increasing or decreasing time constants or changing voltage and current limitation settings to improve the AC system recovery performance where there is a voltage drop during the operation of the series TDC system. The VDCOL synthesizer further comprises a synchronization module in the
CST, configured to implement the current order synchronization of the series MTDC system; a margin setting module in each VST, in which the rectifiers have positive current margins and the inverters have negative current margins; and a current regulator in each VST, which receive the current order from the CST and update with the respective current margin to calculate current references respectively.
Fig.8 illustrates the current order calculated with inputs of DC voltages of all the converters with same/similar nominal DC voltage across the converters and current order according to another embodiment of the present invention.
As shown in Fig.8, comprising a current regulator in all VSTs, the VDCOL synthesizer receives the current setting values. If each converter has same/similar nominal DC voltage, the measured DC voltages across each converter can be used as inputs of comparison module in the VDCOL to calculate the current reference for each converter.
Fig.9 illustrates a current order synchronization module in VDCOL synthesizer according to an embodiment of the present invention.
As shown in Fig.9, the current order synchronization module maintains the current margins at all times to avoid a DC power control collapse. The synchronization module handles this coordination through the telecommunication link. The function of the synchronization unit is to perform the following: for increase of Iord_∞mn, first increase in the rectifiers then in the inverters; for decrease of i0rd_∞mn, first decrease in the inverters then in the rectifiers. Every current references received by VSTs will be echoed back to CST by telecommunication to calculate proper time sequence for the sending of common current order from CST.
According to the present invention, it can utilize the telecommunication for fast current order synchronization. It's obvious for the person skilled in art that all current references calculated at CST can greatly improve the feasibility of the whole system and the AC system stability. The proposed solutions provided in the present invention can easily implement Voltage Dependent Current Order Limiter (VDCOL) function to protect the series MTDC system during faults.
Based on the teaching of the present invention, the person skilled in art appreciates that the VDCOL method for the series MTDC system is realized to protect the series MTDC system during faults and also improve the AC system stability. With the proposed solutions, the forced retard function can be operated normally in the series MTDC system.
Though the present invention has been described on the basis of some preferred embodiments, those skilled in the art should appreciate that those embodiments should by no means limit the scope of the present invention. Without departing from the spirit and concept of the present invention, any variations and modifications to the embodiments should be within the apprehension of those with ordinary knowledge and skills in the art, and therefore fall in the scope of the present invention which is defined by the accompanied claims.

Claims

1. A voltage dependent current order limiter (VDCOL) control method for a series MTDC system, said VDCOL comprising several VDCOL submodules, wherein said method comprises:
calculating the current order limitation value (lordjim) of each converter by respective VDCOL submodule; and
comparing all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current
Order (l0rd_coTTin)-
2. The method according to claim 1 , wherein said method further comprises: selecting a rectifier as the current setting terminal (CST) and enabling its VDCOL;
obtaining the DC current order and measured DC voltages across each converter; and
sending said common current order (l0rd_comn) to the current controllers of voltage setting terminals (VST) and said CST
3. The method according to claim 1 or 2, wherein the V/l characteristics of said VDCOL can be modified, which comprises increasing or decreasing time constants, changing voltage limitation settings or current limitation settings to improve the AC system recovery performance where there is a voltage drop during the operation of the series MTDC system.
4. The method according to claim 1 or 2, wherein the current order synchronization of the series MTDC system is always implemented by said VDCOL.
5. The method according to claim 1 or 2, wherein said method further comprises setting current margin of each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
6. The method according to claim 1 or 2, wherein all converters receive the respective current orders from CST, which updates with the current margins and calculate current references via VDCOL of respective converters.
7. A VDCOL synthesizer for implementing VDCOL control method for a series MTDC system, wherein said VDCOL synthesizer comprises:
a calculating module (1 ), configured to calculate the current order limitation value (lordjim) of each converter with the input DC voltages across the respective DC converters at said CST side; and
a comparison module (2), configured to compare all the current order limitation values of each converter and choosing the minimal current order limitation value as a common current reference (l0rd_comn).
8. The VDCOL synthesizer according to claim 7, wherein said VDCOL synthesizer further comprises:
a selecting module, configured to select a rectifier as the current setting terminal (CST) and enabling its VDCOL;
a receiving module, configured to obtain the DC current order and measured DC voltages across the respective DC converters; and
a sending module, configured to send said common current order (lorcLcomn) to the current controllers of voltage setting terminals (VST) and said CST.
9. The VDCOL synthesizer according to claim 7 or 8, wherein said calculating module (1 ) further comprises a plurality of VDCOL submodules (11 ) whose V/l characteristics can be modified, comprising increasing or decreasing time constants or changing voltage and current limitation settings to improve the AC system recovery performance when there is a voltage drop during the operation of said series MTDC system.
10. The VDCOL synthesizer according to claim 7 or 8, wherein said VDCOL synthesizer further comprises a synchronization module configured to implement the current order synchronization of the series MTDC system.
11. The VDCOL synthesizer according to claim 7 or 8, wherein said VDCOL synthesizer further comprises a margin setting module in each VST, in which the rectifiers have positive current margins and the inverters have negative current margins.
12. The VDCOL synthesizer according to claim 11 , wherein said current margins of VSTs are different.
13. The VDCOL synthesizer according to claim 8, wherein every VST comprises a receiving module to receive the common current order.
14. The VDCOL synthesizer according to claim 13, wherein said current reference value of each VST is equal to the sum of the common current order and its current margin.
15. The VDCOL synthesizer according to claim 7, wherein if each converter has similar nominal DC voltage across the converter, the measured DC voltages of each converter can be used as inputs of said comparison module in the VDCOL to calculate the common current order for each converter.
16. The VDCOL synthesizer according to claim 7 or 8, wherein every common current order received by VSTs will be echoed back to CST by telecommunication to calculate sending time sequence of common current order from CST to different VSTs.
PCT/CN2012/084148 2012-11-06 2012-11-06 Vdcol control method for series mtdc system and vdcol synthesizer thereof WO2014071557A1 (en)

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