WO2013106973A1

WO2013106973A1 - Package-on-package semiconductor chip packaging structure and technology

Info

Publication number: WO2013106973A1
Application number: PCT/CN2012/000612
Authority: WO
Inventors: 刘胜; 陈润; 陈照辉
Original assignee: Liu Sheng; Chen Run; Chen Zhaohui
Priority date: 2012-01-18
Filing date: 2012-05-07
Publication date: 2013-07-25
Also published as: CN103219324A

Abstract

A package-on-package semiconductor chip packaging structure and technology. The packaging structure includes top-layer packaging and bottom-layer packaging. The bottom-layer packaging substrate is provided with a groove, with a semiconductor chip of the bottom-layer packaging being provided in the groove. Bonding pads are arranged on the substrate, and the bottom-layer semiconductor chip is connected to the bonding pads via bonding wires. The top-layer packaging is formed by packaging one or more semiconductor chips on the upper surface of a top-layer packaging substrate by way of lamination. Bonding pads are arranged on the top-layer packaging substrate, and the bonding pads are connected to the semiconductor chip(s) via bonding wires. The top-layer packaging part is sealed using a sealant. The top-layer packaging and the bottom-layer packaging are connected via a bonding pad and a solder ball array, and a sealant is filled between the top-layer packaging substrate and the bottom-layer packaging substrate. The packaging structure technology is completed by a top-layer packaging step, a bottom-layer packaging step and a top-layer packaging and bottom-layer packaging connection step. The advantages of the present invention are as follows: packaging density is improved effectively, the technology flow is simple, the substrate stiffness is high, it is not easy to produce warping, the overall thickness is thin and the reliability is high.

Description

Description Stacked semiconductor chip package structure and process

Technical field

The present invention relates to a semiconductor package technology, and more particularly to a stacked semiconductor chip package structure and process.

Background technique

Due to the increasing demand for miniaturization and light weight of electronic products, three-dimensional packaging has followed this trend, and three-dimensional electronic packaging technology has recently made rapid progress. Package on package technology is a low-cost three-dimensional packaging solution that integrates logic chips and memory chips into a single package, and can flexibly create memory capacity as needed, so ^_ is currently in mobile phones It has been widely used in electronic products. The conventional PoP package uses a thin package substrate. In the process flow, the substrate is thermally expanded to cause warpage, which makes the interconnection between the bottom layer and the top package difficult, and it is easy to cause fatigue, cracks, etc. in the combined ball, resulting in a product. The reliability is reduced.

Summary of the invention

The object of the present invention is to provide a stacked semiconductor chip package structure and process for the defects existing in the prior art. The invention comprises a top layer package, a bottom package, a solder ball array between the top package and the bottom package, a sealant between the top package and the bottom package, wherein the underlying package substrate is provided with an inverted trapezoidal four-slot, bottom layer The upper surface of the package substrate is a first surface, the lower surface of the bottom package substrate is a second surface, and the surface of the bottom package substrate is a third surface, and the semiconductor chip of the bottom package is disposed in the groove, first and second a pad is disposed on the third surface, and the bottom semiconductor chip is connected to the pad on the third surface through the bonding wire, and the top package is stacked on the upper surface of the top package substrate by one or several semiconductor chips, the top layer A pad is disposed on the upper surface and the lower surface of the package substrate, and the semiconductor chip in the top package is connected to the pad on the upper surface of the top package substrate through the bonding wire, and the top package portion is sealed by the sealant. The top package and the bottom package are connected to the solder ball array through pads, and the sealant is filled between the top package substrate and the bottom package substrate, see FIG.

The invention is provided with a groove on the bottom package substrate, and the bottom package chip is fixed at the bottom of the groove, so that the overall thickness of the package is not increased. Therefore, the package structure has the advantages of thin thickness and high reliability, as shown in FIG. The package substrate used in the bottom package is thicker than the conventional package substrate, so the rigidity of the substrate is larger and warpage is less likely to occur.

1 is a schematic cross-sectional view of a conventional PoP package. As can be seen from comparison with FIG. 1, the fundamental difference between the two is that the present invention is provided with a recess on the substrate of the underlying package. The conventional PoP package bottom substrate is thinner, but the underlying package chip is directly bonded on the upper surface of the underlying package substrate, which causes the overall thickness t2 of the conventional PoP' package bottom package to be no thinner than the thickness tl of the underlying package provided in this embodiment. . Moreover, since the package bottom substrate of the conventional package is thin, warpage is more likely to occur in the packaging process, which makes the bonding between the top package and the bottom package difficult, which may cause fatigue failure, breakage, etc. in the solder ball, and the like. The reliability of the packaged product.

The groove on the bottom package substrate is an inverted trapezoid, and the semiconductor chip of the bottom package is bonded to the bottom of the groove by a paste adhesive, or is soldered to the bottom of the groove by flip chip bonding, and the semiconductor chip is connected with the solder ball at the bottom of the groove. . A circuit for connection is provided in the underlying package substrate and the top package substrate. A solder ball array is disposed on the second surface of the bottom package substrate, and the solder ball array is coated by screen printing or electroplating or evaporation, and the solder ball array is reflowed, and the material thereof is SnAg, Sn, SnAgCu, PbSn.

The semiconductor chip mounted on the top layer is in a layered stacked structure, and the semiconductor chip and the bonding wire of the top package are sealed by a sealant, and the sealant is an epoxy molding compound. A single-layer or double-layer solder ball array is disposed between the top package and the bottom package, and the top package and the bottom package are connected by a reflow process, or a solder layer is deposited after plating a copper pillar on the lower surface pad of the top package substrate. A first surface of the bottom package substrate is plated with a copper pillar and a tantalum layer is deposited thereon. The material of the solder layer may be SnAg, Sn, SnAgCu, PbSn, and the top package substrate and the bottom package substrate are connected by a reflow process to complete the top layer. Electrical interconnection between the package and the underlying package. A process for stacking a semiconductor chip package structure, characterized in that it comprises the following steps in sequence:

A. preparing a bottom package substrate with a groove;

B. preparing a pad on three surfaces of the underlying package substrate;

C. mounting the underlying packaged semiconductor chip in the recess and completing wire bonding;

D. preparing a disk on the upper and lower surfaces of the top package substrate;

E. mounting the top package semiconductor chip on top of the top package substrate;

F. performing wire bonding of the stacked semiconductor chip of the top package;

G. Perform a top-sealing package;

H. On the top layer, the solder ball is soldered on the pad on the lower surface of the package substrate, and the connection between the top package and the bottom package is performed;

I. Fill the seal between the top package and the bottom package and solder the ball on the bottom surface of the second surface pad.

The invention has the advantages of effectively increasing the packing density, simple process flow, high rigidity of the substrate, less warpage, thin overall thickness and high reliability.

DRAWINGS

Figure 1 is a cross-sectional view of a conventional PoP package structure;

Figure 2 is a schematic view of the structure of the present invention;

Figure 3 is a cross-sectional view of the underlying package substrate of the present invention;

Figure 4 is a cross-sectional view of the underlying package substrate fixed by a patch adhesive semiconductor chip;

Figure 5 is a schematic view of the bottom semiconductor chip bonding leads;

Figure 6 is a cross-sectional view of the top package substrate;

Figure 7 is a cross-sectional view of the semiconductor chip mounted on the top package substrate;

Figure 8 is a cross-sectional view of a two-layer semiconductor chip fixed by a patch adhesive;

Figure 9 is a cross-sectional view of a three-layer semiconductor chip fixed by a patch adhesive;

Figure 10 is a schematic view of a top semiconductor chip bonding wire;

Figure 11 is a schematic view showing the sealing of the top semiconductor chip and the bonding wire with a sealant; Figure 12 is a schematic view of a solder ball on a pad on a lower surface of a top package substrate;

Figure 13 is a schematic view showing the top package and the bottom package connected together;

Figure 14 is a schematic illustration of filling a sealant between a top package and a bottom package;

Figure 15 is a schematic view of the solder ball on the bottom surface of the second surface pad;

Figure 16 is a schematic structural view of Embodiment 2;

Figure 17 is a schematic structural view of the third embodiment;

Figure 18 is a schematic structural view of Embodiment 4;

Figure 19 is a schematic view showing the structure of the fifth embodiment.

In the figure: 1 patch glue, 2 semiconductor chip, 3 patch glue, 3a spacer layer, 4 semiconductor chip, 5 patch glue, 5 spacer layer, 6 semiconductor chip, 7 inch disk, 8 bond wire, 9 bond Lead wire, 10 bond wire, 11 top package substrate upper surface pad, 12 top package substrate, 13 top package substrate lower surface pad, 14 sealant, 15 solder ball, 16 underlying package substrate, 17 bottom package substrate second surface Pad, 18 solder balls, 19 bottom package substrate third surface pad, 20 chip adhesive, 21 semiconductor chip, 22 pads, 23 bond wires, 24 sealant, 25 pads, 26 pads, 27 bottom package Substrate first surface pad, 28 solder balls, 29 underfill, 30 semiconductor chip, 31 underlying package substrate third surface pad, 32 copper pillars, 33 solder layer, 34 copper pillars, 35 chip 2 surface pads, 36 Bottom filler, 37 solder ball array, 38 bottom package substrate first surface pad. detailed description

Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

Embodiment 1

2 is a schematic structural view of a first embodiment of the present invention, the package including a top package, a bottom package, an interconnected bottom package and a top package solder ball array, and a sealant between the top package and the bottom package. An inverted trapezoidal recess is provided on the substrate 16 of the bottom package, and the semiconductor chip 21 is fixed to the bottom of the recess by the adhesive 20 . The top package includes at least one semiconductor chip. The top package of FIG. ² includes three semiconductor chips. The three semiconductor chips are stacked in a layered manner by a patch adhesive and a spacer layer, and the spacer layer reserves space for the bonding wires. Pad and top seal on semiconductor chip The pads 11 on the first surface of the mounting substrate 12 are electrically interconnected via bond wire connections. The encapsulant 24 covers over the upper surface of the top package substrate to seal the top packaged semiconductor chip and leads. The electrical interconnection of the top package and the bottom package is achieved by the solder ball array 15. The sealing is achieved by the sealant 14 between the lower surface of the top packaged substrate and the first surface and the third surface of the underlying package substrate. The second surface of the bottom packaged substrate 16 is arranged with an array of solder balls to effect electrical interconnection of the package to the exterior.

The packaging process of this embodiment includes the following steps:

Step A

Preparing a bottom package substrate with a recess; the upper surface of the bottom package substrate 16 is a first surface, the lower surface of the bottom package substrate is a second surface, and the surface of the bottom package substrate is a third surface, the groove position is set On the first surface of the substrate, the groove is disposed at the center of the bottom package substrate, and the bottom of the groove forms a third surface. The substrate may be a PCB board or an FR4 plate or a BT plate, as shown in FIG.

Step B

Pads are prepared on three surfaces of the underlying package substrate; pads 27 are prepared on the first surface of the underlying package substrate 16, pads 17 are prepared on the second surface, and pads 19 are prepared on the third surface. The underlying package substrate includes internal circuitry as well as interconnect pads 27, pads 17, and pads 19.

Step C

The underlying packaged semiconductor chip is mounted in the recess and the wire bonding is completed; the bottom of the groove of the bottom package substrate 16 is fixed to the semiconductor chip 21 by the adhesive 20, and the adhesive 20 is made of organic polymer silver or inorganic polymer silver. The glue is first applied to the bottom of the groove, and then the semiconductor chip 21 is mounted, cured, and the semiconductor chip 21 is fixed above the adhesive layer after cooling, as shown in FIG. The semiconductor chip pad 22 and the recess bottom pad 19 are interconnected by the bonding wire 23, and the groove bottom pad 19 is connected to the second surface pad 17 of the underlying package substrate 16 through the internal circuit of the underlying package substrate 16, thereby realizing the semiconductor chip. 21 connection to an external circuit. Bonding leads can be gold wire, copper wire or aluminum wire, and the bonding process can be thermosonic bonding or Hot press bonding, as shown in Figure 5. The semiconductor chip used in the underlying package includes a logic chip. Step D

Pads are prepared on the upper and lower surfaces of the top package substrate; pads 11 are prepared on the upper surface of the top package substrate 12, pads 13 are prepared on the lower surface of the top package substrate 12, internal circuits are provided inside the substrate, and the substrate can be PCB Or FR4 board or BT board, as shown in Figure 6.

Step E

The top-layer packaged semiconductor chip is stacked on the top package substrate; the top package of the embodiment is a three-layer package, and the semiconductor chip 2 is mounted on the upper surface of the top package substrate 12, and the top surface of the top package substrate 12 is first coated. Sheet glue 1, after placing the semiconductor chip 2, reflowing, and then cooling to room temperature, the chip 2 can be fixed. The patch glue 1 is made of organic polymer silver glue or inorganic polymer silver glue, as shown in FIG. The semiconductor chip 4 is fixed on the upper surface of the semiconductor chip 2 by the adhesive 3 and the spacer 3a, and the adhesive 3 is coated on the upper surface of the semiconductor chip 2, and the spacer is reserved for the bonding wire as shown in FIG. The semiconductor chip 6 is fixed on the upper surface of the semiconductor chip 4 by the SMT 5 and the spacer layer 5a. The area of the SMD 5 is slightly smaller than the upper surface of the semiconductor chip 4 to expose the upper surface pad of the semiconductor chip 4. The spacer layer is a semiconductor chip. 4 The wire reserve space, as shown in Figure 9. The top package semiconductor chip employs a memory chip and selects the number of layers to be stacked as needed.

Step F ·

Performing wire bonding of the top-layer packaged semiconductor chip; bonding the upper surface of the semiconductor chip 2 to the pad 11 on the upper surface of the top package substrate 12 by bonding wires 8, and bonding the semiconductor chip through the bonding wire 9. The upper surface pad 25 of the fourth surface is bonded to the top surface of the top package substrate by the bonding wires 10, and the upper surface pads 26 of the semiconductor chip 6 are bonded to the pads 11 on the upper surface of the top package substrate. As shown in Figure 10. The wire is made of gold wire, copper wire or aluminum wire, and the bonding method is hot pressing or thermosonic bonding.

Step G

Performing a top-level hermetic package; encapsulating the bonding wires 8, 9, 10 with the top layer by the encapsulant 24 The semiconductor chips 2, 4, and 6 are sealed and sealed, and the sealant is located above the upper surface of the top package substrate 12. The sealant is sealed by a plastic sealing process, and the sealant may be an epoxy molding compound, as shown in FIG. Step H

The ball is placed on the pad on the lower surface of the top package substrate, and the connection between the top package and the bottom package is performed; the solder ball 15 is soldered on the lower surface pad 13 of the top package substrate 12, and the solder can be screen printed, electroplated Alternatively, it may be applied by evaporation, and after soldering, a solder ball array 15 may be formed. The solder may be SnAg, Sn, SnAgCu or PbSn, as shown in FIG. The ball 15 on the lower surface of the top package substrate 12 is soldered to the first surface pad 27 of the underlying package substrate 16 to effect electrical interconnection between the top package and the bottom package, as shown in FIG.

Step I

Filling and sealing between the top package and the bottom package, and soldering the ball on the bottom surface of the second surface pad; filling the sealant 24 between the top package and the bottom package, and the sealant 24 is made of epoxy molding, using injection molding The method is filled to protect the solder ball array 15 and the underlying package chip 21 and the leads 23, as shown in FIG. Before soldering the ball on the pad 17, the solder is applied over the pad before the solder ball is formed, by a screen printing process or by evaporation or electroplating. A solder ball is formed after reflow. The solder is made of SnAg, Sn, SnAgCu or PbSn solder as shown in Figure 15.

Embodiment 2

The second embodiment is the same as the first embodiment except that the underlying packaged chip 30 is actively face down, and the boring ball 28 is formed on the active surface, and is soldered by thermocompression bonding, thermoacoustic bonding or soldering. The ball 28 is interconnected with the pads 31 of the third surface of the underlying package substrate 16 to effect electrical signal transfer between the chip 30 and the substrate 16. After the solder ball array 28 is soldered to the pad 31, the underfill is filled at the bottom of the chip 30, and the underfill is composed of a filler of a thermosetting polymer and silicon dioxide, as shown in FIG.

Embodiment 3

The third embodiment is the same as the first embodiment except that after the top package is completed, Solder balls are formed on the lower surface pads 13 of the top package substrate 12 while solder balls are formed on the first surface mount pads 27 of the underlying package. After the solder ball fabrication process is completed, the solder balls on the pad 13 and the solder balls on the pads 27 are connected by reflow by a soldering process to complete the electrical interconnection of the top package and the bottom package. A sealant is then filled between the top package and the bottom package to protect the solder balls 15 and the semiconductor chip 21, as shown in FIG.

Embodiment 4

The fourth embodiment is the same as the first embodiment except that the upper top package substrate 12 is fabricated. Before the subsequent packaging process, a copper pillar 32 is plated on the lower surface pad 13 of the substrate 11, and then a solder layer is deposited. . At the same time, after the underlying package substrate 16 is fabricated, a copper pillar 34 is plated on the first surface pad 27 of the underlying package substrate 16, and then a solder layer is deposited. The solder layer material may be Sn, SnAg, SnAgCu or PbSn. The solder layer on the copper post 32 is bonded to the solder layer on the copper post 34 by a reflow process to complete the electrical interconnection of the top package and the bottom package. Thereafter, the gap between the top package and the bottom package is filled with a sealant as shown in FIG.

Embodiment 5

Embodiment 5 is the same as Embodiment 1, except that the semiconductor chip 2 is of a flip-chip structure, and solder bumps 37 are first formed on the active layer surface pads 35 of the semiconductor chip 2, by thermocompression bonding or thermosonic bonding or The solder bumps 37 are soldered to the pads 38 on the upper surface of the top package substrate in a reflow manner. The bumps 37 3⁄4 material may be gold bumps or Sn, SnAg, SnAgCu or PbSn solder bumps. Thereafter, an underfill 36 is filled between the semiconductor chip 2 and the top package substrate to complete the curing, and the underfill is composed of a thermosetting polymer and a filler of silica, as shown in FIG.

Claims

a stacked semiconductor chip package structure comprising a top package, a bottom package, a solder ball array between the top package and the bottom package, a sealant between the top package and the bottom package, characterized by the underlying package substrate a recess is provided, the upper surface of the bottom package substrate is a first surface, the lower surface of the bottom package substrate is a second surface, the surface of the bottom package substrate recess is a third surface, and the bottom package semiconductor chip is disposed in the recess The first, second, and third surfaces are respectively provided with pads, and the bottom semiconductor chip is connected to the pads on the third surface through the bonding wires, and the top package is laminated on the top package substrate by one or several semiconductor chips. Above the upper surface, the upper surface and the lower surface of the top package substrate are provided with pads. The top layer. The semiconductor chip in the package is connected to the pad on the upper surface of the top package substrate through the bonding wires, and the top package portion is sealed by a sealant. , the top package and the bottom package are connected to the solder ball array through the pad, the top package substrate and the bottom package base Between the sealant filled.

2 . The stacked semiconductor chip package structure according to claim 1 , wherein the recess on the bottom package substrate is an inverted trapezoid, and the semiconductor chip on the bottom package is bonded to the bottom of the groove by a patch adhesive, or The flip chip bonding technique is soldered to the bottom of the recess, and the semiconductor chip is connected to the bottom of the recess by solder balls.

3 . The stacked semiconductor chip package structure according to claim 1 , wherein the top package semiconductor chip has a layered stack structure, and the top semiconductor package between the first semiconductor chip and the substrate can be pasted or flipped The soldering process realizes interconnection, the semiconductor chip and the bonding wire of the top package are sealed by a sealant, the upper surface of the top package substrate is encapsulated by a sealant, and the sealant is an epoxy molding compound.

4. The stacked semiconductor chip package structure according to claim 1, wherein the underlying package substrate and the top package substrate are provided with a circuit for connection.

5. The stacked semiconductor chip package structure according to claim 1, wherein a solder ball array is disposed on the second surface of the bottom package substrate, and the solder ball array is screen printed or plated. The solder is applied by vapor deposition, and an array of solder balls is produced by reflow, and the material thereof is SnAg or Sn or SnAgCu or PbSn.

6. The stacked semiconductor chip package structure according to claim 1, wherein the top package and the bottom package are a single layer or a double layer solder ball array, and the top package and the bottom package are connected by a reflow process. Or depositing a solder layer on the lower surface pad of the top package substrate, depositing a solder layer on the first surface pad of the underlying package substrate, and depositing a solder layer on the first surface pad of the underlying package substrate, the material of the germanium layer being SnAg or Sn or SnAgCu Or PbSn, the top package substrate and the bottom package substrate are connected together by a reflow process to complete electrical interconnection between the top package and the bottom package.

7. A process for stacking a semiconductor chip package structure, comprising the steps of:

A. preparing a bottom package substrate with a groove;

B. preparing a pad on three surfaces of the underlying package substrate;

D. preparing a pad on the upper and lower surfaces of the top package substrate;

G. Perform a top-sealing package;

H. soldering the ball on the pad on the lower surface of the top package substrate to make a connection between the top package and the bottom package;

I. Fill the sealant between the top package and the bottom package, and place the ball on the second surface pad on the bottom.