WO2013040458A1

WO2013040458A1 - Image sensor adaptive column readout structure

Info

Publication number: WO2013040458A1
Application number: PCT/US2012/055575
Authority: WO
Inventors: Jeffrey Jon Zarnowski; Gregory Allen BLUM; Thomas Poonnen; Ketan KARIA; Michael Eugene Joyner
Original assignee: Panavision Imaging
Priority date: 2011-09-14
Filing date: 2012-09-14
Publication date: 2013-03-21

Abstract

A pixel array readout structure is provided. The structure includes first partial amplifier circuitry and a switch fabric electrically connected to the first partial amplifier circuitry. A column of pixels in an array includes a first group of pixels, each pixel having an output transistor connected in a first parallel configuration with the switch fabric, and a second group of pixels, each pixel having an output transistor connected in a second parallel configuration with the switch fabric. A switch fabric control is configured to selectively configure the switch fabric into a plurality of connection states, including (a) a first state connecting the first parallel configuration to the first partial amplifier circuitry without connecting the second parallel configuration, and (b) a second state connecting the second parallel configuration to the first partial amplifier circuit without connecting the first parallel configuration.

Description

IMAGE SENSOR ADAPTIVE COLUMN READOUT STRUCTURE

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The instant application claims priority to provisional application no.

61/534,701 filed September 14, 2011, entitled Image Sensor Adaptive Column Readout Structure, the contents of which are expressly incorporated herein in its entirety.

BACKGROUND OF THE INVENTION

Field of the Invention

[0002] The present invention relates to power reduction in image sensor operation. More specifically, the present invention relates to managing the number of circuits being used to read image sensors as a balance between speed and power consumption.

Discussion of Background Information

[0003] Referring now to Fig. 1, an imager for a row of pixels in a solid state imaging device is shown. Each pixel 12 includes a field effect transistor ("FET") 15 as part of its architecture. The pixel FET 15 is one of a pair of differential input transistors of an operational amplifier 30. The output of each operational amplifier 30 is further processed by subsequent elements, such as a correlated double sampling circuit (CDS) and/or an Analog to Digitial (AtoD) converter. The output of the subsequent elements are fed to a video bus (not shown in Fig. 1) for transmission to other image components.

[0004] Referring now to Fig. 2, the arrangement of Fig. 1 is shown in which several pixels 12 are connected with their FETs 15 in parallel with the remaining components of operational amplifier 30. In combination with a selection signal (not shown) that connects to the gates of the FETs 15, the image data of a particular pixel 12 is selected and processed by the operational amplifier 30. Sequential selection of the individual pixels 12 in a column allow the image data of the entire column to be read out.

[0005] The above architecture is shown in U.S. Patent No. 6,084,229, the disclosure of which is expressly incorporated herein by reference in its entirety.

[0006] The architecture in Figs. 1 and 2 is a "one-way" read-out methodology, in that the column of pixels 12 is read out one at a time by the single operational amplifier 30. Referring now to Fig. 3, a "two-way" methodology employs two operational amplifiers 30a and 30b, one at each end of the column. Unlike the oneway methodology in which the operational amplifier 30 is defined in part by the parallel FETs 15 of all of the pixels in the column, operational amplifiers 30a and 30b are defined by the FETs 15 of half of the pixels 12 in an odd/even arrangement. Thus, the even pixels (shown by select 2, select 4) are connected to operational amplifier 30a, and the odd pixels (shown by select 1, select 3) are connected to operational amplifier 30b (or vice versa). Two video buses 102a and 120b are connected to each operational amplifier 30a and 30b, respectively. In this configuration, each operational amplifier 30a and 30b can simultaneously read a different individual pixel 12, such that the two operational amplifiers can read out the entire column of pixels 12 at twice the speed of the one-way methodology. The independent readouts are sent to independent video buses (not shown).

[0007] A drawback of the above two-way methodology is that speed is related to power, e.g., twice as many operational amplifiers require roughly twice as much power to operate. This higher power consumption may be undesirable if the higher speed operation is not necessary for a particular operation.

[0008] Various attempts have been made to reduce the power consumption with respect to parallel processing of image sensors. U.S. Patent No. 7,619,669 discloses a methodology that shuts down unused video buses to save power, but this can only be done if the readout is slow enough or if only some of the pixels are being readout where pixels are skipped from being readout. U.S. Pat. Publication No. 2009/0300390 discloses a methodology that shuts down unused portions of the camera downstream of the video bus until a request to utilize the sensor is made, as referenced in U.S. Pat. Publication No. 2009/0300390.

SUMMARY OF THE INVENTION

[0009] According to an embodiment of the invention, a pixel array readout structure is provided. The structure includes first partial amplifier circuitry and a switch fabric electrically connected to the first partial amplifier circuitry. A column of pixels in an array includes a first group of pixels, each pixel having an output transistor connected in a first parallel configuration with the switch fabric, and a second group of pixels, each pixel having an output transistor connected in a second parallel configuration with the switch fabric. A switch fabric control is configured to selectively configure the switch fabric into a plurality of connection states, including (a) a first state connecting the first parallel configuration to the first partial amplifier circuitry without connecting the second parallel configuration, and (b) a second state connecting the second parallel configuration to the first partial amplifier circuit without connecting the first parallel configuration. [0010] The above embodiment may have various features. The plurality of connection states may include a state simultaneously connecting both the first and second parallel configurations to the first partial amplifier, and/or another state simultaneously disconnecting both the first and second parallel configurations from the first partial amplifier. Image data from a pixel in the first group can be read out and processed by at least the first partial amplifier circuitry when the switch fabric is in the first state. A select pixel input can be configured to activate individual output transistors of selected pixels, where the select pixel input alternately activates pixels in the first and second groups and the switch fabric switches between the first and second states in substantial synchronization with the select pixel input. When any of the output transistors and the first partial amplifier circuitry are connected through the switch fabric they may form an operational amplifier. The plurality of connection states may include a third state simultaneously connecting both the first and second parallel configurations to the first partial amplifier.

[0011] According to another embodiment of the invention, a pixel array readout structure is provided. The structure includes first and second partial amplifier circuitry, and a first switch fabric electrically connected to the first partial amplifier circuitry. A column of pixels in an array includes a first group of pixels, each pixel having an output transistor connected in a first parallel configuration with the switch fabric, and a second group of pixels, each pixel having an output transistor connected in a second parallel configuration with the switch fabric. A switch fabric control is configured to selectively configure the first switch fabric into a plurality of connection states, including (a) a first state connecting the first parallel configuration to the first partial amplifier circuitry without connecting the second parallel configuration, and (b) a second state connecting the second parallel configuration to the first partial amplifier circuit without connecting the first parallel configuration.

[0012] The above embodiment may have various optional features. There may be a first mode of operation, in which (a) the first and second partial amplifier circuitry are enabled, (b) the switch fabric is in the first state such that first group of pixels is connected to and read out through the first partial amplifier circuitry, and (c) the second group of pixels is read out through the second amplifier circuitry; and a second mode of operation, in which (a) the first partial amplifier circuitry is enabled, (b) the second partial amplifier circuitry is disabled, and (c) the first and second group of pixels are read out through the first partial amplifier circuitry; where the second mode of operation reads out the column of pixels slower and with less power demand than the first mode of operation. The plurality of connection states may include a third state simultaneously connecting both the first and second parallel configurations to the first partial amplifier. In the second mode of operation, the switch fabric may alternately switch between the first and second states to alternatively read out from the first and second groups of pixels. A selection controller may control the first switch fabric. An enablement controller may selectively controls enablement of the first and second partial amplifier circuitry. A first switch fabric may be electrically connected to the second partial amplifier circuitry, and the first and second parallel configurations may be connected to the second switch fabric. Any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, may form an operational amplifier. A second switch fabric may be electrically connected to the second partial amplifier circuitry. The first and second parallel configurations may be connected to the second switch fabric. There may be a first mode of operation, in which (a) the first and second partial amplifier circuitry are enabled, (b) the first switch fabric is in the first state such that the first group of pixels is connected to and read out through the first partial amplifier circuitry, and (c) the second switch fabric is in a state such that the second group of pixels is connected to and read out through the second partial amplifier circuitry.

[0013] According to yet another embodiment of the invention, a pixel array readout structure is provided. The structure includes first and second partial amplifier circuitry and first and second switch fabric electrically connected to the first and second partial amplifier circuitry, respectively. A column of pixels may be in in an array, each pixel having a transistor, wherein the column is separated into at least first and second groups, each group having its transistors connected in parallel with the first and second switch fabrics. A control may be configured to establish the following operating modes: a first operational mode in which the first and second partial amplifier circuitry are both enabled, the first group of pixels connects to and is read out by the first partial amplifier circuitry through the first switch fabric, and the second group of pixels connects and is read out by the second partial amplifier circuitry by the second switch fabric; and a second operational mode in which the first partial amplifier circuitry is enabled, the second partial amplifier circuitry is disabled, and the first and second pixel groups are read out by the first partial amplifier circuitry through the first switch fabric.

[0014] The above embodiment may have various optional features. The second mode of operation may read out the column of pixels slower and with lower power demand than the first mode of operation. Any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, may form an operational amplifier. [0015] According to still yet another embodiment of the invention, a pixel array readout structure, is provided. The structure may include first and second groups of partial amplifier circuitry and first and second switch fabrics electrically connected to the first and second groups of partial amplifier circuitry, respectively. A plurality of columns of image sensors in an array, each pixel having a transistor, wherein each column is separated into at least first and second groups, each group having its transistors connected in parallel with the first and second switch fabrics. There may be a first operational mode in which the first and second groups of partial amplifier circuitry are both enabled, the first group of image sensors in the columns connects to and is read out by the first group of partial amplifier circuitry through the first switch fabric, and the second group of image sensors in the columns connects and is read out by the second group of partial amplifier circuitry by the second switch fabric; and a second operational mode in which only some of the partial amplifier circuits in the first and second groups of partial amplifier circuitry are enabled, the remainder of the first and second groups of partial amplifier circuitry are disabled, and the first and second image sensor groups are read out by enabled partial amplifier circuitry; where the second mode of operation reads out the column of pixels slower and with lower power demand than the first mode of operation. When in the the second mode of operation, the first group of partial amplifier circuitry is enabled, the second group of partial amplifier circuitry is disabled, and the first and second image sensor groups are read out by the first group of partial amplifier circuitry through the first switch fabric. Any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, may form an operational amplifier. [0016] Other exemplary embodiments and advantages of the present invention may be ascertained by reviewing the present disclosure and the accompanying drawings.

BRIEF DISCUSSION OF THE DRAWINGS

[0017] The present invention is further described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of certain embodiments of the present invention, in which like numerals represent like elements throughout the several views of the drawings, and wherein:

[0018] Fig. 1 is a schematic of a prior art image sensor.

[0019] Fig. 2 is a schematic of a prior art image sensor in a column

configuration.

[0020] Fig. 3 is a schematic of a prior art image sensor using multiple amplifiers.

[0021] Fig. 4 is a schematic of an embodiment of the invention.

[0022] Fig. 5 is a schematic of the relationship between a pixel FET and partial amplifier circuitry according to the embodiment of Fig. 4.

[0023] Fig. 6 is a schematic of an embodiment of a selection component for connecting pixels to amplifier components.

[0024] Fig. 7 is a schematic of an embodiment of another selection component for connecting pixels to amplifier components.

[0025] Fig. 8 is a schematic of an embodiment of the invention.

[0026] Fig. 9 is a schematic of an embodiment of the invention.

[0027] Fig. 10 is a schematic of an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION [0028] It is to be understood that the figures and descriptions of embodiments of the present invention have been simplified to illustrate elements/steps relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, other elements/steps found or used in typical presentations, productions, data delivery, computing systems, devices and processes. Those of ordinary skill in the art may recognize that other elements and/or steps are desirable and/or required in implementing embodiments of the present invention. However, because such elements and steps are well known in the art, and do not facilitate a better

understanding of the present invention, a discussion of such elements/steps is not provided herein.

[0029] Embodiments herein disclose a "multi-way" readout methodology by which pixels can be selectively connected to different operational amplifiers based on speed needs. Thus, by way of example, the architecture allows for a selective connection that configures the circuit for multiple readouts for high speed operations, and the option to reduce the number of readouts and thus the power consumption for lower speed operations. Higher speeds, and thus the corresponding higher power consumption, can be employed for those camera operations that require the higher speeds and/or are tolerant of the higher power demand. Lower speeds remain available for those situations in which power savings is more important than speed.

[0030] Referring now to Fig. 4, an embodiment of a circuit 400 is shown. The embodiment includes a column of pixels 412o and 412e (collectively or individually "pixels 412"). As is known in the art, there are multiple columns on a CMOS image sensor, and pixels 412 of the various columns are aligned in rows (see, e.g., Fig. 9). As is known in the art, image data is read out in columns by selection of the individual rows via appropriate signals on the select lines 420. [0031] Each pixel 412 may include a photodiode 410 and a FET 415. The gate of each FET 415 of pixels within a common row connect to a particular signal line 420, which will cause the pixels 412 within that row to read out their image data. However, the invention is not limited to any particular architecture or control of pixel 412.

[0032] The pixels 412 are divided into two or more separate groups. Only two are shown in Fig. 4. For purposes of brevity, discussion herein is limited to two such groups, and Fig. 4 shows two such groups. However, the invention is not so limited, and other numbers of groups may be selected. The number of pixels 412 in a column is preferably equally divided between the groups, but unequal allocation is also possible.

[0033] For the two groups in circuit 400, preferably the pixels 412 in odd numbered rows (e.g., rows 1 and 3 as shown by select 1, select 3) are designated odd pixels 412o, and the pixels in even numbered rows (e.g., rows 2 and 4 as shown by select 2, select 4) are designed even pixels 412e.

[0034] Each of FETs 415 has a source and drain connected to a pair of signal pathways. The source and drain of even pixels 412e connect to even signal pathways 432 and 434, while the source and drain of the odd pixels 412o connect to odd signal pathways 436 and 438. In this configuration, the FETs 415 of odd pixels 412o within a column are connected in parallel, and the FETs 415 of the even pixels 412e in the column are also in parallel. The two parallel configurations are independent of each other.

[0035] The signal pathways 432, 434, 436 and 438 of each column connect to selecting components 442, 444, 446 and 448. Each selecting component 442, 444, 446 and 448 preferably has two pixel side connections to both an odd and even signal pathway. As discussed in more detail below, each of the selecting components has at least the ability to select, under control of a pixel selection signal(s) 465 from a pixel selection control 460, either the odd or even signal pathway. Optionally, any particular selecting component may additionally be able to select both odd and even pathways, or no pathway at all.

[0036] Each of the selecting components connects to circuitry that defines a portion of an operational amplifier 430a on one end of the column, and 430b on the other end of the column. These are generically referred to herein as operational amplifiers 430 unless the sub letter (a, b, c . . . ) is needed for best understanding.

[0037] As discussed in U.S. Patent No. 6,084,229, the individual FETs 415

(when properly connected through the selecting components) combine with partial amplifier circuitry on the other side of the selection components to collectively define an operational amplifier. While the FETs 415 in Fig. 4 (and other figures herein) show FETs 415 as distinct from the triangle symbol that often represents an operational amplifier, this is for artistic purposes only; the triangle represents the portion of circuitry of an operational amplifier minus the FET 415. The operable mechanical relationship is generally as shown in Fig. 5.

[0038] Each operational amplifier 430 receives power and/or a control signal

475 from power source controller 470, which can selectively enable certain operational amplifiers while leaving other operational amplifiers disabled. The method of enabling and disabling - be it via direct power supply control and/or other ON/OFF control methodology - is not critical so long as a disabled operational amplifier consumes less power than when enabled. The invention is not limited to any particular methodology by which the operational amplifiers are enabled and/or disabled. [0039] The various power source control(s) 470 and pixel selection control(s)

460 may be electronic circuitry, electronic computer hardware (such as memory and/or a processor), and/or software. Further, while these are illustrated as separate components, there may be partial or full overlap, or further distribution into additional subcomponents. By way of non-limiting example, a collective microprocessor may be the source of all of the pixel selection control signals. By way of another non- limiting example, switches under microprocessor control may selectively connect operational amplifiers 430 to a power source. The invention is not limited to any particular form of these controllers.

[0040] Operation of the architecture of Fig. 4 will now be discussed with respect to a first column of pixels. It is to be understood the other columns of pixels 412 (see, e.g., Fig. 9) will operate in the same manner based upon the row selection signals 420.

[0041] For a high speed operation, it is desirable to configure the circuit 400 similar to that shown in Fig. 3, i.e., have all operational amplifiers 430 active, and simultaneous read image data from odd and even sets of pixels 412. Power source control 470 thus enables operational amplifiers 430a and 430b, and pixel selection control 460 issues appropriate signals to have the selection components connect the appropriate signal pathways. For example, selecting components 442 and 444 select the odd pathways 436 and 438 for operational amplifier 430a, while selecting components 446 and 448 select the even pathways 432 and 434 for operational amplifier 430b. All the odd pixels 412o are thus in parallel with operational amplifier 430a, and all of the even pixels 430e are in parallel with operational amplifier 430b. This configuration provides a two-way methodology similar to Fig. 2 that can receive two separate row selection signals 420 and read out image data twice as fast as the one-way methodology discussed with respect to Fig. 1.

[0042] Unlike Fig. 2, the circuit 400 is not limited to high speed operation, and can reduce to a lower speed one-way methodology with corresponding lower power requirements. To enable circuit 400 for lower speed operation, only the desired operational amplifiers 430 are enabled; the remaining operational amplifiers 430 are disabled and do not draw any power. The selecting components 442, 444, 446 and 448 are also set (either fixed or changing over time) to connect all of the odd and even pixels 412 within a column to a common operational amplifier.

[0043] For example, one-way methodology circuit 400 only needs one of the two operational amplifiers 430a and 430b. For purposes of brevity and by way of non-limiting example only, operational amplifier 430a can be enabled, while operational amplifier 430b is disabled. The opposite may also be true, and it is to be understood that the invention is not so limited. The various selecting components are set and/or controlled to drive image data traffic to the active operational amplifier 430a.

[0044] The methodology by which the selecting components drive traffic may be based on its architecture and/or its functional limitations. For example, if the selecting components can only select between the odd or even pathways, then the pixel selection control 460 will issue commands to have the selectors switch between the odd and even pathways as needed. For example, when select 1 line - which connected to an odd pixel 412o - is activated, then pixel selection control 460 sets the selecting components 442 and 444 to select the odd pathways 436 and 438 for that reading. When select line 2 - which is connected to an even pixel 412e - is activated, then pixel selection control 460 sets the selecting components 442 and 444 to select the even pathways 432 and 434 for that reading. This selection process continues until all pixels 412 are read. Preferably there is an alternating switch off between odd and even pixel readouts (odd - even - odd - even, etc.), but the invention is not so limited.

[0045] During the above readout, the settings of selecting components 446 and 448 are largely irrelevant, as the corresponding operational amplifier 430b is disabled and cannot process any signal regardless of connection. However, it may be desirable to have that pathway set to an open circuit rather than connect into the disabled operational amplifier. Pixel selection control 460 could thus issue commands so that selecting components 446 and 448 are always set to the opposite of selecting components 442 and 444. Thus by way of example, if selecting components 442 and 444 are connected to the even pathways, then selecting components 446 and 448 would be set to odd pathways, and vice-versa.

[0046] Referring now to Fig. 6, an example of the architecture of a circuit 600 for the selecting components consistent with the above embodiment is shown. In this embodiment, the value of the selecting component signal 460 will determine whether the selecting component is set to the odd signal pathway or the even signal pathway. Pixel selection control 460 will issue appropriate pixel selection signal(s) 465 to control switching to separately read out the odd and even pixels sets.

[0047] In another embodiment, the selecting component is not only able to select between the odd or even pathway, but may also be able to select both pathways and/or neither pathway. This embodiment can operate in the same manner as discussed above in connection with Fig. 6 by switching between odd and even pathways. In the alternative, if the selecting component can select both pathways simultaneously, then this mode may be used to receive image data from both the odd and even pixels 412 without having to switch between them. To the extent that the selecting component has the ability to accept no pathway, this mode could be used to set an open circuit relative to the operational amplifier that is not in use.

[0048] Referring now to Fig. 7, an example of the architecture of a circuit 700 for the selecting components consistent with the above embodiment is shown. In this embodiment, pixel selection signal 465 is two separate signals, and the operation of the circuit 700 is based on the values of those signals. Like circuit 600, circuit 700 can be set to select either the odd or even pathway. In addition, circuit 700 can be set to select both pathways, or neither pathway.

[0049] Circuits 600 and 700 are non-limiting examples of possible selecting components using simple nFET that will work for most CMOS imagers. However, the invention is not so limited. More complex versions using both nFETs and pFETs can be used as well. Any components - whether circuit hardware, electronic computer hardware and/or software - may be used. The selecting components may be separate as shown artistically in Fig. 4, be the same circuit, and/or overlapping in whole or in part with selection control 460. The invention is not limited to any particular architecture or methodology for the selecting component. Further, while each selecting component in the circuit is preferably the same, this need not be the case, as different selecting components could have different architecture,

functionality, and or connections to the remainder of the circuit. The selection architecture by which the various signal pathways connect to the operational amplifiers is referred to herein as switch fabric.

[0050] By way of non-limiting example, the circuit 600 could be used for operational amplifiers 430a, while the same circuit could be used but the inputs are reversed for operational amplifiers 430b. In this configuration, a single control signal 465 would always connect one operational amplifier to the odd pixels 412o and the other operational amplifier to the even pixels.

[0051] Referring now to Fig. 8, another embodiment of a circuit 800 is shown.

In this embodiment, only selecting components 442 and 444 are provided. Instead of selecting components 446 and 448, the odd or even pixels (even pixels in Fig. 8) are directly connected to operational amplifier 430b. Operational amplifier 430b would be enabled during two-way operation for one set of pixels 412, and the selecting components would connect the other set of pixels to operational amplifier 430a. For one way processing, operational amplifier 430b would simply be disabled, and the selecting components 442 and 444 would be operated as discussed above to drive image data from both the odd and even pixels 412 to the operational amplifier 430a.

[0052] Fig. 9 shows an expanded view of an image sensor with multiple columns. Twelve (12) pixels in three (3) columns and four (4) rows are shown, although the invention is not limited to any particular layout size or dimensions. The columns of Fig. 9 each function in the same manner as the single column in Fig. 4 discussed herein. As a further variation (not shown), some or all of the columns could be configured as shown in Fig. 8.

[0053] In one embodiment, power source control 470 enables/disables an entire side of operational amplifiers, such that either the entire upper bank of operational amplifiers 430a or the lower bank of operational amplifiers is enabled or disabled as a block. In another embodiment, smaller groups of operational amplifiers 430, or individual operational amplifiers 430, can be selectively controlled. By way of non-limiting example, in Fig. 9, operational amplifiers 430a in the left and right columns may be enabled along with operational amplifier 430b of the center column, while the remainder are disabled. [0054] The above embodiments are scalable to even higher speed readouts by adding more operational amplifiers 430 and expanding the pathways and selection capabilities of selecting components 440. Thus, by way of non-limiting example, the pixels 412 of a particular column could be separated into three or more sets, connected to a corresponding number of operational amplifiers through selecting components that can switch consistent with the methodologies discussed herein. Thus, three, four or even higher way readouts are possible. Such circuits can similarly reduce their speed and power consumptions from maximum by powering down certain operational amplifiers and using the selection components to direct image data to the remaining active operational amplifiers.

[0055] Referring now to Fig. 10, the above embodiments are scalable downward to a less than one operational amplifier per column. Fig. 10 is similar to two columns of Fig. 4, save that the pathways into the amplifier circuitry are bridged by switches 482 of the switch fabric under control of 460. In this embodiment, only one of the four operational amplifiers is powered. This single operational amplifier services the needs of multiple columns. In this embodiment, every other pixel 412 of a selected row is sampled and then readout is switched to the adjacent column of pixels for sampling. Shutting down half of the column readout circuits requires two samplings per row time and can only be used when the application allows for the slower readout speed that could be accomplished by sampling half of the columns at once. The example shown in FIG. 10 allows for every half of the columns to be shut down to save power. In this manner, every third or every fourth or for every two out of three or three out of four columns or any combination can be shut down.

[0056] Embodiments of the invention can apply to Active Pixel Sensors (APS), such as shown in U.S. Patent No. 5,665,959 and reference "A 250000-pixel image sensor with FET amplification at each pixel for high-speed television cameras", by Andoh, F.; Taketoshi, K.; Yamazaki, J.; Sugawara, M.; Fujita, Y.; Mitani, K.; Matuzawa, Y.; Miyata, K.; Araki, S.; Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC, 1990 IEEE International, 14-16 Feb. 1990

Page(s):212 - 213. APS pixels also typically have two nodes per pixel that need to be brought to the pixel array periphery along the column and the two nodes are the sample node and the load for the source follower.

[0057] It will be apparent to those skilled in the art that modifications and variations may be made in the systems and methods of the present invention without departing from the spirit or scope of the invention. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

What is claimed:

1. A pixel array readout structure, comprising:

first partial amplifier circuitry;

a switch fabric electrically connected to the first partial amplifier circuitry; a column of pixels in an array, comprising:

a first group of pixels, each pixel having an output transistor connected in a first parallel configuration with the switch fabric;

a second group of pixels, each pixel having an output transistor connected in a second parallel configuration with the switch fabric; and a switch fabric control configured to selectively configure the switch fabric into a plurality of connection states, including (a) a first state connecting the first parallel configuration to the first partial amplifier circuitry without connecting the second parallel configuration, and (b) a second state connecting the second parallel configuration to the first partial amplifier circuit without connecting the first parallel configuration.

2. The pixel array readout structure of claim 1, wherein the plurality of connection states include a third state simultaneously connecting both the first and second parallel configurations to the first partial amplifier.

3. The pixel array readout structure of claim 2, wherein the plurality of connection states include a fourth state simultaneously disconnecting both the first and second parallel configurations from the first partial amplifier.

4. The pixel array readout structure of claim 1, wherein the plurality of connection states include another state simultaneously disconnecting both the first and second parallel configurations from the first partial amplifier.

5. The pixel array readout structure of claim 1, wherein image data from a pixel in the first group can be read out and processed by at least the first partial amplifier circuitry when the switch fabric is in the first state.

6. The pixel array readout structure of claim 1, further comprising:

a select pixel input configured to activate individual output transistors of selected pixels;

wherein the select pixel input alternately activates pixels in the first and second groups; and

the switch fabric switches between the first and second states in substantial synchronization with the select pixel input.

7. The pixel array readout structure of claim 1, wherein when any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, form an operational amplifier; and

the plurality of connection states include a third state simultaneously connecting both the first and second parallel configurations to the first partial amplifier.

8. A pixel array readout structure, comprising:

first and second partial amplifier circuitry; a first switch fabric electrically connected to the first partial amplifier circuitry;

a column of pixels in an array, comprising:

a second group of pixels, each pixel having an output transistor connected in a second parallel configuration with the switch fabric;

a switch fabric control configured to selectively configure the first switch fabric into a plurality of connection states, including (a) a first state connecting the first parallel configuration to the first partial amplifier circuitry without connecting the second parallel configuration, and (b) a second state connecting the second parallel configuration to the first partial amplifier circuit without connecting the first parallel configuration.

9. The pixel readout structure of claim 8, further comprising:

a first mode of operation, in which (a) the first and second partial amplifier circuitry are enabled, (b) the switch fabric is in the first state such that first group of pixels is connected to and read out through the first partial amplifier circuitry, and (c) the second group of pixels is read out through the second amplifier circuitry;

a second mode of operation, in which (a) the first partial amplifier circuitry is enabled, (b) the second partial amplifier circuitry is disabled, and (c) the first and second group of pixels are read out through the first partial amplifier circuitry;

wherein the second mode of operation reads out the column of pixels slower and with less power demand than the first mode of operation.

10. The pixel array readout structure of claim 9, wherein the plurality of connection states include a third state simultaneously connecting both the first and second parallel configurations to the first partial amplifier.

11. The pixel array readout structure of claim 9, wherein in the second mode of operation, the switch fabric alternately switches between the first and second states to alternatively read out from the first and second groups of pixels.

12. The pixel array readout structure of claim 8, further comprising a selection controller that controls the first switch fabric.

13. The pixel array readout structure 8, further comprising an enablement controller that selectively controls enablement of the first and second partial amplifier circuitry.

14. The pixel array readout structure of 8, further comprising:

the first switch fabric being electrically connected to the second partial amplifier circuitry;

the first and second parallel configurations being connected to the second switch fabric.

15. The pixel array readout structure of claim 8, wherein when any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, form an operational amplifier.

16. The pixel array readout structure of 8, further comprising: a second switch fabric electrically connected to the second partial amplifier circuitry;

the first and second parallel configurations being connected to the second switch fabric; and

a first mode of operation, in which (a) the first and second partial amplifier circuitry are enabled, (b) the first switch fabric is in the first state such that first group of pixels is connected to and read out through the first partial amplifier circuitry, and (c) the second switch fabric is in a state such that the second group of pixels is connected to and read out through the second partial amplifier circuitry.

17. A pixel array readout structure, comprising:

first and second partial amplifier circuitry;

first and second switch fabric electrically connected to the first and second partial amplifier circuitry, respectively;

a column of pixels in an array, each pixel having a transistor, wherein the column is separated into at least first and second groups, each group having its transistors connected in parallel with the first and second switch fabrics;

a control configured to establish the following operating modes:

a first operational mode in which the first and second partial amplifier circuitry are both enabled, the first group of pixels connects to and is read out by the first partial amplifier circuitry through the first switch fabric, and the second group of pixels connects and is read out by the second partial amplifier circuitry by the second switch fabric;

a second operational mode in which the first partial amplifier circuitry is enabled, the second partial amplifier circuitry is disabled, and the first and second pixel groups are read out by the first partial amplifier circuitry through the first switch fabric.

18. The pixel array readout structure of claim 17, wherein the second mode of operation reads out the column of pixels slower and with lower power demand than the first mode of operation.

19. The pixel array readout structure of claim 17, wherein when any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, form an operational amplifier.

20. A pixel array readout structure, comprising:

first and second groups of partial amplifier circuitry;

first and second switch fabrics electrically connected to the first and second groups of partial amplifier circuitry, respectively;

a plurality of columns of pixels in an array, each pixel having a transistor, wherein each column is separated into at least first and second groups, each group having its transistors connected in parallel with the first and second switch fabrics; a first operational mode in which the first and second groups of partial amplifier circuitry are both enabled, the first group of image sensors in the columns connect to and is read out by the first group of partial amplifier circuitry through the first switch fabric, and the second group of image sensors in the columns connect and is read out by the second group of partial amplifier circuitry by the second switch fabric; a second operational mode in which only some of the partial amplifier circuits in the first and second groups of partial amplifier circuitry are enabled, the remainder of the first and second groups of partial amplifier circuitry are disabled, and the first and second image sensor groups are read out by enabled partial amplifier circuitry. wherein the second mode of operation reads out the column of pixels slower and with lower power demand than the first mode of operation.

21. The pixel array readout structure of 20, wherein in the second mode of operation, the first group of partial amplifier circuitry is enabled, the second group of partial amplifier circuitry is disabled, and the first and second image sensor groups are read out by the first group of partial amplifier circuitry through the first switch fabric.

22. The pixel array readout structure of claim 20, wherein when any of the output transistors and the first partial amplifier circuitry, when connected through the switch fabric, form an operational amplifier.