WO2011060595A1

WO2011060595A1 - Pixel array

Info

Publication number: WO2011060595A1
Application number: PCT/CN2009/075749
Authority: WO
Inventors: 柳智忠
Original assignee: 深超光电（深圳）有限公司
Priority date: 2009-11-18
Filing date: 2009-12-21
Publication date: 2011-05-26
Also published as: CN101710477A; CN101710477B

Abstract

A pixel array includes a plurality of scan lines (210, 210a, 210b) curvilinearly extending along column direction, a plurality of data lines (220, 220a, 220b) extending along row direction and a plurality of pixels (230) connected with the scan lines (210, 210a, 210b) and data lines (220, 220a, 20b). Each pixel (230) arranged in the nth column includes a first sub-pixel (310) and a second sub-pixel (320). The first sub-pixel (310) includes a first transistor (312) and a first pixel electrode (314). The first gate electrode (312b) of the first transistor (312) is connected with the (n+l)th scan line. The first drain electrode (312c) of the first transistor (312) is connected with the first pixel electrode (314). The second sub-pixel (320) includes a second transistor (322) and a second pixel electrode (324). The second gate electrode (322b) of the second transistor (322) is connected with the nth scan line. The second drain electrode (322c) of the second transistor (322) is connected with the second pixel electrode (324). The first source electrode (312d) of the first transistor (312) and the second source electrode (322d) of the second transistor (322) are connected to the same data line of the data lines (220, 220a, 220b).

Description

Pixel array

[Technical Field]

The present invention relates to a display array, and more particularly to a pixel array. 【Background technique】

In general, a flat panel display mainly consists of a display panel and a plurality of driving chips.

(Driver IC) is constructed in which the display panel has an array of pixels, and the pixels in the pixel array are driven by corresponding scan lines and corresponding data lines. In order to make the products of flat-panel displays more popular, the industry is doing a lot of work to reduce costs. In recent years, a data design of a data source chip half-source driver has been proposed, which mainly uses the pixel array. Layout to reduce the amount of data driven chip usage.

FIG. 1A is a schematic diagram of a conventional pixel array. Referring to FIG. 1, in the design of a conventional pixel array 100a, two scan lines 120a are located between two adjacent columns of pixels 130a, 130b, wherein the gates of the active elements 140, 150 in the two pixels 130a, 130b The poles 142, 152 are respectively located on both sides of the scanning line 120a. In the fabrication flow of the active devices 140, 150 having the above architecture, the gates 142, 152 of the active devices 140, 150 and the sources 144, 154, 145, 156 of the active devices 140, 150 are in different masks. Process made. However, when the precision of the machine is insufficient or the alignment error in the process, the relative displacement between the gates 142, 152 of the active elements 140, 150 and the sources 144, 154, the drains 146, 156 may cause The characteristics of the active components 140, 150 deviate from the original design values. At this time, since the gate electrodes 142 and 152 are disposed on both sides of the corresponding scan line 120a, when the gates 142 and 152 of the active elements 140 and 150 are relatively displaced from the drain electrodes 146 and 156, the active elements in the pixels 130a and 130b are disposed. The overlapping areas of the gates 142, 152 and the drains 146, 156 of 140, 150 are all different. If the direction toward the pixel 130b is shifted, the gate-drain parasitic of the pixel 130a on the side of the scan line 120a is parasitic. The capacitance Cgd (parasitic capacitance, Cgd) becomes larger, and the pixel 130b located on the other side of the scan line 120a The gate-drain parasitic capacitance Cgd becomes smaller, resulting in a difference in the gate-drain parasitic capacitance Cgd in the pixels 130a, 130b. As a result, the difference in gate-drain parasitic capacitance Cgd caused by the above-mentioned process error is large, and therefore, the pixel array 100a is liable to cause display brightness unevenness during display.

In order to reduce the difference in gate-drain parasitic capacitance Cgd between pixels, a pixel array structure is proposed in U.S. Patent No. 6,583,777. Referring to FIG. 1B, the pixel array 100b has a plurality of irregularly arranged pixels R, G, B and scan lines 110b and data lines 120b connected to the pixels 1, G, B, respectively. Wherein, the scanning line 110b extends straight along the column direction, and the data line 120b extends straight in the row direction and the scanning lines 110b intersect perpendicularly. However, since the pixels R, G, and B are irregularly arranged, it is easy to cause a phenomenon in which the color expression is significantly insufficient in the display process. In addition, since each of the pixels R, G, and B spans the three scanning lines 110b, the design of the pixel array reduces the aperture ratio, which causes the brightness to be insufficient and the display quality to be poor when applied to the display.

[Summary of the Invention]

The present invention provides a pixel array which can reduce the difference in gate-drain parasitic capacitance and thus contribute to improvement in display quality.

The present invention provides a pixel array including a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The scan lines extend in a zigzag direction along the column direction. The data lines extend in the row direction and intersect the scan lines. The pixels are connected to the scan lines and the data lines, and each pixel arranged in the column includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode, wherein a first gate of the first transistor is connected to the ^^^ scan line, and a first drain and a first pixel of the first transistor Electrode connection. The second sub-pixel includes a second transistor and a second pixel electrode, wherein a second gate of the second transistor is connected to the “scanning line, and a second drain of the second transistor is connected to the second pixel. A first source of the first transistor and a second source of the second transistor are connected to the same data line in the data line. In an embodiment of the invention, the layout patterns of the first transistor and the second transistor are convex upwards based on the corresponding scan lines.

In an embodiment of the invention, the layout pattern of the first transistor and the second transistor is a pattern that protrudes downward based on a corresponding scan line.

In an embodiment of the invention, in the pixels arranged in the same column, the first transistor and the second transistor are located on the same side of the column of pixels.

In an embodiment of the invention, the three sides of each of the first pixel electrodes or each of the second pixel electrodes are surrounded by a corresponding one of the scan lines.

In an embodiment of the invention, each of the scan lines has a waveform on the pixel array. In an embodiment of the invention, each of the scan lines includes a plurality of first wires and a plurality of second wires. The first wire extends in the column direction. The second wire extends in the row direction. The first wire is alternately connected to the second wire.

In an embodiment of the invention, the portion of the second wire is covered by one of the first pixel electrode or the second pixel electrode.

In an embodiment of the invention, the second wire is located between the first sub-pixel and the second sub-pixel in the same pixel and between two adjacent pixels.

In an embodiment of the invention, the length of each of the first wires is substantially greater than or equal to the width of one of the pixel electrodes, and the length of each of the second wires is substantially greater than or equal to the length of one of the pixel electrodes.

In an embodiment of the invention, each of the scan lines further includes a plurality of first branches and a plurality of second branches. The first branch connects the portion of the first wire and extends in the row direction. The second branch connects a portion of the first wire and extends in the row direction. The first branch and the second branch are substantially parallel to the second wire.

In an embodiment of the invention, the portion of the first branch and the portion of the second branch located in the same pixel are covered by the second pixel electrode.

In an embodiment of the invention, the pixels connected to the same data line are distributed on the strip. Both sides of the data line.

In an embodiment of the invention, in the pixels arranged in the same column, a part of the pixels located in the even rows are connected to one of the scanning lines, and a part of the pixels located in the odd rows are connected to the other scanning line.

In an embodiment of the present invention, in each pixel arranged in the column, the first transistor and the second transistor respectively have a first channel layer and a second channel layer, and the first channel layer is located in the first + Above the scan line, the second channel layer is above the “Scan Line”. The first drain is connected to the first pixel electrode from the first channel layer along a first direction, and the second drain is connected to the second pixel electrode from the second channel layer along a second direction, and the first direction is The second direction is the same.

In an embodiment of the invention, in the pixels arranged in the same column, the line connecting the center points of the first and second sub-pixels approaches the same straight line.

In an embodiment of the invention, in each of the pixels, the shape of the first transistor and the shape of the second transistor are in the form of a mirror image on the basis of the data line.

In an embodiment of the invention, the first sub-pixel further includes a first capacitor electrode electrically connected to the first pixel electrode, and the first capacitor electrode and the data line belong to the same film layer and partially overlap the previous scan line. To form a first storage capacitor. The second sub-pixel further includes a second capacitor electrode electrically connected to the second pixel electrode, and the second capacitor electrode and the data line are in the same film layer and partially overlap with the previous scan line to form a second storage capacitor.

Based on the above, the pixel array of the present invention designs the scan lines in a zigzag layout manner, and the first sub-pixels and the second sub-pixels connected to the same data line are disposed on both sides of the data line. At the same time, the first gate of the first transistor located in the same pixel is connected to the (n+1)th scan line, and the second gate of the second transistor is connected to the _nth scan line. Therefore, the design of the pixel array of the present invention can greatly reduce the number of layouts of the data lines, thereby reducing the manufacturing cost, and effectively increasing the aperture ratio to significantly improve the brightness of the screen display, and can also improve the color performance of the display. In addition, since the extending directions of the pixel electrodes corresponding to the drains of the transistors are the same, the gate-drain parasitic power in the entire pixel is obtained when there is a registration deviation between the layers on the transistor. The difference in capacitance (Cgd) is small. In this way, when the pixel array of the present invention is applied to a display, it helps to improve the display uniformity of the display, thereby avoiding the problem of unevenness of brightness caused by flicker.

The above described features and advantages of the present invention will be more apparent from the following description of the appended claims.

[Description of the Drawings]

1A is a schematic diagram of a conventional pixel array.

FIG. 1B is a schematic diagram of another conventional pixel array.

2A is a schematic diagram of a pixel array in accordance with an embodiment of the present invention.

2B is a schematic diagram of a scan line of the pixel array of FIG. 2A.

2C is a schematic diagram of a pixel array in accordance with another embodiment of the present invention.

2D is a schematic diagram of a pixel array according to still another embodiment of the present invention.

3A is a schematic diagram of a pixel array in accordance with an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view taken along line A-A of Fig. 3A, and line B-B.

FIG. 3C is a schematic diagram of a pixel array according to another embodiment of the present invention.

【detailed description】

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2A is a schematic diagram of a pixel array according to an embodiment of the invention. 2B is a schematic diagram of scan lines of the pixel array of FIG. 2A. Referring to FIG. 2A and FIG. 2B simultaneously, in the embodiment, the pixel array 200a includes a plurality of scan lines 210, a plurality of data lines 220, and a plurality of pixels 230. For convenience of explanation, the pixel array 200a has a column direction L1 and a row direction L2, and the column direction L1 is substantially orthogonal to the "" direction L2.

As shown in FIG. 2B, the scan line 210 of the present embodiment extends substantially in a meandering manner along the column direction L1, and for convenience of description, the scan line 210 will be composed of a plurality of first scan lines 210a and a plurality of strips. The configuration of the second scanning line 210b will be described as an example. In other words, the scanning lines 210 extend macroscopically in parallel with each other in the column direction L1. Microscopically, the scanning lines 210 extend substantially in a single waveform on the substrate.

More specifically, in this embodiment, each of the first scan lines 210a (or the second scan lines 210b) includes a plurality of first wires 212, a plurality of second wires 214, a plurality of first branches 216, and a plurality of Second branch 218. The first wire 212 extends substantially along the column direction L1, and the second wire 214 extends substantially along the row direction L2. In particular, the first wire 212 and the second wire 214 are alternately connected such that the first scan line 210a is substantially square. Of course, in other embodiments, the first scan line 210a may also have a sawtooth shape or an S-shaped shape. The first branch 216 connects a portion of the first wire 212 and extends substantially along the row direction L2. The second branch 218 connects a portion of the first wire 212 and extends along the row direction L2. The first branch 216 and the second branch 218 are substantially parallel to the second wire 214, and the first scan line 210a is connected to a first branch 216 and a first segment on each of the first wires 212 adjacent to the second scan line 210b. The two branches 218 are such that the first branch 216 of the first scan line 210a and the second wire 214 of the second scan line 210b are substantially on both sides of the data line. Therefore, each sub-pixel adjacent to the data line can further achieve the effect of avoiding lateral light leakage through the first branch 216 and the second branch 218.

Referring to FIG. 2A and FIG. 2B again, the data line 220 in this embodiment extends substantially along the row direction L2 and intersects the first scan line 210a and the second scan line 210b to define a plurality of pixel regions. In this embodiment, the data line 220 intersects with the first scan line 210a and the second scan line 210b but is not electrically connected. Each of the pixels 230 in the pixel array 200a is connected to the corresponding first scan line 210a, the second scan line 210b, and the data line 220, and each pixel 230 arranged in the nth column includes a first sub-pixel 310 and a first Two sub-pixels 320. The first sub-pixel 310 includes a first transistor 312 and a first pixel electrode 314. The first transistor 312 has a first channel layer 312a, a first gate 312b, a first drain 312c, and a first source. Pole 312d. The first channel layer 312a is located above the (n+1)th scan line 210 (ie, the second scan line 210b), and the first gate 312b and the (n+1)th scan line 210 (ie, the second scan) Line 210b) is connected. The first drain 3 12c is connected to the first pixel electrode 314, and the first drain 3 12c is connected to the first pixel electrode 314 from the first channel layer 312a along a first direction D1, that is, the first pixel electrode 3 14 corresponds to the (n+1)th scan line 210 (i.e., the second scan line 210b). The three sides of the first pixel electrode 314 are surrounded by the corresponding previous scan line 210 (i.e., the first scan line 210a).

On the other hand, the second sub-pixel 320 includes a second transistor 322 and a second pixel electrode 324, wherein the second transistor 322 has a second channel layer 322a, a second gate 322b, and a second drain 322c. A second source 322d. The second channel layer 322a is located above the nth scan line 210 (i.e., the first scan line 210a), and the second gate 322b is connected to the nth scan line 210 (i.e., the first scan line 210a). The second drain 322c is connected to the second pixel electrode 324, and the second drain 322c is connected to the second pixel electrode 324 from the second channel layer 322a along a second direction D2, that is, the second pixel electrode 324 corresponds to the nth A scan line 210 (ie, the first scan line 210a). In particular, the first direction D1 is the same as the second direction D2. That is, the first direction D 1 is substantially parallel to the second direction D2. The three sides of the second pixel electrode 324 are surrounded by corresponding corresponding upper scan lines (not shown).

Specifically, the layout patterns of the first transistor 312 and the second transistor 322 are in a shape that protrudes upward corresponding to the reference of the second scan line 210b and the first scan line 210a, respectively. Therefore, in this embodiment, The pixels of the n columns are located in the area surrounded by the nth scan line 210, and are located in the first sub-pixel 310 and the second sub-pixel 320 of the nth column, and the first gate 3 12b and the (n+ l )th scan The line 210 (i.e., the second scan line 210b) is connected, and the second gate 322b is connected to the nth scan line 210 (i.e., the first scan line 210a), in other words, the scan connected to the first gate 312b. The line 210 is the next one of the scan lines 210 connected to the second gate 322b, and since n is an arbitrary positive integer, those skilled in the art may also refer to the first gate 3 12b being connected to the nth scan line 210. The second gate 322b is connected to the (n-1)th scanning line 210, and the present invention is not limited thereto. In other embodiments, referring to FIG. 2C, the layout of the pixel array 200b, the first transistor 312, and the second transistor 322 may be corresponding to the second scan line 210b. A pattern that protrudes downward from the reference of the first scan line 210a. That is, the pixel of the nth column is located in the area surrounded by the nth scan line 210. In the nth column of pixels, the first gate 312b' is connected to the nth scan line 210, and the second gate The pole 322b is connected to the (n-1)th scan line 210. In other words, the scan line 210 connected to the first gate 312b is also the scan line 210 connected to the second gate 322b'. The next one, and since n is an arbitrary positive integer, those skilled in the art may also refer to the first gate 312b being connected to the nth scan line 210, and the second gate 322b and the (n+1)th scan. The line 210 is connected, and the present invention is not limited thereto. In addition, those skilled in the art are aware of the directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left J, "right", etc. Direction. Therefore, the directional terminology used is for the purpose of illustration and not limitation. In other words, if the illustration of FIG. 2A is rotated by 180 degrees, the layout patterns of the first transistor 312 and the second transistor 322 can be obtained to correspond to the reference directions of the second scan line 210b and the first scan line 210a, respectively. For the shape of the lower bulge, please refer to Figure 2D. Moreover, in the present example, the first source 312d of the first transistor 312 and the second source 322d of the second transistor 322 are connected to the same data line 220a in the data line 220.

Specifically, as shown in FIG. 2A , the second wire 214 is located between the first sub-pixel 310 and the second sub-pixel 320 in the same pixel 230 and between the adjacent two pixels 230 . The length of each of the first wires 212 is substantially greater than or equal to the width of the first pixel electrode 314 (or the second pixel electrode 324), and the length of each of the second wires 214 is substantially equal to or greater than the first pixel electrode 314 (or The length of the second pixel electrode 324). In addition, the data line 220a of the embodiment substantially intersects the first scan line 210a and the second scan line 210b, wherein the first sub-pixel 310 and the second sub-pixel 320 connected to the same data line 220a are distributed on the data line. On both sides of 220a, and the first sub-pixel 310 and the second sub-pixel 320 are substantially in the same column. In the pixel 230 in which the present example is arranged in the same column, the partial pixels 230 located in the even rows are connected to one of the scanning lines 210, and the partial pixels 230 located in the odd rows are connected to the other scanning line 210. That is, the second sub-pixel 320 located in the even row is electrically connected to the first scan line 210a, and the first sub-pixel 310 located in the odd row is electrically connected to the second scan line 210b. In addition, the first gate 312b of the first transistor 3 12 is substantially connected to the second scan line 210b, and the second gate 322b of the second transistor 322 is substantially connected to the first scan line 210a. In the pixels 230 arranged in the same column, the first transistor 312 and the second transistor 322 are located on the same side of the column pixel 230, and in each pixel 230, the first transistor 312 is in the form of the second transistor 322 horizontally flipped by 180 degrees. . That is, the shape of the first transistor 312 and the shape of the second transistor 322 are mirrored and slightly misaligned with the data line 220a as a reference line. In other words, the layout of the first transistor 312 and the second transistor 322 are substantially the same, that is, the shapes of the first channel layer 312a and the second channel layer 322a, and the first drain 312c and the second drain 322c correspond to each other. The extending direction of the one pixel electrode 314 and the second pixel electrode 324 and the shapes of the first source electrode 312d and the second source electrode 322d are the same. In addition, the first pixel electrode 314 and the second pixel electrode 324 cover a portion of the second wire 214 , wherein the second pixel electrode 324 also covers a portion of the first branch 216 and a portion of the second branch 218 located in the same pixel 230 .

Further, in the present embodiment, in the pixels 230 arranged in the same column, the line connecting the center points of the first sub-pixel 310 and the second sub-pixel 320 approaches the same straight line. Specifically, in the pixel 230 formed by the first sub-pixel 310 and the second sub-pixel 320, the first sub-pixel 310 located in the odd-numbered rows and the second sub-pixel 320 located in the even-numbered rows are not completely aligned. The line connecting the center point of the first sub-pixel 310 is T1, and the line connecting the center point of the second sub-pixel 320 is T2, wherein the offset degree S of the connection line T1 and the connection line T2 is the first sub-pixel 310 or the The two sub-pixels 320 are 3% to 50% of the length. Since the degree of offset S is not large, the first sub-pixel 310 and the second sub-pixel 320 can be counted in the same column.

It should be noted that, in this embodiment, the extending direction of the first drain electrode 312c to the corresponding first pixel electrode 314 is the same as the extending direction of the second drain electrode 322c to the corresponding second pixel electrode 324. Therefore, even when a misalignment occurs between different layers when making a transistor or a slight offset due to the tolerance of the precision of the machine, the variation of the gate-drain parasitic capacitance (Cgd) can be relatively uniform. The more consistent change means that the gate-drain parasitic capacitance (Cgd) of each pixel 230 on the pixel array 200a will become larger or smaller at the same time. As a result, two adjacent pixels 230 The difference in brightness between the two is small, and when the pixel array 200a is applied to a display (not shown), it helps to improve the display uniformity of the display, thereby avoiding the problem of flicker and uneven brightness.

In addition, since the pixel array 200a of the present embodiment designs the scan line 210 in a zigzag layout manner, the first sub-pixel 310 and the second sub-pixel 320 connected to the same data line 220a are disposed on the data line 220a. On both sides. At the same time, the first gate 312b of the first transistor 312 located in the same pixel 230 is connected to the second scan line 210b, and the second gate 322b of the second transistor 322 is connected to the first scan line 210a. In addition to greatly reducing the number of layouts of the data lines 220, this design can also effectively increase the aperture ratio, so that the brightness of the screen display is significantly improved. In addition, the pixels 230 of the embodiment are basically located on the same column, and each of the pixels 230 composed of the first sub-pixel 310 and the second sub-pixel 320 is substantially rectangular, and thus compared with the existing pixels. For the array 100, the embodiment can effectively improve the color rendering capability of the picture.

FIG. 3A is a schematic diagram of a pixel array according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along line A-A of Fig. 3A, and line BB'. Referring to FIG. 3A and FIG. 3B simultaneously, the pixel array 200c of the present embodiment is similar to the above-described pixel array 200a. In the pixel array 200c of the present embodiment, the gap D between adjacent pixels is reduced, so that in the same layout space, since the gap D between adjacent pixels becomes smaller, the area of the pixel can be increased. In turn, the aperture ratio of the pixel is increased. In addition, in the high aperture ratio pixel array 200c of the present embodiment, the dielectric layer 240 having high coverage characteristics is also over the first transistor 312" and the second transistor 322", and the dielectric layer 240 can also be regarded as a The flat layer is overcoated, so the layout of the first pixel electrode 314" and the second pixel electrode 324" may further extend above the corresponding scan line 210 to further increase the aperture ratio of the pixel. It is to be noted that in the present embodiment, the first pixel electrode 314" and the second pixel electrode 324" only show the nth scanning line and the (n+1)th scanning line. However, in other embodiments, referring to FIG. 3C, the first pixel electrode 314'" and the second pixel electrode 324" may also cover the entire first sub-pixel 310"' and the second sub-pixel 320"'.

In order to further enhance the storage capacitance of the first sub-pixel 310" and the second sub-pixel 320", A sub-pixel 310 further includes a first capacitor electrode 316, and the second sub-pixel 320 further includes a second capacitor electrode 326. In detail, the first capacitor electrode 316 is electrically connected to the first pixel electrode 314 ′′, and the first capacitor electrode 316 partially overlaps with the previous scan line 210 (ie, the nth scan line 210 ) to form a first storage capacitor. Cl, that is, the lower electrode of the first storage capacitor C1 is a portion of the upper scan line 210, the upper electrode is the first capacitor electrode 316, and the upper electrode and the data line 220 belong to the same film layer. The second capacitor electrode 326 is electrically connected. a second pixel electrode 324", and the second capacitor electrode 326 partially overlaps with the previous scan line 210 (ie, the (n-1)th scan line 210) to form a second storage capacitor C2, that is, the second storage capacitor C2. The electrode is a portion of the upper scan line 210, the upper electrode is the second capacitor electrode 326, and the upper electrode and the data line 220 are in the same film layer. In detail, referring to FIG. 3A and FIG. 3B, in the first sub-pixel 310" in the nth column, the first pixel electrode 314" passes through the first contact window 242 of the dielectric layer 240 and the first transistor. 312" is electrically connected and electrically connected to the first capacitor electrode 316 through the second contact window 244 of the dielectric layer 240. In actual operation, an opening voltage level is applied to the (n+1)th a scan line 210 (ie, a second scan line 210b) to turn on the first transistor 312", and then input a data voltage from the data line 220a, the data voltage is passed through the first transistor 312 that is turned on, and the first of the dielectric layer 240 The contact window 242 is transferred to the first pixel electrode 314". And the first pixel electrode 314" having the data voltage transmits the data voltage to the first capacitor electrode 316 through the second contact window 244 of the dielectric layer 240. So that the first pixel electrode 314" is equipotential to the first capacitor electrode 316, so the (n+1)th scan line 210 (ie, the second scan line 210b), the first capacitor electrode 316, and the (n+1)th a gate insulating layer 31 between the strip scan line 210 (ie, the second scan line 210b) and the first capacitor electrode 316 8 collectively constitutes a first storage capacitor C1 of the first sub-pixel 310", and the first storage capacitor C1 is used to stabilize the data voltage of the first pixel electrode 314" during the first transistor 312" off, thereby improving display quality. In this way, the first sub-pixel 310" can have both a high aperture ratio and a high storage capacitance value. Similarly, the operation mechanism of the second sub-pixel 320" is similar to that of the first sub-pixel 310", and will not be described again.

In summary, the pixel array of the present invention designs the scan lines in a zigzag layout manner, and the first sub-pixels and the second sub-pixels connected to the same data line are disposed on both sides of the data line. At the same time, the first gate of the first transistor located in the same pixel is connected to the (n+1)th scan line, and the second gate of the second transistor is connected to the _nth scan line. Therefore, in addition to substantially reducing the number of layouts of the data lines, the pixel array of the present invention can effectively increase the aperture ratio to significantly improve the brightness of the screen display, and can also improve the color performance of the display. In addition, since the drains of the transistors extend to the corresponding pixel electrodes, the difference in gate-drain parasitic capacitance (Cgd) in the overall pixel is obtained when there is a registration deviation between the layers on the transistor. small. In this way, when the pixel array of the present invention is applied to a display, it helps to improve the display uniformity of the display, thereby avoiding the problem of unevenness of brightness caused by flicker.

In the above-described embodiments, the present invention has been exemplarily described, and various modifications of the present invention can be made without departing from the spirit and scope of the invention.

Claims

Rights request

What is claimed is: 1 . A pixel array, wherein the pixel array comprises:

a plurality of scanning lines extending in a zigzag direction along the column direction;

a plurality of data lines extending along the row direction and intersecting the plurality of scan lines;

a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, and each of the pixels arranged in the nth column includes:

a first sub-pixel includes a first transistor and a first pixel electrode, wherein a first gate of the first transistor is connected to the (n+1)th scan line, and a first one of the first transistor a drain connected to the first pixel electrode;

a second sub-pixel includes a second transistor and a second pixel electrode, wherein a second gate of the second transistor is coupled to the “scanning line, and a second drain of the second transistor The two pixel electrodes are connected, a first source of the first transistor and a second source of the second transistor are connected to the same one of the plurality of data lines.

The pixel array according to claim 1, wherein a layout pattern of the first transistor and the second transistor is upwardly convex based on a corresponding scan line.

The pixel array according to claim 1, wherein a layout pattern of the first transistor and the second transistor is a downward convex shape based on a corresponding scan line.

4. The pixel array of claim 1, wherein the plurality of first transistors and the plurality of second transistors are located on a same side of the column of pixels in pixels arranged in the same column.

The pixel array according to claim 1, wherein three sides of each of the first pixel electrodes or each of the second pixel electrodes are surrounded by a corresponding one of the scanning lines.

6. The pixel array of claim 5, wherein each of the scan lines has a one-sided waveform on the pixel array.

7. The pixel array of claim 1, wherein each of the scan lines comprises:

a plurality of first wires extending along the column direction; a plurality of second wires extending along the row direction,

The plurality of first wires are alternately connected to the plurality of second wires.

The pixel array according to claim 7, wherein a portion of the plurality of second wires are covered by one of the first pixel electrode or the second pixel electrode.

9. The pixel array of claim 7, wherein the plurality of second wires are located between the first sub-pixel and the second sub-pixel in the same pixel and between adjacent two pixels.

10. The pixel array of claim 7, wherein each of the first wires has a length substantially greater than or equal to a width of one of the pixel electrodes, and each of the second wires has a length substantially greater than a length of one of the pixel electrodes.

The pixel array according to claim 7, wherein each of the scan lines further comprises: a plurality of first branches connecting the plurality of first wires and extending along the row direction; and a plurality of second branches, connecting And a portion of the plurality of first wires extending along the row direction, wherein the plurality of first branches and the plurality of second branches are substantially parallel to the plurality of second wires.

12. The pixel array of claim 11, wherein the portion of the first branch and the portion of the second branch are covered by the second pixel electrode.

The pixel array according to claim 1, wherein pixels connected to the same data line are distributed on both sides of the data line.

The pixel array according to claim 1, wherein among the pixels arranged in the same column, the partial pixels located in the even rows are connected to one of the scanning lines, and the partial pixels located in the odd rows are connected to the other scanning line.

The pixel array of claim 1 , wherein in each of the pixels arranged in the nth column, the first transistor and the second transistor respectively have a first channel layer and a second channel layer, the first a channel layer is located above the +7th scan line, and the second channel layer is located above the first scan line, the first drain is connected to the first pixel electrode from the first channel layer along a first direction, The second drain is connected to the second pixel electrode from the second channel layer along a second direction. And the first direction is the same as the second direction.

The pixel array according to claim 1, wherein in the pixels arranged in the same column, the lines connecting the center points of the plurality of first and second sub-pixels are close to the same straight line.

The pixel array according to claim 1, wherein in each of the pixels, a shape of the first transistor and a shape of the second transistor are in a form of a mirror image based on the data line.

The pixel array of claim 1 , wherein the first sub-pixel further comprises a first capacitor electrode electrically connected to the first pixel electrode, and the first capacitor electrode and the data line are in the same film layer And partially overlapping with the previous scan line to form a first storage capacitor, and the second sub-pixel further includes a second capacitor electrode electrically connected to the second pixel electrode, and the second capacitor electrode and the data line are The same film layer partially overlaps with the previous scan line to form a second storage capacitor.