WO2010132941A1

WO2010132941A1 - Universal time-based extensions for instrumentation

Info

Publication number: WO2010132941A1
Application number: PCT/AU2010/000602
Authority: WO
Inventors: Peter Graham Foster
Original assignee: Chronologic Pty. Ltd.
Priority date: 2009-05-20
Filing date: 2010-05-20
Publication date: 2010-11-25
Also published as: EP2432754B1; EP2433194B1; CN102439532A; WO2010132943A1; EP2800004A1; JP5636043B2; JP2014197421A; EP2433196B1; US8984321B2; US20140229756A1; AU2010251772A1; WO2010132939A1; EP2433196A1; EP2433195A4; EP2433197A4; US20150039791A1; US20120066418A1; EP2433193A1; EP2433193A4; CA2761363A1

Abstract

A method of controlling a plurality of event driven instruments as a single time- controlled synchronous virtual instrument, the method comprising: attaching the plurality of instruments to a common communications network; attaching a control device to the common communication network, the control device containing a local clock, the local clock maintaining a notion of real time; providing the control device with a plurality of trigger times, each of the trigger times associated with one or more of the instruments; and transmitting an event signal to those of the instruments associated with a respective one of the trigger times when the notion of real time of the control device matches the respective trigger time.

Description

UNIVERSAL TIME-BASED EXTENSIONS FOR INSTRUMENTATION

RELATED APPLICATION

This application is based on and claims the benefit of the filing date of US application no. 61/179904 filed 20 May 2009, the content of which as filed is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for providing a synchronization and timing system, with connectivity based on revision three of the Universal Serial Bus (USB) architecture (or USB 3.0), of particular but by no means exclusive use in providing clocks, data acquisition and automation and control of test and measurement equipment, instrumentation interfaces and process control equipment, synchronized to an essentially arbitrary degree in either a local environment or in a distributed scheme.

BACKGROUND OF THE INVENTION

The USB specification up to and including revision 2.0 was intended to facilitate the interoperation of devices from different vendors in an open architecture. USB 2.0 data is encoded using differential signalling (viz. in which two wires transfer the information) in the form of the difference between the signal levels of those two wires. The USB 2.0 specification is intended as an enhancement to the PC architecture, spanning portable, desktop and home environments.

However, USB was user focussed so the USB 2.0 specification lacked a mechanism for synchronising devices to any great precision. Several proposals attempted to address this and other deficiencies. For example, US Patent No. 6,343,364 (Leydier et al.) discloses an example of frequency locking to USB traffic, which is directed toward a smart card reader. This document teaches a local, free-running clock that is compared to USB SYNC and packet ID streams; its period is updated to match this frequency, resulting in a local clock with a nominal frequency of 1.5 MHz. This provides a degree of synchronization sufficient to read smart card information into a host PC but, as this approach is directed to a smart card reader, inter-device synchronization is not addressed.

WO 2007/092997 (Foster et al.) discloses a synchronized USB device that allows the generation of accurate clock frequencies on board the USB device regardless of the accuracy of the clock in the Host PC. The USB SOF packet is decoded by the LJSB device, and treated as a clock carrier signal instead of acting as a clock reference.

The carrier signal, once decoded from the USB traffic, is combined with a scaling factor to generate synchronization information and hence to synthesize a local clock signal with precise control of the clock frequency. In this way, the frequency of the local clock signal can be more accurate than the somewhat ambiguous frequency of the carrier signal.

This arrangement is said to be able to produce a local clock signal to arbitrarily high frequencies, such as a clock frequency of tens of megahertz, and thus to ensure that the local clock of each device connected to a given USB is synchronized in frequency. US Application No. 10/620,769 also teaches a method and apparatus to further synchronize multiple local clocks in phase by measurement of signal propagation time from the host to each device and provision of clock phase compensation on each of the USB devices.

US Patent Application 12/279,328 (Foster et. al.) teaches synchronisation of the local clocks of a plurality of USB devices to a timebase received from another interface. In one embodiment, a USB device contains a local clock that is synchronised to an externally provided time signature across Ethernet using the IEEE-1588 protocol. In yet another embodiment the USB device's clock is synchronised to a timebase derived from a Global Positioning System (GPS) synchronised clock.

All of the above systems work within the bounds of conventional USB 2.0 and as such are limited in several areas. USB 2.0 is limited in range by the device response timeout. This is the window of time that the USB Host Controller allocates for receipt of a signal from a given USB device in response to a request from said USB Host Controller. The physical reach of USB 2.0 is therefore approximately 25 m.

The USB 3.0 specification was released in November 2008 and is also focussed on consumer applications. The USB 3.0 specification makes significant changes to the architecture of USB. In particular, the background art synchronisation schemes discussed above will not work with the new 5 Gb/s protocol (termed 'SuperSpeed USB') because it does away with the broadcast mechanism for SOF packets.

USB 3.0 defines two parallel and independent USB busses on the same connection cable. Firstly, the USB 2.0 bus remains unchanged (for backward compatibility) and offers Low Speed (1.5 Mb/s), Full Speed (12 Mb/s) and High Speed (480 Mb/s) protocols. The second bus - for 5 Gb/s traffic - provides the SuperSpeed USB. These busses operate independently, except that operation of the busses to a given USB device is mutually exclusive. That is, if a SuperSpeed connection is possible, then the USB 2.0 bus in disconnected to that device.

The dual-bus architecture of USB 3.0 is depicted schematically at 10 in figure 1. Personal Computer 12, containing USB Host Controller 14, is connected to USB 3.0 Hub 16 by first USB 3.0-compliant cable 18; USB 3.0 device 20 is connected to a downstream port 22 of USB 3.0 Hub 16 by second USB 3.0- compliant cable 24.

USB Host Controller 14 contains both a USB 2.0 Host 26 and a SuperSpeed Host 28. These two hosts 26, 28 are independent of one another, and each host 26, 28 is capable of connecting up to 127 devices (including hubs). USB 3.0-compliant cables are compound cables, containing a USB 2.0-compliant cable and a series of shielded conductors capable of transmitting SuperSpeed signals. Hence, USB 3.0-compliant cable 18 comprises USB 2.0-compliant cable 30 and shielded conductors 32.

USB 3.0 Hub 16 contains both a USB 2.0 Hub function 34 and a SuperSpeed Hub function 36, each connected directly to its respective Host 26, 28 by compound cable 18. USB 3.0 device 20 contains both a USB 2.0 device function 38 and a SuperSpeed device function 40, each connected back to its respective hub function 34, 36 of USB 3.0 Hub 16 by compound cable 24.

At enumeration of USB 3.0 device 20, SuperSpeed Host 28 checks for the presence of a SuperSpeed device function (40). If a SuperSpeed device is found, then a connection is established. If a SuperSpeed device is not found (as in the case where only a USB 2.0 device is connected to port 22), then the USB 2.0 Host 26 checks for the presence of a USB 2.0 device function (38) at - A - device 20. Once the Host Controller 14 determines which device function is connected, it tells the USB 3.0 Hub 16 to only enable communication for downstream port 22 corresponding to whether the USB 2.0 device function 38 or SuperSpeed device function 40 is attached. This means that only one of the two parallel busses is in operation at any one time to an end device such as USB 3.0 device 20.

Furthermore, SuperSpeed USB has a different architecture from that of the USB 2.0 bus. Very high speed communication systems consume large amounts of power owing to high bit rates. A design requirement of SuperSpeed USB was lower power consumption, to extend the battery life of user devices. This has resulted in a change from the previous broadcast design of the USB 2.0: SuperSpeed is not a broadcast bus, but rather directs communication packets to a specific node in the system and shuts down communication on idle links.

This significantly affects any extension of the synchronisation schemes of, for example, US Patent Application No. 12/279,328, whose method and apparatus for synchronising devices is based on a broadcast clock carrier signal that is delivered to each device on the bus, which is unsuitable in SuperSpeed USB.

A SuperSpeed Hub function acts as a device to the host (or upstream port) and as a host to the device (or downstream port). This means that the SuperSpeed Hub function acts to buffer and schedule transactions on its downstream ports rather than merely acting as a repeater. Similarly, the SuperSpeed Hub function does so with scheduling transmissions on the upstream port. A heavily burdened Hub function can therefore add significant non-deterministic delays in packet transmission through the system. This also precludes the use of USB 2.0 synchronisation schemes such as that of US Patent Application No. 12/279,328 from operating on SuperSpeed USB.

The crude Isochronous synchronisation of USB 2.0 has been significantly improved in the USB 3.0 specification. Opening an Isochronous communication pipe between a Host Controller and a USB device guarantees a fixed bandwidth allocation in each Service Interval for the communication pipe. The Isochronous Protocol of USB 3.0 contains a so-called Isochronous Timestamp Packet (ITP), which is sent at somewhat regular intervals to each lsochronous Endpoint and which contains a timestamp of the beginning of ITP transmission by the USB Host Physical Layer (Phy) in the time domain of the Host Controller. The Isochronous Timestamp Packet is accurate to about 25 ns. SuperSpeed USB shuts down idle links to conserve power, but links must be active in order to receive an Isochronous Timestamp Packet. The Host Controller must therefore guarantee that all links to a device are in full active mode (termed power state UO) before transmission of the Isochronous Timestamp Packet.

Unfortunately the Isochronous Timestamp packet can be delayed in propagation down the USB network. USB 3.0 also does not provide a way of determining the propagation time of packets in SuperSpeed USB and hence no way of accurately knowing the phase relationship between time domains on different USB devices. Phase differences of several hundred nanoseconds are expected to be a best case scenario with SuperSpeed USB making it impractical for instrumentation or other precision timing requirements.

US Patent No. 5,566,180 (Eidson et al.) discloses a method of synchronising clocks in which a series of devices on a communication network transmit their local time to each other and network propagation time is determined by the ensemble of messages. Further disclosures by Eidson (US Patents Nos. 6,278,710, 6,665,316, 6,741 ,952 and 7,251 ,199) extend this concept but merely work toward a synchronisation scheme in which a constant stream of synchronising messages are transferred between each of the nodes of a distributed instrument network via Ethernet. This continual messaging consumes bandwidth and limits the accuracy of the possible synchronisation to several hundred nano-seconds in a point-to-point arrangement and substantially lower accuracy (typically micro-seconds) in a conventional switched subnet.

It should be understood that the terms 'clock signals' and 'synchronisation' in this disclosure are used to refer to clock signals, trigger signals, delay compensation information and propagation time measurement messages. It should also be understood that a 'notion of time' in this disclosure is used to denote an epoch or 'real time' and can also be used to refer to the combination of a clock signal and an associated epoch. SUMMARY OF THE INVENTION

It is a general object of the present invention to enable precision synchronisation of a plurality USB devices, synchronised, in turn, to another instrumentation platform.

In a first broad aspect, the present invention provides a method of controlling a plurality of event driven instruments as a single time-controlled synchronous virtual instrument, the method comprising: attaching the plurality of instruments to a common communications network; attaching a control device to the common communication network, the control device containing a local clock, the local clock maintaining a notion of real time; providing the control device with a plurality of trigger times, each of the trigger times associated with one or more of the instruments; and transmitting an event signal to those of the instruments associated with a respective one of the trigger times when the notion of real time of the control device matches the respective trigger time.

Thus, timing control using a time based architecture of time-based triggers and signals is provided.

In an embodiment, the local clock of the timing generator maintains its own notion of real time with an onboard real time clock and precision oscillator. The local clock of the timing generator may be synchronised to an externally derived notion of time, and selects a most accurate of available sources of time. As an example, the timing generator may be synchronised to the packet or protocol framing signals in a Wireless USB for distributing synchronisation to a wireless network of devices. The timing generator's notion of real time may furthermore be chosen as the most accurate timebase from all attached sources of time and therefore be the timebase master for all attached synchronous networks.

In one embodiment, the local clock is synchronised to an external time reference (that is, external to the instruments or control device, as the method is applied to a system of discrete instruments that are synchronised to a common notion of time that is referred to an external source, such as GPS). In one embodiment, the timing generator has an input for receiving from an external time source information signals that contain a timebase reference. The external time source may be a Global Positioning System (GPS) reference clock signal; an atomic clock signal; a synchronised USB; an Ethernet time code signal, such as but not limited to, an IEEE-1588 Precision Time Protocol (PTP) reference time signal, an Network Time Protocol (NTP) time signal or other Ethernet time reference; an Inter-Range Instrumentation Group (IRIG) reference time signal, or any other reference time signal. The external time source may be received through, for example, electrical cables, through optical fibre, wireless mechanism.

Thus, the present invention allows the synchronisation of SuperSpeed connected USB devices with devices connected via Ethernet (using Network Time Protocol (NTP), the IEEE-1588 synchronisation protocol or any other time source); with devices connected via a PCI bus; compact PCI bus; with devices connected via a PXI (or PXI-express) bus; with devices connected via a VXI or VME bus; with devices connected via wireless means including but not limited to Zigbee or Wireless USB; and devices connected across any other communication bus.

The a particular embodiment, the method further comprises: determining respective propagation times of trigger signals from the control device to each of the instruments; determining respective prethggers for each of the trigger times, the respective pretrigger being equal to the respective propagation time; adjusting the trigger times according to the respective pretriggers; wherein each of the trigger signals is launched onto the communication network at the respective pretrigger times so as to arrive at each of the respective plurality of instruments at the respective trigger times.

The method may include transmitting the event signal across a low latency interface.

The method may include the local clock maintaining the notion of real time using a real time clock register and precision oscillator.

In one embodiment, a synchronisation bridge (bridging between a plurality of busses) comprises a plug-in board to be used inside a personal computer system. In a further embodiment the synchronisation bridge comprises a plug- in board for an instrumentation system such as compactPCI, PXI, PXI-express, VXI, VME or other instrumentation system. Most notably in the case of PXI and PXI-express the synchronisation bridge would preferably be used in the slot 1 timing controller card slot to enable synchronisation across the PXI or PXI- express instrumentation chassis. Furthermore the synchronisation bridge may comprise circuitry to synchronise the SuperSpeed USB with a wireless network, either a Wireless USB network or another type of network using a variety of protocols.

In yet another embodiment the synchronisation bridge comprises a home entertainment system whereby audio and video streams are synchronised and distributed across a plurality of busses, for example SuperSpeed USB and Ethernet, most notably using Precision Time Protocol (PTP) or IEEE-1588. In this case, audio-visual information, for example for home theatre or gaming applications, is decoded by the bridge (or may also be decoded by another component and transferred to the bridge) for delivery across a plurality of synchronised networks. In a particular embodiment, video streams are passed across the SuperSpeed USB that is synchronised with the Ethernet for delivery of the audio streams, although other embodiments will be evident to those skilled in the art.

In an embodiment, the timing generator contains a USB Host Controller adapted to provide a synchronous USB. In this embodiment, the timing generator may be adapted to distribute synchronisation information, including - for example - synchronous clocking, absolute time reference and trigger signals or a trigger signal, a clock signal and clock phase information, to a plurality of USB devices by any of the means described herein. The synchronisation information may be referenced or synchronised to a notion of real time of the timing generator; this notion of real time may be further referenced or synchronised to an external source of time, with the timing generator acting as a bridge between different synchronisation schemes.

In one embodiment, the rack-based instrument chassis is a PXI (including PXI- express), CompactPCI, VXI, VME or other instrumentation system. In this embodiment, the method may comprise including the timing generator within a Slot 1 timing controller for a PXI system and delivering the event signals across the dedicated PXI (including PXI-express) Trigger Bus or PXI Star Trigger Bus.

In an embodiment, the timing generator is adapted to deliver event signals to the plurality of instruments via a Trigger Bus or PXI Star Trigger Bus, at the predefined times, coordinated by the timing generator's notion of time and taking into account signal propagation time across the PXI Trigger Bus or PXI Star Trigger Bus. According to this embodiment, each attached instrument functions as it normally would in a typical event based architecture, retaining its event-based operation, executing commands or operations in response to event signals. According to this embodiment the time-based control signals may therefore all be generated on the timing generator.

In yet another embodiment, each of the attached instruments maintains its own notion of real time, synchronised to a notion of real time of the timing generator. Requests for execution of commands or operations at predetermined times are delivered to the registers locally to the plurality of instruments. The instruments are then responsible for maintaining their own notions of real time by tracking the local clock of the timing generator and executing commands or operations at their respective plurality of predetermined and preconfigured times.

It will be apparent to those skilled in the art that a combination of the above embodiments is possible, whereby some of the attached instruments maintain their own notion of real time, executing their own commands at the predetermined times, while other of the attached instruments operate in an event driven framework with the timing generator coordinating their operation via signals sent across the Trigger Bus or PXI Star Trigger Bus.

According to this aspect, there is also provided an apparatus for providing time- control of a plurality of instruments, the apparatus comprising: a real time clock; a plurality of time registers corresponding respectively to the instruments; circuitry for attaching the apparatus to the instruments; circuitry for generating event signals; circuitry for delivering the event signals to the instruments when the instruments are attached to the apparatus; wherein the circuitry for generating event signals is adapted to generate the event signals corresponding to those of the respective time registers that match the real time register.

In one embodiment, the circuitry for attaching the plurality of instruments is a PXI or PXI-express chassis.

In an embodiment, the circuitry for delivering the event signals is a PXI Trigger Bus or PXI Star Trigger Bus.

In an embodiment, the circuitry for attaching the instruments is a common VXI chassis, a common CompactPCI chassis, any common interface bus or at least two different interfaces.

In a certain embodiment, the instruments are attached to a common VME chassis.

In a second broad aspect, the present invention provides a method of controlling a plurality of PXI-card-based devices as a single time-controlled synchronous virtual instrument, the method comprising: attaching the devices to a common PXI or PXI-express chassis; attaching a control device to slot 1 of the PXI chassis, the control device containing a local clock that maintains a notion of real time; synchronising respective local clocks of a first set of the devices with the notion of real time of the control device; configuring the first set of the devices to perform functions at a plurality of respective trigger times; configuring a second set of the devices to perform functions upon receipt of respective event trigger signals; the control device transmitting the respective event trigger signals to the respective devices of the second set at the respective trigger times; wherein the second set of devices perform their respective functions on receipt of event signals generated by the control device at the appropriate time and the first set of devices are synchronised to the notion of time of the control device and perform their respective functions at the appropriate time with respect to their respective internal synchronised clocks. In one embodiment, the control device configures the plurality of first PXI devices with their respective trigger times across a PXI PCI Bus.

In another embodiment, the control device transmits the plurality of event trigger signals to their respective the second PXI devices across a PXI Trigger Bus or PXI Star Trigger Bus.

In one embodiment, the control device transmits the event trigger signals to their respective the second set of devices across a PXI Trigger Bus or PXI Star Trigger Bus.

The method may include synchronising the first set of devices to the notion of real time of the control device across the PXI Trigger Bus or PXI Star Trigger Bus.

The notion of real time may be synchronised to an external time reference (which may comprise, for example, a GPS time server, an IEEE-1588 time server, an NTP time server or an IRIG time server).

In a third broad aspect, the present invention provides an apparatus for controlling a plurality of PXI-card-based devices as a single time-controlled synchronous virtual instrument, the apparatus comprising: circuitry for attaching the apparatus to a PCI bus of a first PXI or PXI-express chassis; circuitry for attaching the apparatus to a PXI Trigger or PXI Star Trigger bus of a second PXI or PXI-express chassis; a local clock that maintains a notion of real time; and a plurality of time registers.

The first PXI or PXI-express chassis may be the second PXI or PXI-express chassis.

The apparatus may be adapted to transmit a first clock signal derived from the local clock across the PXI Trigger or PXI Star Trigger bus to a selected one or more of the devices.

In one embodiment, the apparatus is adapted to transmit a plurality of commands to the devices across the PCI bus. The commands may include operations that are required to be executed and respective times at which execution of the operations is required.

In a certain embodiment, the apparatus is adapted to transmit an event trigger signal across the PXI Trigger or PXI Star Trigger bus to a selected one or more of the devices at a predetermined time of the local clock.

In a fourth broad aspect, the present invention provides a method of controlling a plurality of instruments attached to a rack-based instrument chassis, the method comprising: connecting to the instrument chassis a timing generator with a local clock and a plurality of registers; synchronising the local clock to a notion of real time; programming each of the instruments attached to the instrument chassis to execute a plurality of commands or operations at respective predefined times; configuring or providing the registers of the timing generator with the respective predefined times required for execution of the plurality of respective commands or operations; comparing each of the registers with the local clock; wherein the timing generator is adapted to output respective event signals to each of the attached instruments in response to the time stored at the respective registers that match the local clock.

In a fifth broad aspect, the present invention provides a method of extending the synchronisation domain of a PXI instrumentation architecture beyond the bounds of the PXI chassis, the method comprising: attaching a USB Host Controller with a local clock to a PXI instrumentation chassis; expanding the USB network by attaching a plurality of USB hubs to the PXI instrumentation chassis; synchronising the local clock of the USB Host Controller to a PXI Trigger Bus or PXI Star Trigger Bus of the PXI instrumentation chassis; synchronising a notion of real time of the USB Host Controller to predefined event signals derived from the PXI Trigger Bus or PXI Star Trigger Bus; and synchronising a plurality of LJSB devices at respective attachment points within the USB network to a timebase and the notion of time the USB Host Controller.

The synchronisation of the notion of real time of the USB Host Controller may include phase compensation for USB signal propagation time.

Thus, a distributed synchronisation extension for PXI is provided, whereby coordinated operation of a plurality of functions on the USB devices is enabled, synchronised to the time domain of the PXI instrumentation chassis. The resulting synchronised USB devices are — or synchronised USB network is — operable as an extension of the synchronised PXI architecture, but distributed outside the confines of the PXI rack.

The present invention therefore provides a time-based measurement and control architecture for trigger or event based instrumentation platforms such as PXI. A time based controller can be used to coordinate all triggering functions normally associated with these signals based platforms.

In one embodiment, the control device configures the plurality of first PXI devices with their respective trigger times across a PXI PCI Bus.

In one embodiment, the control device transmits the plurality of event trigger signals to their respective the second PXI devices across a PXI Trigger Bus or PXI Star Trigger Bus.

The notion of real time may be synchronised to an external time reference (which may comprise, for example, a GPS time server, an IEEE-1588 time server, an NTP time server or an IRIG time server). The USB hubs act as USB expansion hubs, and may be either card-based hubs attached to one of the expansion slots of the instrumentation chassis or stand-alone USB hubs that are not attached to the instrumentation chassis.

In one embodiment, the USB hubs attached to the PXI instrumentation chassis are attached to adjacent slots, with downstream USB communication between USB Hub layers across a PXI Local Bus.

Furthermore, respective local clocks of the plurality USB Hubs, used for re- clocking USB data streams through the hubs, are synchronised where possible to the same timebase as the USB Host Controller from timing signals derived from the PXI Trigger Bus or PXI Star Trigger Bus. This may be either by direct means for the USB hubs attached to the instrumentation chassis or indirectly via a USB synchronisation channel as described herein according to the other broad aspects of this invention. This minimises jitter in clocking periodic signal structures contained within the USB data stream through the plurality of USB Hubs, thereby minimising the jitter of the local clocks of the plurality of synchronised USB devices.

In a particular embodiment, the method includes phase locking, or syntonising, the local clock on the USB Host Controller and respective local clocks of the USB hubs to a reference clock signal provided by the PXI Trigger Bus or PXI Star Trigger Bus. The method may include phase-aligning, or synchronising, the local clock on the USB Host Controller and the local clocks of the USB hubs to a reference trigger signal provided by the PXI Trigger Bus or PXI Star Trigger Bus.

In one particular embodiment, the method comprises adapting the USB network once synchronised to be an extension of the PXI instrumentation architecture. In this way the USB network provides a measurement and control network that is coordinated with the PXI instrumentation architecture. Furthermore the USB network provides a distributed PXI-based instrumentation system for timing, measurement and control, maintaining the precision timing of the PXI chassis, but in a distributed format.

In an embodiment, the USB Host Controller comprises an input for receiving from a source external to the USB network, information signals that contain a timebase reference. In a particular embodiment above the information signals are received from the PXI Trigger Bus or PXI Star Trigger Bus. The external source of time may also be a Global Positioning System (GPS) reference clock signal; an atomic clock signal; a synchronised USB; an Ethernet time code signal, such as but not limited to, an IEEE-1588 Precision Time Protocol (PTP) reference time signal, an Network Time Protocol (NTP) time signal or other Ethernet time reference; an Inter-Range Instrumentation Group (IRIG) reference time signal, or any other reference time signal. The external time source may be received through, for example, electrical cables constituting or attached to the input or through optical fibre, a wireless means or any other means of transferring signals mechanism.

In an embodiment, a hybrid instrumentation network comprising a plurality of interconnected and synchronised instrumentation platforms is multiply connected to a plurality of PXI instrumentation chassis. According to this embodiment a USB synchronised to a given PXI instrumentation chassis may deliver synchronisation information, including a clock signal and notion of real time, to a USB Host Controller in another PXI chassis. In this way timing reference signals may be accurately distributed among the plurality of PXI chassis.

In a certain embodiment, the USB Hubs and USB devices are synchronised by any of the methods or apparatuses according to the invention described herein, such as via a periodic signal structure contained in a non-SuperSpeed USB communication channel; to a SuperSpeed USB device via a non-SuperSpeed synchronisation channel which disables standard non-SuperSpeed signals and instead multiplexes specific synchronisation information across the non- SuperSpeed D+/D- data signalling lines; to a SuperSpeed USB device via a clock synchronised to an Isochronous Timestamp Packet synchronisation methodology; or any other synchronisation mechanism.

The SuperSpeed USB Isochronous Timestamp Packets contain information concerning the time domain of the USB Host Controller. The Isochronous Timestamp Packet contains information about the absolute time that it was generated by the USB Host Controller's physical layer and contains both a USB frame number reference and a time offset since the previous frame boundary. The Isochronous Timestamp Packet also contains information to inform the USB device of any transmission delays in the LJSB network. This information allows creation of a system to determine a mapping between time domains of multiple devices and therefore synchronise all devices.

It should be noted that all the various features of each of the above aspects of the invention can be combined as suitable and desired.

Furthermore, it should be noted that the invention also provides apparatuses and systems arranged to perform each of the methods of the invention described above.

In addition, apparatuses according to the invention can be embodied in various ways. For example, such devices could be constructed in the form of multiple components on a printed circuit or printed wiring board, on a ceramic substrate or at the semiconductor level, that is, as a single silicon (or other semiconductor material) chip.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the present invention may be more clearly ascertained, embodiments will now be described, by way of example, with reference to the accompanying drawing, in which:

Figure 1 is a schematic diagram of the dual-bus architecture of USB3 according to the background art;

Figure 2 is a schematic representation of a background art PXI Chassis;

Figure 3 is a schematic representation of a means for expanding a Synchronous USB within a PXI Chassis according to an embodiment of the present invention;

Figure 4 is a schematic representation of a Time-Based Controller for a PXI Instrumentation system according to an embodiment of the present invention;

Figure 5 is a schematic representation of a Time-Based Controller for a PXI Instrumentation system according to another embodiment of the present invention; and

Figure 6 is a schematic representation of a distributed synchronisation extension to the PXI platform according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Figure 2 is a schematic representation of the architecture of a PXI instrumentation chassis 50 according to the background art. The PXI chassis 52 contains a slot 54 for a computer (viz. slot 0 of chassis 52, which typically houses a rugged embedded PC), a timing controller slot 56 [viz. slot 1 of chassis 52), and a plurality of expansion slots 58. These components are connected by several busses 60, 62, 64 across the backplane (which also provides power to the modules as required).

Main communication is provided across the PCI bus 60. All data is transferred between the embedded computer (connected to slot 0) and attached timing controller (connected to slot 1 ) and plug-in modules 58 across PCI bus 60. Slot 1 may contain a special timing controller device that provides coordination of the different plug-in modules via delivery of clock and trigger event signals across the backplane's Star Trigger Bus 62. Finally a PXI Local Bus 64 is provided for sideband communication between adjacent modules.

A system 110 for synchronous USB expansion according to a further embodiment of the present invention is shown schematically in figure 3. System 110 includes a PXI chassis 1 12 with a slot 0 controller 114 and a slot 1 timing controller 1 16.

System 110 also includes a USB Host Controller 122 and two USB Hub devices 124 attached to PXI chassis 1 12 in adjacent slots of PXI chassis 1 12. USB Host Controller 122 has circuitry for determining a signal propagation time for signals to propagate to any USB devices attached to Host Controller 122, by any suitable method of the present invention described herein. USB Hub devices 124 each has a plurality of downstream USB expansion ports 126 on their respective front panels. USB Host Controller 122 may optionally have a plurality of downstream USB expansion ports 128.

The timing controller attached at slot 1 [viz. 1 16) provides timing information to USB Host Controller 122 and USB Hub devices 124 via a PXI Star Trigger Bus 130. These signals advantageously include a reference clock and event trigger signals. In this way, each of the USB Host Controller 122 and USB Hub devices 124 can synchronise its clock to the same timebase, derived from the timing controller 1 16. This reduces the likelihood of clock jitter between the synchronised USB devices attached to system 1 10.

Furthermore USB Host Controller 122 and USB Hub devices 124 are daisy chained using a PXI Local Bus 132, which connects adjacent modules providing a sideband communication channel between adjacent modules.

It should be noted that the technique employed in this embodiment is also applicable to PXI-express. PXI-express is an evolution of PXI in which the PCI bus (cf. PCI bus 60 of figure 2) has been upgraded to a PCI-express bus, but is otherwise comparable to PXI.

It will also be apparent to those skilled in the art that a plurality of USB Host Controllers 122 can be used in PXI Chassis 1 12, each arranged to receive synchronisation signals from PXI Star Trigger Bus 130. In this way a plurality of USB networks can be synchronised together and to the notion of time of PXI Chassis 1 12.

Furthermore, a USB Host Controller 122 may also be attached to the Slot 1 PXI timing controller slot and contain additional circuitry to drive clock and trigger signals onto the Star Trigger Bus 130. This would allow USB Host Controller 122 to control the timing of multiple attached PXI modules by transmitting precise timing signals onto PXI Star Trigger Bus 130 through an additional dedicated connector. In this embodiment, a local clock source of Host Controller 122 provides a reference clock signal, which may be delivered to PXI Star Trigger Bus 130 and subsequently to attached PXI devices.

A PXI Instrumentation System according to another embodiment of the present invention is shown schematically at 150 in figure 4. PXI Instrumentation System 150 comprises a PXI Chassis 152 that has a slot 0 computer 154, a slot 1 timing controller 156 and a plurality of PXI Modules 158. PXI modules 158 may be the same type of module, or different types of module.

Slot 1 timing controller 156, optionally, has a plurality of reference time-code interfaces 160. These are able to act as both a source of time-code information (to synchronise other clocks to timing controller 156) and a sink for time-code information (to synchronise time controller 156 to an external time reference), in order to synchronise to the most accurate clock in extended the network. Whether or not timing controller 156 has any of these reference time-code interfaces 160, but either way, timing controller 156 has a local clock 162 that maintains a notion of absolute time.

Timing controller 156 can be programmed to deliver event triggering signals to each of the attached PXI Modules 158 via a PXI Star Trigger Bus 164 at predetermined times. In this way, a system of typical event-driven PXI Modules can be controlled in a Time-Based manner using timing controller 156 as the source of time-based triggers.

Figure 5 is a schematic representation of a PXI Instrumentation system with Time-Based Controller according to another embodiment of the present invention, shown generally at 170. PXI Instrumentation system 170 comprises a PXI Chassis 172 with a slot 0 computer 174, a slot 1 timing controller 176 and a plurality of PXI Modules 178. PXI Modules 178 may be the same type of module, or different types of module.

Timing controller 176 has a local clock 180 that maintains a notion of absolute time. Timing controller 176 optionally also has a plurality of reference time- code interfaces 182, which desirably are able to act as both a source of time- code information (to synchronise other clocks to the timing controller 176) and a sink for time-code information (to synchronise time controller 176 to an external time reference), in order to synchronise to the most accurate clock in the extended network.

Each of attached PXI Modules 178 has a respective local clock 184 that maintains its own notion of absolute time. Timing controller 176 sends synchronising signals, which may include a clock signal for syntonisation and a signal indicative of synchronising the phase of the clock, to each of PXI Modules 178 via a PXI Star Trigger Bus 186. The respective local clocks 184 of PXI Modules 178 may be syntonised and synchronised to the notion of time maintained by timing controller 176 by any suitable means.

Each of PXI Modules 178 can be programmed via a PCI Bus 188 to execute commands at a predetermined time. In this way a system of time-based execution commands are provided to a PXI Instrumentation system 170.

It will also be apparent to those skilled in the art that a combination of time- based triggering is possible by mixing time and event based modules in systems 150 and 170 of figures 4 and 5 respectively.

Figure 6 is a schematic representation of an extended PXI system 190 for providing a distributed synchronisation extension to the PXI platform according to an embodiment of the present invention. PXI system 190 comprises two PXI Chassis 192 and 194 and one or more synchronised USB devices 196 and 198 attached respectively thereto. It should be understood that a plurality of USB devices may be attached to PXI Chassis 192 and 194 and that accordingly USB devices 196 and 198 are exemplary only.

A plurality of time-triggered PXI Modules 200 and event-triggered PXI Modules 202 are attached to each of PXI Chassis 192, 194. (time-triggered PXI Modules 200 are shown with a clock in this figure for clarity.) PXI Chassis 192, 194 contain respective slot 0 computers 204, 206 and slot 1 timing controllers 208, 210.

Timing controllers 208 and 210 have interfaces to both transmit and receive time-code information (as in system 150 of figure 4). In this embodiment, timing controller 208 provides a synchronised and time-triggered environment to its attached PXI devices via a PXI Star Trigger Bus 212, as does timing controller 210 in chassis 194 via its PXI Star Trigger Bus 214. USB Hub 216, a time- triggered device synchronised to timing controller 208, hosts synchronised USB device 196. Similarly, USB Hub 218, a time-triggered device synchronised to timing controller 210, hosts synchronised USB device 198. USB Hubs 216 and 218 may each be a USB Host Controller or simply an expansion hub.

USB Hub 216 has a downstream synchronous USB connection 220 to a USB Device Function (not shown) within timing controller 210; this USB connection 220 provides clock and timing information to timing controller 210. An alternative synchronisation path 222 may also be provided, extending between slot 1 timing controllers 208, 210, but in practice would not be used if USB connection 220 is in use; synchronisation path 222 may be any of the synchronisation interfaces supported by both slot 1 timing controllers 208, 210, including IEEE-1588, NTP, dedicated clock and trigger lines, IRIG or other timing protocols as described by reference to system 150 of figure 4.

Timing controller 208 is therefore the reference clock to which all devices are synchronised in this distributed synchronous network based on the PXI form factor. It will be apparent to those skilled in the art that many PXI chassis and their local distributed LJSB networks may be synchronised according to this embodiment of the present invention.

Modifications within the scope of the invention may be readily effected by those skilled in the art. It is to be understood, therefore, that this invention is not limited to the particular embodiments described by way of example hereinabove and that combinations of the various embodiments described herein are readily apparent to those skilled in the art.

In the preceding description of the invention and in the claims that follow, except where the context requires otherwise owing to express language or necessary implication, the expression "Host Controller" embraces all forms of USB Host Controller, including standard LJSB Host controllers, USB-on-the-go Host Controllers and wireless LJSB Host Controllers.

In the preceding description of the invention and in the claims that follow, except where the context requires otherwise owing to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, that is, to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention.

Further, any reference herein to background art is not intended to imply that such background art forms or formed a part of the common general knowledge in any country.

Claims

CLAIMS:

1. A method of controlling a plurality of event driven instruments as a single time-controlled synchronous virtual instrument, the method comprising: attaching said plurality of instruments to a common communications network; attaching a control device to said common communication network, said control device containing a local clock, said local clock maintaining a notion of real time; providing said control device with a plurality of trigger times, each of said trigger times associated with one or more of said instruments; and transmitting an event signal to those of said instruments associated with a respective one of said trigger times when said notion of real time of said control device matches said respective trigger time.

2. A method as claimed in claim 1 , further comprising: determining respective propagation times of trigger signals from said control device to each of said instruments; determining respective pretriggers for each of said trigger times, said respective pretrigger being equal to said respective propagation time; adjusting said trigger times according to said respective pretriggers; wherein each of said trigger signals is launched onto said communication network at said respective pretrigger times so as to arrive at each of said respective plurality of instruments at said respective trigger times.

3. A method as claimed in either claim 1 or 2, including transmitting said event signal across a low latency interface.

4. A method as claimed in any one of claims 1 to 3, including said local clock maintaining said notion of real time using a real time clock register and precision oscillator.

5. A method as claimed in any one of claims 1 to 3, wherein said local clock is synchronised to an external time reference.

6. A method as claimed in claim 5, wherein said external time reference is a global positioning system (GPS) time code.

7. A method as claimed in claim 5, wherein said external time reference is provided by an atomic clock or by a synchronised USB.

8. A method as claimed in claim 5, wherein said external time reference is an Ethernet provided time code.

9. A method as claimed in claim 8, wherein said Ethernet provided time code is an IEEE-1588 Precision Time Protocol time code.

10. A method as claimed in claim 8, wherein said Ethernet provided time code is a Network Time Protocol (NTP) time code.

1 1. A method as claimed in claim 5, wherein said external time reference is an Inter-Range Instrumentation Group (IRIG) time code.

12. A method as claimed in claim 5, wherein said external time reference is a plurality of event signals from a PXI chassis.

13. A method as claimed in claim 5, wherein said external time reference is a plurality of event signals from a VXI chassis.

14. A method as claimed in claim 5, wherein said external time reference is received from another instrumentation platform.

15. An apparatus for providing time-control of a plurality of instruments, the apparatus comprising: a real time clock; a plurality of time registers corresponding respectively to said instruments; circuitry for attaching said apparatus to said instruments; circuitry for generating event signals; circuitry for delivering said event signals to said instruments when said instruments are attached to said apparatus; wherein said circuitry for generating event signals is adapted to generate said event signals corresponding to those of said respective time registers that match said real time register.

16. An apparatus as claimed in claim 15, wherein said circuitry for attaching said plurality of instruments is a PXI or PXI-express chassis.

17. An apparatus as claimed in either claim 15 or 16, wherein said circuitry for delivering said event signals is a PXI Trigger Bus or PXI Star Trigger Bus.

18. An apparatus as claimed in claim 15, wherein said circuitry for attaching said instruments is a common VXI chassis.

19. An apparatus as claimed in claim 15, wherein said circuitry for attaching said instruments is a common CompactPCI chassis.

20. An apparatus as claimed in claim 15, wherein said instruments are attached to a common VME chassis.

21. An apparatus as claimed in claim 15, wherein said circuitry for attaching said instruments is any common interface bus.

22. An apparatus as claimed in claim 15, wherein said circuitry for attaching said instruments comprises at least two different interfaces.

23. A method of controlling a plurality of PXI-card-based devices as a single time-controlled synchronous virtual instrument, the method comprising: attaching said devices to a common PXI or PXI-express chassis; attaching a control device to slot 1 of said PXI chassis, said control device containing a local clock that maintains a notion of real time; synchronising respective local clocks of a first set of said devices with the notion of real time of said control device; configuring said first set of said devices to perform functions at a plurality of respective trigger times; configuring a second set of said devices to perform functions upon receipt of respective event trigger signals; said control device transmitting said respective event trigger signals to said respective devices of said second set at said respective trigger times; wherein said second set of devices perform their respective functions on receipt of event signals generated by said control device at the appropriate time and said first set of devices are synchronised to the notion of time of said control device and perform their respective functions at the appropriate time with respect to their respective internal synchronised clocks.

24. A method as claimed in claim 23, wherein said control device configures said plurality of first PXI devices with their respective trigger times across a PXI PCI Bus.

25. A method as claimed in claim 23, wherein said control device transmits said plurality of event trigger signals to their respective said second PXI devices across a PXI Trigger Bus or PXI Star Trigger Bus.

26. A method as claimed in claim 24, wherein said control device transmits said event trigger signals to their respective said second set of devices across a PXI Trigger Bus or PXI Star Trigger Bus.

27. A method as claimed in claim 23, including synchronising said first set of devices to said notion of real time of said control device across said PXI Trigger Bus or PXI Star Trigger Bus.

28. A method as claimed in claims 23 to 27, wherein said notion of real time is synchronised to an external time reference.

29. A claim as claimed in claim 28, wherein said external time reference is a GPS time server.

30. A claim as claimed in claim 28, wherein said external time reference is an IEEE-1588 time server.

31. A claim as claimed in claim 28, wherein said external time reference is an NTP time server.

32. A claim as claimed in claim 28, wherein said external time reference is an IRIG time server.

33. An apparatus for controlling a plurality of PXI-card-based devices as a single time-controlled synchronous virtual instrument, the apparatus comprising: circuitry for attaching said apparatus to a PCI bus of a first PXI or PXI-express chassis; circuitry for attaching said apparatus to a PXI Trigger or PXI Star Trigger bus of a second PXI or PXI-express chassis; a local clock that maintains a notion of real time; and a plurality of time registers.

34. An apparatus as claimed in claim 33, wherein said first PXI or PXI-express chassis is said second PXI or PXI-express chassis.

35. An apparatus as claimed in either claim 33 or 34, adapted to transmit a first clock signal derived from said local clock across said PXI Trigger or PXI Star Trigger bus to a selected one or more of said devices.

36. An apparatus as claimed in any one of claims 33 to 35, adapted to transmit a plurality of commands to said devices across said PCI bus.

37. An apparatus as claimed in claim 36, wherein said commands include operations that are required to be executed and respective times at which execution of said operations is required.

38. An apparatus as claimed in any one of claims 33 to 37, adapted to transmit an event trigger signal across said PXI Trigger or PXI Star Trigger bus to a selected one or more of said devices at a predetermined time of said local clock.

39. A method of controlling a plurality of instruments attached to a rack-based instrument chassis, the method comprising: connecting to the instrument chassis a timing generator with a local clock and a plurality of registers; synchronising said local clock to a notion of real time; programming each of said instruments attached to the instrument chassis to execute a plurality of commands or operations at respective predefined times; configuring or providing said registers of said timing generator with said respective predefined times required for execution of said plurality of respective commands or operations; comparing each of said registers with said local clock; wherein said timing generator is adapted to output respective event signals to each of said attached instruments in response to the time stored at said respective registers that match said local clock.

40. A method of extending the synchronisation domain of a PXI instrumentation architecture beyond the bounds of the PXI chassis, the method comprising: attaching a USB Host Controller with a local clock to a PXI instrumentation chassis; expanding the USB network by attaching a plurality of USB hubs to the PXI instrumentation chassis; synchronising the local clock of the USB Host Controller to a PXI Trigger Bus or PXI Star Trigger Bus of the PXI instrumentation chassis; synchronising a notion of real time of the USB Host Controller to predefined event signals derived from the PXI Trigger Bus or PXI Star Trigger Bus; and synchronising a plurality of USB devices at respective attachment points within the USB network to a timebase and the notion of time the USB Host Controller.

41. A method as claimed in claim 40, wherein synchronisation of said notion of real time of said USB Host Controller includes phase compensation for USB signal propagation time.