WO2010018254A1 - Microprocessor system including a reconfigurable hardwired control unit and method for operating a microprocessor - Google Patents

Microprocessor system including a reconfigurable hardwired control unit and method for operating a microprocessor Download PDF

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Publication number
WO2010018254A1
WO2010018254A1 PCT/ES2009/000396 ES2009000396W WO2010018254A1 WO 2010018254 A1 WO2010018254 A1 WO 2010018254A1 ES 2009000396 W ES2009000396 W ES 2009000396W WO 2010018254 A1 WO2010018254 A1 WO 2010018254A1
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Prior art keywords
control unit
microprocessor
instruction
data
instructions
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PCT/ES2009/000396
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Spanish (es)
French (fr)
Inventor
Javier Castillo Villar
José Ignacio MARTINEZ TORRES
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Universidad Rey Juan Carlos
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Publication of WO2010018254A1 publication Critical patent/WO2010018254A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Definitions

  • the invention encompasses in the field of microprocessors.
  • RISC Reduced Instruction Set Computer
  • an RISC processor comprises two distinct parts, namely the control unit and the data path.
  • the data path includes all the hardware necessary to perform the tasks required by each assembly instruction or machine code, including the arithmetic-logic unit (ALU: "Arithmetic-Logic Unit”) responsible for calculating, the instruction memory contained in the program to be executed, the data memory that contains the data with which the program / processor operates, registers (for example, organized in a register bank), as well as a large number of other elements, including adders, shifters, multiplexers, etc.
  • the control unit (CU: “Control Unit”) is responsible for receiving the program instructions contained in the instruction memory and generate the necessary control signals so that the data path performs the necessary operations to execute said instructions.
  • control unit There are several ways to physically implement a control unit, the most common being the wired control unit (“hardwired”) and the microprogrammed (“ ⁇ croprogrammed”).
  • the wired control unit has a basically rigid configuration.
  • the logic is interpreted by the instruction and the control outputs are generated towards the data path.
  • the microprogrammed control unit contains in its interior a series of micro-instructions that are responsible for detailing the low-level steps that the data path must execute to execute the instruction.
  • the wired control unit is much faster and more efficient in resource consumption (silicon area) and is therefore the most commonly used in RISC processors.
  • the microprogrammed control unit gives the system more flexibility as it is possible to change the microprogram to correct errors, add support for new instructions or even change the entire coding of the instruction set by virtually converting the microprocessor into a different one. In this way you can, for example, change the microinstructions contained in a microprogrammed control unit so that the microprocessor, instead of executing code or programs compiled for a certain processor architecture (for example, for PowerPC, MIPS, Intel x86, SPARC, ARM, Alpha, etc.) can execute compiled programs for another type of architecture. Logically, this makes the processor much more flexible.
  • microprogrammed control units that can execute instruction sets of different architectures (i.e., programs compiled for different processor architectures) only by modifying the microprogram. This is possible due to the great similarities between the instruction sets of the different architectures, so that it is possible to execute all these different instruction sets on the same data path with hardly any modifications.
  • the processor must have a data path that contains the necessary hardware set to run as many different instruction sets as possible without modifications. That is, it can be a data path that represents a "superset" of the data paths of different processors, for example, of the different RISC processors.
  • WO-A-2007/015258 Refers to a configurable control unit. For this, an instruction set with a certain configuration capacity is planned. For certain applications it may be interesting to change the behavior of some instructions and for this each instruction has a field with attributes that changes the response of the control unit to that instruction. The control unit interprets these attributes and executes that instruction differently depending on the attribute. That is, the instruction set has special fields that are capable of modifying some properties of that control unit, such as the time it takes for the instruction to execute. This functionality is supported by additional hardware in the control unit.
  • a first aspect of the invention relates to a microprocessor system comprising a microprocessor comprising: (i) a data path comprising at least one arithmetic-logic unit, registers, an instruction memory configured to contain instructions of a program that the microprocessor must execute, and a data memory configured to contain data with which can operate the program; Y
  • control unit configured to receive program instructions from the instruction memory and to generate control signals and apply them to the data path so that operations are performed in the data path in accordance with the program instructions ;
  • This control unit is a wired control unit.
  • the system is configured to, in response to a reconfiguration instruction contained in the program instructions, reconfigure the control unit, so that the control unit, which before receiving said reconfiguration instruction ' was configured so that the microprocessor processes instructions of a compiled program for a first processor architecture, after receiving said reconfiguration instruction it is reconfigured to be configured so that the microprocessor processes instructions of a compiled program for a second processor architecture, other than the First processor architecture.
  • control unit can be modified when the microprocessor is started and thereafter used for a certain type of compiled code, without changing the configuration during microprocessor operation.
  • Virtualization allows to generate code generated for another processor on a different machine (that is, on a machine that initially does not present the architecture corresponding to the code). It may be running code of the two (or more) machines
  • Analysis- consists of analyzing the consumption of the processor to "guess” what instructions you are executing; changing the coding of the instruction set its consumption also varies, making this type of attack more difficult. )
  • the system may comprise a memory containing at least two sets of data indicative of respective logical configurations of the control unit.
  • the system may comprise a reconfiguration device configured to, in response to the reconfiguration instruction, modify the configuration of the control unit according to the data of one of said data sets.
  • the control unit may be implemented in a programmable logic device.
  • programmable logic devices are: FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), CPLD (Complex
  • control unit may be implemented in an ASIC circuit.
  • the system may be configured to change the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, in order to make it difficult to analyze the operation of the microprocessor from a consumption analysis. energy system (and, therefore, to hinder "DPA attacks", as indicated above).
  • the system may be configured to make changes to the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, such changes being made randomly or pseudorandomly.
  • Randomization can refer to the frequency with which the configuration changes are made and / or at the times when the configuration changes occur, and / or to what new configuration will be selected, among the different configurations available (for example, in a system memory). That is, the time at which the configuration change occurs can be determined randomly (or pseudo-randomly), and / or the configuration to which it is changed can be chosen randomly (or pseudo-randomly).
  • This aspect of the invention may have interesting applications in, for example, the field of security.
  • Another aspect of the invention relates to a method for operating a microprocessor (for example, of the type described above), whose microprocessor comprises: a data path comprising at least one arithmetic-logic unit, registers, - a memory instruction set to contain instructions from a program • that the microprocessor must execute, and a data memory configured to contain data with which the program can operate; and a control unit configured to receive program instructions from the instruction memory and to generate control signals and apply them to the data path so that operations are performed in the data path according to the program instructions, being the control unit a wired control unit.
  • the method comprises the steps of in response to a reconfiguration instruction contained in the program instructions, reconfiguring the control unit, so that the control unit - goes from being configured so that the microprocessor processes instructions of a compiled program for a first processor architecture,
  • the step of reconfiguring the control unit can be performed by accessing data indicative of the logical configuration of the control unit.
  • This data may be housed in a memory in which at least two sets of data indicative of respective logical configurations of the control unit are housed.
  • one of said data sets can be accessed (for example, by accessing a memory location specified in the instruction of rec 'ONFIGURATION) and, through a hardware (for example) device can reconfigure the control unit according to said data set.
  • the reconfiguration can be performed on a control unit implemented in a programmable logic device, or on a control unit implemented in an ASIC circuit comprising at least a part of reconfigurable logic corresponding to the control unit.
  • the method may comprise the step of reconfiguring repetitively (for example, randomly or pseudorandomly, in terms of the moments in which it is reconfigured and / or as to what the new configuration will be) the control unit for the microprocessor Operate, at different times of a microprocessor operating period, with compiled programs for different microprocessor architectures.
  • the method may comprise the step of, in response to the reconfiguration instruction but before reconfiguring the control unit, to terminate the processing of instructions received prior to the reception of the reconfiguration instruction, for example, to ensure that each instruction is processed by the "architecture" that corresponds.
  • Another aspect of the invention relates to the use of a device according to what has been described above, to hinder an analysis of the operation of the microprocessor from an analysis of the energy consumption of the system (something that can serve to hinder "DPA attacks ").
  • another aspect of the invention relates to the use of the described method, in order to make it difficult to analyze the operation of the microprocessor based on an analysis of the energy consumption of the system.
  • Figure 1 shows a schematic view of a system according to a possible embodiment of the invention.
  • Figure 2. Shows a schematic view of a reconfiguring device and its relationship with a main memory and with the system control unit.
  • Figure 3. Shows a flowchart that reflects a possible way of carrying out the method of the invention.
  • a preferred embodiment of the invention is schematically shown in Figure 1, with a microprocessor comprising a data path 1 (which can be conventional) comprising a program counter 11 (which takes account of which is the next instruction of the program to be executed), instruction memory (cache) 12, register bank 13, arithmetic-logic unit 14, memory (cache) of data 15, multiplexers 16 (only one illustrated), etc.
  • the microprocessor comprises a wired control unit 2.
  • the control unit generates, in response to the instructions that you receive from instruction memory 12, signals that are applied to data path 1 to perform the corresponding operations. All this is conventional and it is not considered necessary to describe it here in more detail.
  • the system also comprises a memory 3, hereinafter referred to as "main memory”, something that is also conventional in this type of systems.
  • this main memory 3 includes sets or sets of data indicative of logical configurations different from the control unit 2, in the sense that depending on whether the control unit 2 is configured according to one or another of said data sets, the microprocessor (that is, the 'control unit set 2 and data path 1) can correctly process instructions from a compiled program for one or another processor architecture.
  • the system includes an element, subsystem or reconfiguring device 4 that can also act in response to the instructions arriving from the instruction memory.
  • the reconfiguration device Upon receiving (directly or indirectly, for example, as in Figure 2, through the control unit 2) a specific instruction, which we now call "reconfiguration instruction", the reconfiguration device accesses the main memory
  • control unit is implemented on reconfigurable logic hardware, for example, on an FPGA (Field Programmable Gate Array), PLD device
  • Figure 2 schematically reflects how the reconfigurator device 4, which can be implemented with hardware and comprise a bus controller, is able to connect to bus 5 of the system and read data from main memory 3.
  • the control unit 2 (implemented on configurable logic hardware 21) generates, in addition to (or instead of) the control signals 201 that it applies to data path 1, an indicative signal or instruction 202 that a reconfiguration of the control unit must occur, accompanied by (or including) an indication 202A of the location in main memory 3 where the data set that defines the new configuration of the control unit 2 begins.
  • the reconfiguring device 4 accesses, via bus 5, the main memory 3, reads there the data set defining the new configuration of the control unit, and dumps said new configuration into programmable logic 21, through a reconfiguration gate 22.
  • a reconfiguration gate 22 For example, in the case of an FPGA device of the manufacturer Xilinx ® , this can be done through its ICAP gate (Internal Configuration Access Port). That is, “dump" the new configuration corresponding to the data set obtained in main memory 3 (in the position or area indicated by the reconfiguration instruction 200), the "architecture" of the microprocessor is modified and, therefore, can be configured to process a new type of compiled programs.
  • Figure 3 schematically reflects how the invention can be implemented.
  • Both the control unit 2 and the reconfiguration device 4 are continuously looking for new instructions at their input, where the instructions arrive from the instruction memory 12 at the rate set by the program counter 11. Once a new one is detected instruction (step 100), this is decoded (step 101) and checked (step 102) if it is a "reconfiguration instruction". If it is not a "reconfiguration instruction", the control unit executes (step 103) the instruction in a conventional manner, and the processor proceeds to search for the next instruction.
  • the microprocessor starts executing the pending interrupts (step 104) and emptying the data path (step 105), and the reconfiguration device
  • step 106 which can be executed after, before or at the same time with steps 104-105) read (the data set indicative of) the new configuration of control unit 2 of main memory 4 and dump (in step 107, which is preferably carried out after step 105) said new configuration in the control unit 2, being therefore reconfigured.
  • the operation could be as follows: The processor is executing a certain instruction set contained in instruction memory 12. Within that instruction set there is a reconfiguration instruction and which basically serves to "activate" the reconfiguration device 4
  • control unit 2 and data path 1 ends everything you are doing up to that point, addressing all pending interruptions and emptying the data path.
  • interruptions in the system work to handle external events. For example, when a key is pressed on the processor an interrupt is activated and skips to a preset memory location for that event where the program is located to be executed if the key is pressed.
  • interruptions in the system work to handle external events. For example, when a key is pressed on the processor an interrupt is activated and skips to a preset memory location for that event where the program is located to be executed if the key is pressed.
  • the reconfiguring element 4 begins to read from the main memory 3 the new configuration of the control unit and reconfiguring said control unit on the corresponding reconfigurable hardware.
  • the word "comprises” and its variants should not be construed as excluding, that is, they do not exclude the possibility that what is described includes other elements, steps etc.
  • the invention is not limited to the specific embodiments that have been described but also covers, for example, the variants that can be made by the average person skilled in the art (for example, in terms of the choice of materials, dimensions , components, configuration, etc.), within what follows from the claims.

Abstract

The invention relates to a microprocessor system comprising a microprocessor including a data path (1) and a hardwired control unit (2). The system is configured to reconfigure the control unit in response to a reconfiguration instruction (200), such that, prior to reception of the reconfiguration instruction, the control unit is configured such that the microprocessor processes instructions from a program compiled for a first processor architecture and, following reception of said reconfiguration instruction, the control unit is reconfigured so that it remains configured such that the microprocessor processes instructions from a program compiled for a second processor architecture different from the first processor architecture.

Description

SISTEMA MICROPROCESADOR CON UNIDAD DE CONTROL CABLEADA • RECONFIGURABLE, Y MÉTODO PARA OPERAR UN MICROPROCESADORMICROPROCESSOR SYSTEM WITH WIRED CONTROL UNIT • RECONFIGURABLE, AND METHOD FOR OPERATING A MICROPROCESSOR
CAMPO TÉCNICO DE LA INVENCIÓN La invención se engloba en el campo de los microprocesadores .TECHNICAL FIELD OF THE INVENTION The invention encompasses in the field of microprocessors.
ANTECEDENTES DE LA INVENCIÓNBACKGROUND OF THE INVENTION
En la actualidad la mayor parte de los microprocesadores de propósito general están construidos siguiendo la arquitectura denominada RISC (Reduced Instruction Set Computer) . En este tipo de arquitectura, la cantidad de diferentes instrucciones que puede ejecutar el procesador ha sido reducida para simplificar el diseño del procesador.At present, most of the general purpose microprocessors are built following the architecture called RISC (Reduced Instruction Set Computer). In this type of architecture, the number of different instructions that the processor can execute has been reduced to simplify the design of the processor.
Básicamente, un procesador RISC comprende dos partes diferenciadas, a saber, la unidad de control y el camino de datos .Basically, an RISC processor comprises two distinct parts, namely the control unit and the data path.
El camino de datos comprende todo el hardware necesario para realizar las tareas que demanda cada instrucción ensamblador o código máquina, incluyendo la unidad aritmético-lógica (ALU: "Arithmetic-Logic Unit") encargada de realizar cálculos, la memoria de instrucciones que contiene el programa a ejecutar, la memoria de datos que contiene los datos con los que opera el programa/procesador, registros (por ejemplo, organizados en un banco de registros) , así como una gran cantidad de otros elementos, incluyendo sumadores, desplazadores, multiplexores, etc. - Por otra parte, la unidad de control (CU: "Control Unit") se encarga de recibir las instrucciones del programa contenidas en la memoria de instrucciones y generar las señales de control necesarias para que el camino de datos realice las operaciones necesarias para ejecutar dichas instrucciones.The data path includes all the hardware necessary to perform the tasks required by each assembly instruction or machine code, including the arithmetic-logic unit (ALU: "Arithmetic-Logic Unit") responsible for calculating, the instruction memory contained in the program to be executed, the data memory that contains the data with which the program / processor operates, registers (for example, organized in a register bank), as well as a large number of other elements, including adders, shifters, multiplexers, etc. - On the other hand, the control unit (CU: "Control Unit") is responsible for receiving the program instructions contained in the instruction memory and generate the necessary control signals so that the data path performs the necessary operations to execute said instructions.
Existen diversas formas de implementar físicamente una unidad de control, siendo las más habituales la unidad de control cableada ( "hardwired" ) y la microprogramada ("πύcroprogrammed") .There are several ways to physically implement a control unit, the most common being the wired control unit ("hardwired") and the microprogrammed ("πύcroprogrammed").
La unidad de control cableada tiene una configuración básicamente rígida. Mediante circuitos lógicos se interpreta la instrucción y se generan las salidas de control hacia el camino de datos.The wired control unit has a basically rigid configuration. The logic is interpreted by the instruction and the control outputs are generated towards the data path.
La unidad de control microprogramada contiene en su interior una serie de microinstrucciones que se encargan de detallar los pasos de bajo nivel que debe ejecutar el camino de datos para ejecutar la instrucción.The microprogrammed control unit contains in its interior a series of micro-instructions that are responsible for detailing the low-level steps that the data path must execute to execute the instruction.
Generalmente, la unidad de control cableada es mucho más rápida y eficiente en consumo de recursos (área de silicio) y es por tanto la más comúnmente usada en procesadores RISC. Sin embargo, la unidad de control microprogramada dota de mayor flexibilidad al sistema ya que es posible cambiar el microprograma para corregir errores, añadir soporte para nuevas instrucciones o incluso cambiar toda la codificación del juego de instrucciones convirtiendo virtualmente el microprocesador en otro diferente. De esta manera se puede, por ejemplo, cambiar las microinstrucciones contenidas en una unidad de control microprogramada para que el microprocesador, en lugar de ejecutar código o programas compilados para una determinada arquitectura de procesador (por ejemplo, para PowerPC, MIPS, Intel x86, SPARC, ARM, Alpha, etc.) pueda ejecutar programas compilados para otro tipo de arquitectura. Lógicamente, esto hace que el procesador sea mucho más flexible.Generally, the wired control unit is much faster and more efficient in resource consumption (silicon area) and is therefore the most commonly used in RISC processors. However, the microprogrammed control unit gives the system more flexibility as it is possible to change the microprogram to correct errors, add support for new instructions or even change the entire coding of the instruction set by virtually converting the microprocessor into a different one. In this way you can, for example, change the microinstructions contained in a microprogrammed control unit so that the microprocessor, instead of executing code or programs compiled for a certain processor architecture (for example, for PowerPC, MIPS, Intel x86, SPARC, ARM, Alpha, etc.) can execute compiled programs for another type of architecture. Logically, this makes the processor much more flexible.
Esta flexibilidad de las unidades de control microprogramadas ha sido explotada para diseñar procesadores que puedan ejecutar juegos de instrucciones de diferentes arquitecturas (es decir, programas compilados para diferentes arquitecturas de procesador) únicamente modificando el microprograma. Esto es posible debido a las grandes similitudes existentes entre los juegos de instrucciones de las diferentes arquitecturas, de tal forma que es posible ejecutar todos estos diferentes juegos de instrucciones sobre el mismo camino de datos sin apenas modificaciones . En la práctica puede haber alguna instrucción de un juego de instrucciones que no se pueda ejecutar sobre un .determinado camino de datos originalmente configurado para otra arquitectura de procesador; por lo tanto, puede ser conveniente, para mayor flexibilidad, que el camino de datos disponga del hardware adicional para ejecutar esa instrucción. Por lo tanto, para disponer de una flexibilidad máxima el procesador debe tener un camino de datos que contenga el conjunto de hardware necesario para ejecutar el mayor número posible de juegos de instrucciones diferentes sin modificaciones. Es decir, puede tratarse de un camino de datos que representa un "superconjunto" de los caminos de datos de diferentes procesadores, por ejemplo, de los diferentes procesadores RISC.This flexibility of microprogrammed control units has been exploited to design processors that can execute instruction sets of different architectures (i.e., programs compiled for different processor architectures) only by modifying the microprogram. This is possible due to the great similarities between the instruction sets of the different architectures, so that it is possible to execute all these different instruction sets on the same data path with hardly any modifications. In practice, there may be some instruction in a set of instructions that cannot be executed on a certain data path originally configured for another processor architecture; therefore, it may be convenient, for greater flexibility, for the data path to have the additional hardware to execute that instruction. Therefore, to have maximum flexibility, the processor must have a data path that contains the necessary hardware set to run as many different instruction sets as possible without modifications. That is, it can be a data path that represents a "superset" of the data paths of different processors, for example, of the different RISC processors.
US-A-2004/0133770 (Pappálardo, et al.) describe un procesador que comprende dos unidades de control, una cableada (con las ventajas que ello implica en cuanto a rapidez y consumo de recursos) y otra microprogramada (con las ventajas que ello implica en cuanto a flexibilidad) . Por lo tanto, el microprocesador puede adaptarse a programas compilados para otras arquitecturas (distintas de las que originalmente se han previsto al diseñar la unidad de control cableada) modificando la programación de la unidad de control microprogramada . Por lo tanto, en un principio, se combinan las ventajas de ambos tipos de unidad de control, aunque con la desventaja de tener que disponer de dos unidades de control, lo cual implica una mayor cantidad de hardware, con las desventajas que ello implica en cuanto a, por ejemplo, el uso de superficie .US-A-2004/0133770 (Pappálardo, et al.) Describes a processor comprising two control units, one wired (with the advantages that this implies in terms of speed and resource consumption) and another microprogrammed (with the advantages that this implies in terms of flexibility) Therefore, the microprocessor can be adapted to programs compiled for other architectures (other than those originally planned when designing the wired control unit) by modifying the programming of the microprogrammed control unit. Therefore, initially, the advantages of both types of control unit are combined, although with the disadvantage of having to have two control units, which implies a greater amount of hardware, with the disadvantages that this implies in as for, for example, the use of surface.
WO-A-2007/015258 (Gopi, et al.) hace referencia a una unidad de control configurable . Para ello, se ha previsto un juego de instrucciones con cierta capacidad de configuración. Para ciertas aplicaciones puede ser interesante cambiar el comportamiento de algunas instrucciones y para ello cada instrucción tiene un campo con atributos que cambia la respuesta de la unidad de control a dicha instrucción. La unidad de control interpreta dichos atributos y ejecuta esa instrucción de forma diferente en función del atributo. Es decir, el juego de instrucciones presenta unos campos especiales que son capaces de modificar algunas propiedades de esa unidad de control, como por ejemplo el tiempo que la instrucción tarda en ejecutarse. Esta funcionalidad está soportada por un hardware adicional en la unidad de control .WO-A-2007/015258 (Gopi, et al.) Refers to a configurable control unit. For this, an instruction set with a certain configuration capacity is planned. For certain applications it may be interesting to change the behavior of some instructions and for this each instruction has a field with attributes that changes the response of the control unit to that instruction. The control unit interprets these attributes and executes that instruction differently depending on the attribute. That is, the instruction set has special fields that are capable of modifying some properties of that control unit, such as the time it takes for the instruction to execute. This functionality is supported by additional hardware in the control unit.
DESCRIPCIÓN DE LA INVENCIÓNDESCRIPTION OF THE INVENTION
Un primer aspecto de la invención se refiere a un sistema microprocesador que comprende un microprocesador que comprende : (i) un camino de datos que comprende, al menos, una unidad aritmético-lógica, registros, una memoria de instrucciones configurada para contener instrucciones de un programa que el microprocesador debe ejecutar, y una memoria de datos configurada para contener datos con los que pueda operar el programa; yA first aspect of the invention relates to a microprocessor system comprising a microprocessor comprising: (i) a data path comprising at least one arithmetic-logic unit, registers, an instruction memory configured to contain instructions of a program that the microprocessor must execute, and a data memory configured to contain data with which can operate the program; Y
(ii) una unidad de control configurada para recibir instrucciones de programa de la memoria de instrucciones y para generar señales de control y aplicarlas al camino de datos de manera que se realicen, en el camino de datos, operaciones de acuerdo con las instrucciones de programa; esta unidad de control es una unidad de control cableada.(ii) a control unit configured to receive program instructions from the instruction memory and to generate control signals and apply them to the data path so that operations are performed in the data path in accordance with the program instructions ; This control unit is a wired control unit.
De acuerdo con la invención, el sistema está configurado para, como respuesta a una instrucción de reconfiguración contenida en las instrucciones de programa, reconfigurar la unidad de control, de manera que la unidad de control, que antes de recibir dicha instrucción de reconfiguración ' estaba configurada para que el microprocesador procese instrucciones de un programa compilado para una primera arquitectura de procesador, después de recibir dicha instrucción de reconfiguración se reconfigure para quedar configurada para que el microprocesador procese instrucciones de un programa compilado para una segunda arquitectura de procesador, distinta de la primera arquitectura de procesador.According to the invention, the system is configured to, in response to a reconfiguration instruction contained in the program instructions, reconfigure the control unit, so that the control unit, which before receiving said reconfiguration instruction ' was configured so that the microprocessor processes instructions of a compiled program for a first processor architecture, after receiving said reconfiguration instruction it is reconfigured to be configured so that the microprocessor processes instructions of a compiled program for a second processor architecture, other than the First processor architecture.
De esta manera, se consigue combinar la flexibilidad de los microprocesadores con unidad de control microprogramada con la rapidez y bajo consumo de los microprocesadores con unidad de control cableada. Es decir, se consigue un sistema que combina lo mejor de ambos conceptos. Por lo tanto, se puede, cuando sea conveniente, cambiar la configuración lógica de la unidad de control para que el microprocesador, que antes estaba configurado para procesar instrucciones de un programa compilado para una arquitectura de procesador, pase a estar configurado para procesar, correctamente, instrucciones de un programa compilado para otra arquitectura de procesador. Ejemplos de arquitecturas de procesador son: PowerPC, MIPS, Intel x86, SPARC, ARM, Alpha, etc.In this way, it is possible to combine the flexibility of the microprocessors with a microprogrammed control unit with the speed and low consumption of the microprocessors with a wired control unit. That is, you get a system that combines the best of both concepts. Therefore, you can, when convenient, change the logical configuration of the control unit so that the microprocessor, which was previously configured to process instructions of a compiled program for a processor architecture, becomes configured to process, correctly, instructions of a compiled program for another processor architecture . Examples of processor architectures are: PowerPC, MIPS, Intel x86, SPARC, ARM, Alpha, etc.
Por ejemplo: 1) En la arquitectura MIPS la instrucción de suma se codifica de la siguiente forma: add, rt,rs,rd rt=rs+rd donde rt es el registro destino (rl, r2 , r3) y rs,rd son los registros fuente. Se codifica como:For example: 1) In the MIPS architecture the summation instruction is coded as follows: add, rt, rs, rd rt = rs + rd where rt is the destination register (rl, r2, r3) and rs, rd are Source records It is coded as:
V000000 rs rd rt 00000 100000" (estando rs,rt y rd codificados con 5 bits) siendo por tanto la operación "add r3=r2+rl" como sigue: "000000 00001 00010 00011 00000 100000"V000000 rs rd rt 00000 100000 "(being rs, rt and rd encoded with 5 bits) being therefore the operation" add r3 = r2 + rl "as follows:" 000000 00001 00010 00011 00000 100000 "
2) En la arquitectura ARM la misma instrucción se codifica de la siguiente forma: "add Rd = Rn + Rm"2) In the ARM architecture the same instruction is coded as follows: "add Rd = Rn + Rm"
"1111 00 0 0100 0 Rn Rd 00000000 Rm" Por tanto "add r3=r2+rl" sería:"1111 00 0 0100 0 Rn Rd 00000000 Rm" Therefore "add r3 = r2 + rl" would be:
"1111 00 0 0100 0 0011 0010 00000000 0001" Por tanto, la "reconfiguración" de la unidad de control desde "compatibilidad" con MIPS a "compatibilidad" con ARM implica que si la unidad de control, antes de recibir la instrucción de reconfiguración, emitía un determinado conjunto de señales como respuesta a "000000 00001 00010 00011 00000 100000", después de la "reconfiguración debe generar las mismas señales de control como respuesta a"1111 00 0 0100 0 0011 0010 00000000 0001" Therefore, the "reconfiguration" of the control unit from "compatibility" with MIPS to "compatibility" with ARM implies that if the control unit, before receiving the reconfiguration instruction , emitted a certain set of signals in response to "000000 00001 00010 00011 00000 100000", after "reconfiguration you must generate the same control signals in response to
"1111 00 0 0100 0 0010 0010 00000000 0001". La invención puede servir como base para muchas aplicaciones interesantes, por ejemplo:"1111 00 0 0100 0 0010 0010 00000000 0001". The invention can serve as the basis for many interesting applications, for example:
- Ejecución de código de diferentes microprocesadores (es decir, de código compilado para. diferentes "arquitecturas" de microprocesador) . Se puede modificar la unidad de control al arrancar el microprocesador y a partir de entonces utilizarlo para un determinado tipo de código compilado, sin modificar la configuración durante la operación del microprocesador.- Execution of code of different microprocessors (that is, of compiled code for different microprocessor "architectures"). The control unit can be modified when the microprocessor is started and thereafter used for a certain type of compiled code, without changing the configuration during microprocessor operation.
- "Virtualización" -. La virtualización permite ejecutar código generado para otro procesador sobre una máquina diferente (es decir, sobre una máquina que en un principio no presenta la arquitectura correspondiente al código) . Se puede estar ejecutando código de las dos (o más) maquinas- "Virtualization" -. Virtualization allows to generate code generated for another processor on a different machine (that is, on a machine that initially does not present the architecture corresponding to the code). It may be running code of the two (or more) machines
(es decir, compilado para las dos -o más- arquitecturas) secuencialmente durante un mismo ciclo o período de funcionamiento del microprocesador, cambiando entre uno y otro. Con la invención resulta posible modificar, en tiempo de ejecución, la unidad de control, de tal forma que ambos códigos se ejecuten de forma nativa sobre el procesador sin apenas perdida de rendimiento (salvo la pérdida debida a la reprogramación o reconfiguración de la unidad de control) . En este caso puede ser necesario implementar un mecanismo que detenga la ejecución de instrucciones (y opcionalmente para vaciar el camino de datos y/o atender todas las interrupciones pendientes) mientras se lleva a cabo la reconfiguración (de manera que cualquier instrucción sea procesada por la "arquitectura" que corresponda) . - Aleatorización del juego de instrucciones: Por motivos de seguridad y para prevenir ataques DPA en sistemas con altos requerimientos de seguridad, puede ser interesante cambiar cada cierto tiempo la codificación del juego de instrucciones para evitar que un atacante pueda averiguar qué programa está ejecutando el microprocesador(that is, compiled for the two -or more- architectures) sequentially during the same cycle or period of operation of the microprocessor, switching between them. With the invention, it is possible to modify, at run time, the control unit, so that both codes are executed natively on the processor with hardly any loss of performance (except for the loss due to reprogramming or reconfiguration of the control unit). control) . In this case it may be necessary to implement a mechanism that stops the execution of instructions (and optionally to empty the data path and / or address all pending interruptions) while reconfiguration is carried out (so that any instruction is processed by the "architecture" that corresponds). - Randomization of the instruction set: For security reasons and to prevent DPA attacks on systems with high security requirements, it may be interesting to change the coding of the instruction set from time to time to prevent an attacker from finding out which program the microprocessor is running
(o qué datos está procesando) , analizando el consumo energético del mismo. (El ataque DPA -Differential Power(or what data you are processing), analyzing its energy consumption. (The DPA-Differential Power attack
Analysis- consiste en analizar el consumo del procesador para "adivinar" que instrucciones está ejecutando; cambiando la codificación del juego de instrucciones su consumo también varía, haciendo más difícil este tipo de ataque . )Analysis- consists of analyzing the consumption of the processor to "guess" what instructions you are executing; changing the coding of the instruction set its consumption also varies, making this type of attack more difficult. )
El sistema puede comprender una memoria que contenga al menos dos conjuntos de datos indicativos de respectivas configuraciones lógicas de la unidad de control. Además, el sistema puede comprender un dispositivo reconfigurador configurado para, como respuesta a la instrucción de reconfiguración, modificar la configuración de la unidad de control de acuerdo con los datos de uno de dichos conjuntos de datos .The system may comprise a memory containing at least two sets of data indicative of respective logical configurations of the control unit. In addition, the system may comprise a reconfiguration device configured to, in response to the reconfiguration instruction, modify the configuration of the control unit according to the data of one of said data sets.
La unidad de control puede estar implementada en un dispositivo de lógica programable . Ejemplos de dispositivos de lógica programable son: FPGA (Field Programmable Gate Array) , PLD (Programmable Logic Device) , CPLD (ComplexThe control unit may be implemented in a programmable logic device. Examples of programmable logic devices are: FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), CPLD (Complex
Programmable Logic Device) , PAL (Programmable Array Logic) , y GAL (Generic Array Logic) . Alternativamente, la unidad de control puede está implementada en un circuito ASICProgrammable Logic Device), PAL (Programmable Array Logic), and GAL (Generic Array Logic). Alternatively, the control unit may be implemented in an ASIC circuit.
("Application Specific Integrated Circuit") que comprende al menos una parte de lógica reconfigurable correspondiente a la unidad de control . El sistema puede estar configurado para cambiar la configuración de la unidad de control repetitivamente para, durante un período de funcionamiento, operar con programas compilados para diferentes arquitecturas, con el fin de dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema (y, por lo tanto, para dificultar "ataques DPA", tal y como se ha indicado más arriba) .("Application Specific Integrated Circuit") comprising at least one part of the reconfigurable logic corresponding to the control unit. The system may be configured to change the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, in order to make it difficult to analyze the operation of the microprocessor from a consumption analysis. energy system (and, therefore, to hinder "DPA attacks", as indicated above).
El sistema puede estar configurado para realizar cambios de la configuración de la unidad de control repetitivamente para, durante un período de funcionamiento, operar con programas compilados para diferentes arquitecturas, realizándose dichos cambios de forma aleatoria o pseudoaleatoria. La "aleatorización" se puede referir a la frecuencia con la que se realizan los cambios de configuración y/o a los momentos en los que se producen los cambios de configuración, y/o a cuál será la nueva configuración que se selecciona, entre las diferentes configuraciones disponibles (por ejemplo, en una memoria del sistema) . Es decir, el momento en el que se produce el cambio de configuración se puede determinar de forma aleatoria (o pseudoaleatoria) , y/o la configuración a la que se cambia puede ser elegida de forma aleatoria (o pseudoaleatoria) . Este aspecto de la invención puede tener aplicaciones interesantes en, por ejemplo, el campo de la seguridad.The system may be configured to make changes to the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, such changes being made randomly or pseudorandomly. "Randomization" can refer to the frequency with which the configuration changes are made and / or at the times when the configuration changes occur, and / or to what new configuration will be selected, among the different configurations available (for example, in a system memory). That is, the time at which the configuration change occurs can be determined randomly (or pseudo-randomly), and / or the configuration to which it is changed can be chosen randomly (or pseudo-randomly). This aspect of the invention may have interesting applications in, for example, the field of security.
Otro aspecto de la invención se refiere a un método para operar un microprocesador (por ejemplo, del tipo descrito más arriba), cuyo microprocesador comprende: un camino de datos que comprende, al menos, una unidad aritmético-lógica, registros,- una memoria de instrucciones configurada para contener instrucciones de un programa • que el microprocesador debe ejecutar, y una memoria de datos configurada para contener datos con los que pueda operar el programa; y una unidad de control configurada para recibir instrucciones de programa de la memoria de instrucciones y para generar señales de control y aplicarlas al camino de datos de manera que se realicen, en el camino de datos, operaciones de acuerdo con las instrucciones de programa, siendo la unidad de control una unidad de control cableada. De acuerdo con la invención, el método comprende los pasos de como respuesta a una instrucción de reconfiguración contenida en las instrucciones de programa, reconfigurar la unidad de control, de manera que la unidad de control - pase de estar configurada para que el microprocesador procese instrucciones de un programa compilado para una primera arquitectura de procesador,Another aspect of the invention relates to a method for operating a microprocessor (for example, of the type described above), whose microprocessor comprises: a data path comprising at least one arithmetic-logic unit, registers, - a memory instruction set to contain instructions from a program • that the microprocessor must execute, and a data memory configured to contain data with which the program can operate; and a control unit configured to receive program instructions from the instruction memory and to generate control signals and apply them to the data path so that operations are performed in the data path according to the program instructions, being the control unit a wired control unit. According to the invention, the method comprises the steps of in response to a reconfiguration instruction contained in the program instructions, reconfiguring the control unit, so that the control unit - goes from being configured so that the microprocessor processes instructions of a compiled program for a first processor architecture,
- a estar configurada para que el microprocesador procese instrucciones de un programa compilado para una segunda arquitectura de procesador, distinta de la primera arquitectura de procesador.- to be configured for the microprocessor to process instructions from a compiled program for a second processor architecture, other than the first processor architecture.
Lo que se ha dicho más arriba con respecto al sistema de la invención también aplica al método, mutatis mutandis .What has been said above with respect to the system of the invention also applies to the method, mutatis mutandis.
El paso de reconfigurar la unidad de control se puede realizar accediendo a datos indicativos de configuración lógica de la unidad de control . Estos datos pueden estar alojados en una memoria en la que están alojados al menos dos conjuntos de datos indicativos de respectivas configuraciones lógicas de la unidad de control . Por ejemplo, como respuesta a la instrucción de reconfiguración, se puede acceder a uno de dichos conjuntos de datos (por ejemplo, accediendo a una posición de memoria indicada en la instrucción de rec'onfiguración) y, mediante un dispositivo hardware (por ejemplo) , se puede reconfigurar la unidad de control de acuerdo con dicho conjunto de datos. La reconfiguración se puede realizar sobre una unidad de control implementada en un dispositivo de lógica programable, o sobre una unidad de control implementada en un circuito ASIC que comprende al menos una parte de lógica reconfigurable correspondiente a la unidad de control. El método puede comprender el paso de reconfigurar repetitivamente (por ejemplo, de forma aleatoria o pseudoaleatoria, . en cuanto a los momentos en los que se reconfigura y/o en cuanto a cuál será la nueva configuración) la unidad de control para que el microprocesador opere, en diferentes momentos de un periodo de funcionamiento del microprocesador, con programas compilados para diferentes arquitecturas de microprocesador .The step of reconfiguring the control unit can be performed by accessing data indicative of the logical configuration of the control unit. This data may be housed in a memory in which at least two sets of data indicative of respective logical configurations of the control unit are housed. For example, in response to the reconfiguration instruction, one of said data sets can be accessed (for example, by accessing a memory location specified in the instruction of rec 'ONFIGURATION) and, through a hardware (for example) device can reconfigure the control unit according to said data set. The reconfiguration can be performed on a control unit implemented in a programmable logic device, or on a control unit implemented in an ASIC circuit comprising at least a part of reconfigurable logic corresponding to the control unit. The method may comprise the step of reconfiguring repetitively (for example, randomly or pseudorandomly, in terms of the moments in which it is reconfigured and / or as to what the new configuration will be) the control unit for the microprocessor Operate, at different times of a microprocessor operating period, with compiled programs for different microprocessor architectures.
El método puede comprender el paso de, como respuesta a la instrucción de reconfiguración pero antes reconfigurar la unidad de control, terminar el procesamiento de instrucciones recibidas antes de la recepción de la instrucción de reconfiguración, por ejemplo, para garantizar que cada instrucción sea procesada por la "arquitectura" que le corresponda.The method may comprise the step of, in response to the reconfiguration instruction but before reconfiguring the control unit, to terminate the processing of instructions received prior to the reception of the reconfiguration instruction, for example, to ensure that each instruction is processed by the "architecture" that corresponds.
Otro aspecto de la invención se refiere al uso de un dispositivo según lo que se ha descrito más arriba, para dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema (algo que puede servir para dificultar "ataques DPA") .Another aspect of the invention relates to the use of a device according to what has been described above, to hinder an analysis of the operation of the microprocessor from an analysis of the energy consumption of the system (something that can serve to hinder "DPA attacks ").
De la misma manera, otro aspecto de la invención se refiere al uso del método descrito, con el fin de dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema.In the same way, another aspect of the invention relates to the use of the described method, in order to make it difficult to analyze the operation of the microprocessor based on an analysis of the energy consumption of the system.
DESCRIPCIÓN DE LAS FIGURAS Para complementar la descripción y con objeto de ayudar a una mejor comprensión de las características de la invención, de acuerdo con un ejemplo preferente de realización práctica de la misma, se acompaña como parte integrante de la descripción, un juego de figuras en el que con carácter ilustrativo y no limitativo, se ha representado lo siguiente:DESCRIPTION OF THE FIGURES To complement the description and in order to help a better understanding of the characteristics of the invention, according to a preferred example of practical implementation thereof, a set of figures is accompanied as an integral part of the description in which, as an illustration and not limitation, the following has been represented:
La figura 1.- Muestra una vista esquemática de un sistema de acuerdo con una posible realización de la invención. La figura 2. - Muestra una vista esquemática de un dispositivo reconfigurador y su relación con una memoria principal y con la unidad de control del sistema.Figure 1 shows a schematic view of a system according to a possible embodiment of the invention. Figure 2. - Shows a schematic view of a reconfiguring device and its relationship with a main memory and with the system control unit.
La figura 3.- Muestra un flujograma que refleja una posible forma de llevar a cabo el método de la invención.Figure 3.- Shows a flowchart that reflects a possible way of carrying out the method of the invention.
REALIZACIÓN PREFERENTE DE LA INVENCIÓNPREFERRED EMBODIMENT OF THE INVENTION
En la figura 1 se refleja, de forma esquemática, una realización preferida de la invención, con un microprocesador que comprende un camino de datos 1 (que puede ser convencional) comprendiendo un contador de programa 11 (que lleva la cuenta de cual es la próxima instrucción del programa a ejecutar) , memoria (cache) de instrucciones 12, banco de registros 13, unidad aritmético- lógica 14, memoria (cache) de datos 15, multiplexores 16 (sólo se ha ilustrado uno), etc. Por otra parte, el microprocesador comprende una unidad de control 2 cableada. La unidad de control genera, como respuesta a las instrucciones que recibe de la memoria de instrucciones 12, señales que se aplican al camino de datos 1 para realizar las operaciones correspondientes. Todo esto' es convencional y no se considera necesario describirlo aquí con más detalle.A preferred embodiment of the invention is schematically shown in Figure 1, with a microprocessor comprising a data path 1 (which can be conventional) comprising a program counter 11 (which takes account of which is the next instruction of the program to be executed), instruction memory (cache) 12, register bank 13, arithmetic-logic unit 14, memory (cache) of data 15, multiplexers 16 (only one illustrated), etc. On the other hand, the microprocessor comprises a wired control unit 2. The control unit generates, in response to the instructions that you receive from instruction memory 12, signals that are applied to data path 1 to perform the corresponding operations. All this is conventional and it is not considered necessary to describe it here in more detail.
El sistema comprende también una memoria 3, a continuación denominada "memoria principal", algo que también es convencional en este tipo de sistemas.The system also comprises a memory 3, hereinafter referred to as "main memory", something that is also conventional in this type of systems.
Ahora bien, de acuerdo con la invención, esta memoria principal 3 incluye juegos o conjuntos de datos indicativos de configuraciones lógicas diferentes de la unidad de control 2 , en el sentido de que dependiendo de si la unidad de control 2 está configurada de acuerdo con uno u otro de dichos conjuntos de datos, el microprocesador (es decir, el ' conjunto de unidad de control 2 y camino de datos 1) puede procesar, correctamente, instrucciones de un programa compilado para una u otra arquitectura de procesador.However, according to the invention, this main memory 3 includes sets or sets of data indicative of logical configurations different from the control unit 2, in the sense that depending on whether the control unit 2 is configured according to one or another of said data sets, the microprocessor (that is, the 'control unit set 2 and data path 1) can correctly process instructions from a compiled program for one or another processor architecture.
Por otra parte, el sistema incluye un elemento, subsistema o dispositivo reconfigurador 4 que también puede actuar como respuesta a las instrucciones que llegan desde la memoria de instrucciones . Al recibir (de forma directa o indirecta, por ejemplo, como en la figura 2, a través de la unidad de control 2) una instrucción determinada, que a continuación denominamos "instrucción de reconfiguración" , el dispositivo reconfigurador accede a la memoria principalOn the other hand, the system includes an element, subsystem or reconfiguring device 4 that can also act in response to the instructions arriving from the instruction memory. Upon receiving (directly or indirectly, for example, as in Figure 2, through the control unit 2) a specific instruction, which we now call "reconfiguration instruction", the reconfiguration device accesses the main memory
(por ejemplo, a una posición en la memoria principal indicada por la "instrucción de reconfiguración" ; esta posición puede estar indicada en un campo de la(for example, to a position in the main memory indicated by the "reconfiguration instruction"; this position may be indicated in a field of the
"instrucción de reconfiguración") y accede allí a uno de los mencionados "conjuntos de datos", para luego acceder a la unidad de control y provocar una reconfiguración de la misma, de acuerdo con dicho conjunto de datos. Para ello, la unidad de control está implementada sobre hardware de lógica reconfigurable, por ejemplo, sobre un dispositivo FPGA (Field Programmable Gate Array) , PLD"reconfiguration instruction") and access there one of the aforementioned "data sets", then access the control unit and cause a reconfiguration thereof, according to said data set. For this, the control unit is implemented on reconfigurable logic hardware, for example, on an FPGA (Field Programmable Gate Array), PLD device
(Programmable Logic Device) , CPLD (Complex Programmable Logic Device) , PAL (Programmable Array Logic) o GAL(Programmable Logic Device), CPLD (Complex Programmable Logic Device), PAL (Programmable Array Logic) or GAL
(Generic Array Logic) , o sobre un ASIC (Application(Generic Array Logic), or on an ASIC (Application
Specific Integrated Circuit) que comprende al menos una parte de lógica reconfigurable .Specific Integrated Circuit) comprising at least one part of reconfigurable logic.
La figura 2 refleja esquemáticamente cómo el dispositivo reconfigurador 4, que puede estar implementado con hardware y comprender un controlador de bus, es capaz de conectarse al bus 5 del sistema y leer datos de la memoria principal 3. Por ejemplo, como respuesta a una "instrucción de reconfiguración" 200, la unidad de control 2 (implementada sobre hardware de lógica configurable 21) genera, en adición a (o en lugar de) las señales de control 201 que aplica al camino de datos 1, una señal o instrucción 202 indicativa de que debe producirse una reconfiguración de la unidad de control, acompañada por (o incluyendo) una indicación 202A de la posición en la memoria principal 3 donde empieza el conjunto de datos que define la .nueva configuración de la unidad de control 2. Como respuesta a dicha señal o instrucción 202, el dispositivo reconfigurador 4 accede, a través del bus 5, a la memoria principal 3, lee allí el conjunto de datos que definen la nueva configuración de la unidad de control, y vuelca dicha nueva configuración en la lógica programable 21, a través de una puerta de reconfiguración 22. Por ejemplo, en el caso de un dispositivo FPGA del fabricante Xilinx®, esto se puede hacer a través de su puerta ICAP (Internal Configuration Access Port) . Es decir, "volcando" la nueva configuración correspondiente al conjunto de datos obtenido en la memoria principal 3 (en la posición o área indicada por la instrucción de reconfiguración 200) , se modifica la "arquitectura" del microprocesador y, por lo tanto, puede quedar configurado para procesar un nuevo tipo de programas compilados.Figure 2 schematically reflects how the reconfigurator device 4, which can be implemented with hardware and comprise a bus controller, is able to connect to bus 5 of the system and read data from main memory 3. For example, in response to a " reconfiguration instruction "200, the control unit 2 (implemented on configurable logic hardware 21) generates, in addition to (or instead of) the control signals 201 that it applies to data path 1, an indicative signal or instruction 202 that a reconfiguration of the control unit must occur, accompanied by (or including) an indication 202A of the location in main memory 3 where the data set that defines the new configuration of the control unit 2 begins. In response to said signal or instruction 202, the reconfiguring device 4 accesses, via bus 5, the main memory 3, reads there the data set defining the new configuration of the control unit, and dumps said new configuration into programmable logic 21, through a reconfiguration gate 22. For example, in the case of an FPGA device of the manufacturer Xilinx ® , this can be done through its ICAP gate (Internal Configuration Access Port). That is, "dump" the new configuration corresponding to the data set obtained in main memory 3 (in the position or area indicated by the reconfiguration instruction 200), the "architecture" of the microprocessor is modified and, therefore, can be configured to process a new type of compiled programs.
La figura 3 refleja, esquemáticamente, cómo se puede implementar la invención.Figure 3 schematically reflects how the invention can be implemented.
Tanto la unidad de control 2 como el dispositivo de reconfiguración 4 están continuamente buscando nuevas instrucciones a su entrada, a donde las instrucciones llegan desde la memoria de instrucciones 12 con el ritmo que marca el contador de programa 11. Una vez que se detecta una nueva instrucción (paso 100) , ésta se decodifica (paso 101) y se comprueba (paso 102) si se trata de una "instrucción de reconfiguracón" . Si no se trata de una "instrucción de reconfiguración" , la unidad de control ejecuta (paso 103) la instrucción de forma convencional, y el procesador pasa a buscar la siguiente instrucción.Both the control unit 2 and the reconfiguration device 4 are continuously looking for new instructions at their input, where the instructions arrive from the instruction memory 12 at the rate set by the program counter 11. Once a new one is detected instruction (step 100), this is decoded (step 101) and checked (step 102) if it is a "reconfiguration instruction". If it is not a "reconfiguration instruction", the control unit executes (step 103) the instruction in a conventional manner, and the processor proceeds to search for the next instruction.
Ahora bien, si se trata de una instrucción de reconfiguración, el microprocesador pasa a ejecutar las interrupciones pendientes (paso 104) y a vaciar el camino de datos (paso 105) , y el dispositivo de reconfiguraciónHowever, if it is a reconfiguration instruction, the microprocessor starts executing the pending interrupts (step 104) and emptying the data path (step 105), and the reconfiguration device
(en el paso 106 que puede ejecutarse después, antes o a la vez con los pasos 104-105) lee (el conjunto de datos indicativo de) la nueva configuración de la unidad de control 2 de la memoria principal 4 y vuelca (en el paso 107, que preferiblemente se realice después del pasó 105) dicha nueva configuración en la unidad de control 2 , quedando la misma por lo tanto reconfigurada. Básicamente, el funcionamiento podría ser el siguiente: El procesador está ejecutando un juego de instrucciones determinado contenido en la memoria de instrucciones 12. Dentro de ese juego de instrucciones existe una instrucción de reconfiguración y que básicamente sirve para "activar" el dispositivo de reconfiguración 4(in step 106 which can be executed after, before or at the same time with steps 104-105) read (the data set indicative of) the new configuration of control unit 2 of main memory 4 and dump (in step 107, which is preferably carried out after step 105) said new configuration in the control unit 2, being therefore reconfigured. Basically, the operation could be as follows: The processor is executing a certain instruction set contained in instruction memory 12. Within that instruction set there is a reconfiguration instruction and which basically serves to "activate" the reconfiguration device 4
(implementado en hardware) e indicarle la posición de la memoria principal 3 en la que comienza el conjunto de datos que corresponde a la nueva configuración de la unidad de control 2. - Cuando se ejecute dicha instrucción el procesador(implemented in hardware) and indicate the position of the main memory 3 at which the data set that corresponds to the new configuration of the control unit 2 begins. - When said instruction is executed the processor
(unidad de control 2 y camino de datos 1) termina todo lo que está haciendo hasta ese punto, atendiendo todas las interrupciones pendientes y vaciando el camino de datos.(control unit 2 and data path 1) ends everything you are doing up to that point, addressing all pending interruptions and emptying the data path.
(Como es sabido, las interrupciones en el sistema funcionan para atender eventos externos. Por ejemplo, cuando se pulsa una tecla en el procesador se activa una interrupción y se salta a una posición de memoria preestablecida para ese evento donde se encuentra el programa que hay que ejecutar en caso de que se pulse dicha tecla. Cuando se quiere reconfigurar la unidad de control para, básicamente, convertir la "arquitectura" del procesador en otra, aparte de cambiar el juego de instrucciones puede ser necesario cambiar la numeración de las interrupciones y la posición de memoria a la que hay que saltar cuando se produce el evento correspondiente. Esto se puede hacer modificando una tabla, que puede estar junto a la unidad de control.) De esta manera se deja el procesador en un estado conocido sin" nada pendiente de tal forma que al reiniciarlo con la nueva configuración de la unidad de control, no queden instrucciones codificadas de otra manera (es decir, correspondientes a la "arquitectura" anterior) por ejecutar. Si se cambia la configuración de la unidad de control y quedan eventos externos por atender -que lanzan interrupciones en el procesador- puede haber un riesgo de que se puedan mezclar instrucciones correspondientes a configuraciones -o "arquitecturas"- diferentes. Por eso puede ser conveniente dejar el procesador en un estado en el que no tenga nada de trabajo pendiente (y en caso de que el camino de datos esté segmentado, algo que es habitual, se termina de procesar todas las instrucciones anteriores a la instrucción de reconfiguraciδn) . - Una vez parado el procesador, el elemento reconfigurador 4 comienza a leer de la memoria principal 3 la nueva configuración de la unidad de control y a reconfigurar dicha unidad de control sobre el hardware reconfigurable correspondiente . En este texto, la palabra "comprende" y sus variantes (como "comprendiendo", etc.) no deben interpretarse de forma excluyente, es decir, no excluyen la posibilidad de que lo descrito incluya otros elementos, pasos etc.(As is known, interruptions in the system work to handle external events. For example, when a key is pressed on the processor an interrupt is activated and skips to a preset memory location for that event where the program is located to be executed if the key is pressed. When you want to reconfigure the control unit to basically convert the "architecture" of the processor into another, apart from changing the instruction set it may be necessary to change the numbering of the interruptions and the memory position to jump to when the corresponding event occurs. This can be done by modifying a table, which can be next to the control unit.) In this way the processor is left in a known state without "anything pending in such a way that when restarting it with the new configuration of the control unit, there are no instructions otherwise coded (ie, corresponding to the "a architecture "above) to be executed. If the unit configuration is changed control and external events remain to be addressed - which throw interruptions in the processor - there may be a risk that instructions corresponding to different configurations - or "architectures" - can be mixed. Therefore, it may be convenient to leave the processor in a state in which it has no pending work (and in case the data path is segmented, which is usual, all instructions prior to the instruction of the instruction are finished). reconfiguration). - Once the processor is stopped, the reconfiguring element 4 begins to read from the main memory 3 the new configuration of the control unit and reconfiguring said control unit on the corresponding reconfigurable hardware. In this text, the word "comprises" and its variants (such as "understanding", etc.) should not be construed as excluding, that is, they do not exclude the possibility that what is described includes other elements, steps etc.
Por otra parte, la invención no está limitada a las realizaciones concretas que se han descrito sino abarca también, por ejemplo, las variantes que pueden ser realizadas por el experto medio en la materia (por ejemplo, en cuanto a la elección de materiales, dimensiones, componentes, configuración, etc.), dentro de lo que se desprende de las reivindicaciones. On the other hand, the invention is not limited to the specific embodiments that have been described but also covers, for example, the variants that can be made by the average person skilled in the art (for example, in terms of the choice of materials, dimensions , components, configuration, etc.), within what follows from the claims.

Claims

REIVINDICACIONES
1. - Sistema microprocesador que comprende un microprocesador que comprende: un camino de datos (1) que comprende, al menos, una unidad aritmético-lógica (14) , registros (13) , una memoria de instrucciones (12) configurada para contener instrucciones de un programa que el microprocesador debe1. - Microprocessor system comprising a microprocessor comprising: a data path (1) comprising at least one arithmetic-logic unit (14), registers (13), an instruction memory (12) configured to contain instructions of a program that the microprocessor must
• ejecutar, y una memoria de datos (15) configurada para contener datos con los que pueda operar el programa; y una unidad de control (2) configurada para recibir instrucciones de programa de la memoria de instrucciones (12) y para generar señales de control y aplicarlas al camino de datos (1) de manera que se realicen, en el camino de datos, operaciones de acuerdo con las instrucciones de programa; siendo la unidad de control (2) una unidad de control cableada; caracterizado. porque el sistema está configurado para, como respuesta a una instrucción de reconfiguración (200) contenida en las instrucciones de programa, reconfigurar la unidad de control, de manera que la unidad de control, antes de recibir dicha instrucción de reconfiguración, está configurada para que el microprocesador procese instrucciones de un programa compilado para una primera arquitectura de procesador, y después de recibir dicha instrucción de reconfiguración, se reconfigure para quedar configurada para que el microprocesador procese instrucciones de un programa compilado para una segunda arquitectura de procesador, distinta de la primera arquitectura de procesador. • execute, and a data memory (15) configured to contain data with which the program can operate; and a control unit (2) configured to receive program instructions from the instruction memory (12) and to generate control signals and apply them to the data path (1) so that operations, in the data path, are performed according to the program instructions; the control unit (2) being a wired control unit; characterized. because the system is configured to, in response to a reconfiguration instruction (200) contained in the program instructions, reconfigure the control unit, so that the control unit, before receiving said reconfiguration instruction, is configured so that The microprocessor processes instructions of a compiled program for a first processor architecture, and after receiving said reconfiguration instruction, it is reconfigured to be configured so that the microprocessor processes instructions of a compiled program for a second processor architecture, other than the first processor architecture
2.- Sistema según la reivindicación 1, caracterizado porque comprende una memoria (3) que contiene ai menos dos conjuntos de datos indicativos de respectivas configuraciones lógicas de la unidad de control (2) .2. System according to claim 1, characterized in that it comprises a memory (3) containing at least two sets of data indicative of respective logical configurations of the control unit (2).
3.- Sistema según la reivindicación 2, caracterizado porque comprende un dispositivo reconfigurador (4) configurado para, como respuesta a la instrucción de reconfiguración, modificar la configuración de la unidad de control de acuerdo con los datos de uno de dichos conjuntos de datos.3. System according to claim 2, characterized in that it comprises a reconfiguration device (4) configured to, in response to the reconfiguration instruction, modify the configuration of the control unit according to the data of one of said data sets.
4. - Sistema según cualquiera de las reivindicaciones anteriores, caracterizado porque la unidad de control está implementada en un dispositivo de lógica programable.4. - System according to any of the preceding claims, characterized in that the control unit is implemented in a programmable logic device.
5.- Sistema según cualquiera de las reivindicaciones 1-3, caracterizado porque la unidad de control está implementada en un circuito ASIC • que comprende al menos una parte de lógica reconfigurable correspondiente a la unidad de control .5. System according to any of claims 1-3, characterized in that the control unit is implemented in an ASIC circuit • comprising at least a part of reconfigurable logic corresponding to the control unit.
6.- Sistema según cualquiera de las reivindicaciones anteriores, caracterizado porque está configurado para cambiar la configuración de la unidad de control repetitivamente para, durante un período de funcionamiento, operar con programas compilados para diferentes arquitecturas, con el fin de dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema. 6. System according to any of the preceding claims, characterized in that it is configured to change the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, in order to hinder an analysis of the Microprocessor operation based on an analysis of the energy consumption of the system.
7.- Sistema según cualquiera de las reivindicaciones- anteriores, caracterizado porque está configurado para realizar cambios • de la configuración de la unidad de control repetitivamente para, durante un período de funcionamiento, operar con programas compilados para diferentes arquitecturas, realizándose dichos cambios de forma aleatoria o pseudoaleatoria.7. System according to any of the preceding claims, characterized in that it is configured to make changes in the configuration of the control unit repetitively to, during a period of operation, operate with compiled programs for different architectures, such changes being made in a way random or pseudorandom.
8.- Método para operar un microprocesador que comprende: un camino de datos (1) que comprende, al menos, una unidad aritmético-lógica (14) , registros (13) , una memoria de instrucciones (12) configurada para contener instrucciones de un programa que el microprocesador debe ejecutar, y una memoria de datos (15) configurada para contener datos con los que pueda operar el programa; y una unidad' de control (2) configurada para recibir instrucciones de programa de la memoria de instrucciones8. Method for operating a microprocessor comprising: a data path (1) comprising at least one arithmetic-logic unit (14), registers (13), an instruction memory (12) configured to contain instructions for a program that the microprocessor must execute, and a data memory (15) configured to contain data with which the program can operate; and a control unit (2) configured to receive program instructions from the instruction memory
(12) y para generar señales de control y aplicarlas al camino de datos (1) de manera que se realicen, en el camino de datos, operaciones de acuerdo con las instrucciones de programa ; siendo la unidad de control (2) una unidad de control cableada; caracterizado porque el método comprende los pasos de como respuesta a una instrucción de reconfiguración (200) contenida en las instrucciones de programa, reconfigurar la unidad de control, de manera que la unidad de control - pase de estar configurada para que el microprocesador procese instrucciones de un programa compilado para una primera arquitectura de procesador, - .a estar configurada para que el microprocesador procese instrucciones de un programa compilado para una segunda arquitectura de procesador, distinta de la primera arquitectura de procesador.(12) and to generate control signals and apply them to the data path (1) so that operations are performed in the data path according to the program instructions; the control unit (2) being a wired control unit; characterized in that the method comprises the steps of in response to a reconfiguration instruction (200) contained in the program instructions, reconfiguring the control unit, so that the control unit - goes from being configured so that the microprocessor processes instruction instructions. a compiled program for a first processor architecture, - .to be configured for the microprocessor to process instructions from a compiled program for a second processor architecture, other than the first processor architecture.
9.- Método según la reivindicación 8, caracterizado porque el paso de reconfigurar la unidad de control se realiza accediendo a datos indicativos de configuración lógica de la unidad de control alojados en una memoria (3) que contiene al menos dos conjuntos de datos indicativos de respectivas configuraciones lógicas de la unidad de control .9. Method according to claim 8, characterized in that the step of reconfiguring the control unit is performed by accessing data indicative of logical configuration of the control unit housed in a memory (3) containing at least two sets of data indicative of respective logical configurations of the control unit.
10.- Método según la reivindicación 9, caracterizado porque como respuesta a la instrucción de reconfiguración se accede a uno de dichos conjuntos de datos y, mediante un dispositivo hardware, se reconfigura la unidad de control de acuerdo con dicho conjunto de datos.10. Method according to claim 9, characterized in that in response to the reconfiguration instruction one of said data sets is accessed and, by means of a hardware device, the control unit is reconfigured according to said data set.
11.- Método según cualquiera de las reivindicaciones 8-10, caracterizado porque la reconfiguración se realiza sobre una unidad de control implementada en un dispositivo de lógica programable.11. Method according to any of claims 8-10, characterized in that the reconfiguration is performed on a control unit implemented in a programmable logic device.
12.- Método según cualquiera de las reivindicaciones 8-10, caracterizado porque la reconfiguración se realiza sobre una unidad de control implementada en un circuito ASIC que comprende al menos una parte de lógica reconfigurable correspondiente a la unidad de control .12. Method according to any of claims 8-10, characterized in that the reconfiguration is carried out on a control unit implemented in an ASIC circuit comprising at least a part of reconfigurable logic corresponding to the control unit.
13.- Método según cualquiera de las reivindicaciones 8-12, que comprende el paso de reconfigurar repetitivamente la unidad de control para que el microprocesador opere, en diferentes momentos de un periodo de funcionamiento del microprocesador, con programas compilados para diferentes arquitecturas de microprocesador.13. Method according to any of claims 8-12, comprising the step of repeatedly reconfiguring the control unit for the microprocessor to operate, at different times during a period of operation of the microprocessor, with compiled programs for different microprocessor architectures.
14.- Método según la reivindicación 13, caracterizado porque durante dicho período de funcionamiento se reconfigura la unidad de control de forma aleatoria o pseudoaleatoria .14. Method according to claim 13, characterized in that during said period of operation the control unit is reconfigured randomly or pseudorandomly.
15.- Método según cualquiera de las reivindicaciones 8-14, que comprende el paso de, como respuesta a la instrucción de reconfiguración pero antes reconfigurar la unidad de control, terminar el procesamiento de instrucciones recibidas antes de la recepción de la instrucción de reconfiguración .15. Method according to any of claims 8-14, comprising the step of, in response to the reconfiguration instruction but before reconfiguring the control unit, to finish the processing of instructions received before the reconfiguration instruction is received.
16.- Uso de un dispositivo según cualquiera de las reivindicaciones 1-7, para dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema.16. Use of a device according to any of claims 1-7, to make it difficult to analyze the operation of the microprocessor based on an analysis of the energy consumption of the system.
17.- Uso del método según cualquiera de las reivindicaciones 8-15, con el fin de dificultar un análisis de la operación del microprocesador a partir de un análisis del consumo energético del sistema. 17. Use of the method according to any of claims 8-15, in order to make it difficult to analyze the operation of the microprocessor based on an analysis of the energy consumption of the system.
PCT/ES2009/000396 2008-07-28 2009-07-27 Microprocessor system including a reconfigurable hardwired control unit and method for operating a microprocessor WO2010018254A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5774686A (en) * 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5774686A (en) * 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor

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