WO2009143126A3 - Integrated circuit package having integrated faraday shield - Google Patents

Integrated circuit package having integrated faraday shield Download PDF

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Publication number
WO2009143126A3
WO2009143126A3 PCT/US2009/044480 US2009044480W WO2009143126A3 WO 2009143126 A3 WO2009143126 A3 WO 2009143126A3 US 2009044480 W US2009044480 W US 2009044480W WO 2009143126 A3 WO2009143126 A3 WO 2009143126A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
packaged
integrated
layers
integrated circuit
Prior art date
Application number
PCT/US2009/044480
Other languages
French (fr)
Other versions
WO2009143126A2 (en
Inventor
Stanley Craig Beddingfield
Jean-Francois Drouard
Original Assignee
Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Priority to CN2009801025126A priority Critical patent/CN101919053B/en
Publication of WO2009143126A2 publication Critical patent/WO2009143126A2/en
Publication of WO2009143126A3 publication Critical patent/WO2009143126A3/en

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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

A packaged integrated circuit (IC) (100) includes a first substrate (110) comprising a first plurality of layers and a first circuit coupling features (112) at an upper surface of the first substrate, the first plurality of layers including a first electromagnetic interference shielding layer (132). The packaged IC also includes a second substrate (106) having an upper surface attached to a lower surface of the first substrate by an electrically conductive adhesive material (136). The second substrate includes a second plurality of layers and a second circuit coupling feature (108) at a lower surface of the second substrate. The first plurality of layer includes a second EMI shielding layer (134). The packaged IC further includes a functional die (124) disposed between the first and the second substrates and functionally coupled to the first and/or the second circuit coupling features. In the packaged IC, the adhesive material electrically couples the first and the second shielding layers.
PCT/US2009/044480 2008-05-19 2009-05-19 Integrated circuit package having integrated faraday shield WO2009143126A2 (en)

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CN2009801025126A CN101919053B (en) 2008-05-19 2009-05-19 Integrated circuit package having integrated faraday shield

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US12/123,115 US7741567B2 (en) 2008-05-19 2008-05-19 Integrated circuit package having integrated faraday shield
US12/123,115 2008-05-19

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WO2009143126A2 WO2009143126A2 (en) 2009-11-26
WO2009143126A3 true WO2009143126A3 (en) 2010-02-25

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US (2) US7741567B2 (en)
CN (1) CN101919053B (en)
TW (1) TW201013882A (en)
WO (1) WO2009143126A2 (en)

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US20100214759A1 (en) 2010-08-26
TW201013882A (en) 2010-04-01
US7741567B2 (en) 2010-06-22
CN101919053A (en) 2010-12-15
US8049119B2 (en) 2011-11-01
WO2009143126A2 (en) 2009-11-26
CN101919053B (en) 2013-02-13
US20090284947A1 (en) 2009-11-19

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