WO2009128800A1 - Silicon nanowire and composite formation and highly pure and uniform length silicon nanowires - Google Patents

Silicon nanowire and composite formation and highly pure and uniform length silicon nanowires Download PDF

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WO2009128800A1
WO2009128800A1 PCT/US2008/004983 US2008004983W WO2009128800A1 WO 2009128800 A1 WO2009128800 A1 WO 2009128800A1 US 2008004983 W US2008004983 W US 2008004983W WO 2009128800 A1 WO2009128800 A1 WO 2009128800A1
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silicon
nanowires
etching
silver
silicon nanowires
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PCT/US2008/004983
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French (fr)
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Munir H. Nayeeh
Sommaya Shams
Osama M. Nayfeh
Dimitri Antoniadis
Kevin Mantey
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The Board Of Trustees Of The University Of Illinois
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Priority to PCT/US2008/004983 priority Critical patent/WO2009128800A1/en
Publication of WO2009128800A1 publication Critical patent/WO2009128800A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

Definitions

  • FIELD A field of the invention is silicon nanowires and composites.
  • Silicon nanowires offer the promise of operational speeds that far exceed present state of the art solid state electronic devices. Silicon nanowires have the advantage of being compatible with existing process technology in the integrated circuit industry. When fabrication issues are solved, silicon nanowires will be used to form many electronic devices, such as field effect transistors (FETs), diodes, and logic gates. Such devices will incorporate silicon nanowires as charge carriers that will operate under physics laws of quantum mechanics. The potential exists for silicon nanowires to be powerful building blocks for nanoelectronics devices if the nanowires can be fabricated with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping. Silicon nanowire based devices should eventually form an important alternative to conventional planar technology. A silicon nanowire based FET, for example, will provide improved electrostatic control of the channel via the gate voltage and better suppression of short channel effects than conventional planar technology.
  • silicon nanowires are as biosensors for the real-time detection of biological molecules (i.e. DNA, RNA, proteins). Such sensors are based on the fact that changes in conduction occur when a charged object is brought in close proximity to the silicon nanowire surface.
  • Efforts to fabricate silicon nanowires that have been used in the art include chemical vapor deposition (CVD), pulsed laser vaporization (PLV), and thermal evaporation (TE).
  • CVD and vapor-liquid-solid PLV require catalysts, while oxide-assisted thermal evaporation is catalyst free.
  • a catalyst free technique provides a likely important advantage in terms of purity control, especially for avoiding trace metals.
  • Silicon nanowires fabricated by CVD are now grown on surfaces catalyzed by metal nanoparticles, such as gold nanoparticles. With this technique, there is marginal control over the length, direction and straightness or curvature of the silicon nanowires that form.
  • the cross section is governed generally by the diameter of the metal nanoparticle. In principle, the length increases with monotonically proportional to the growth time but is also statistical with length distribution.
  • the wires are expected to be epitaxial but tend to have metal in its bulk. Previous researchers have used etching in ionic silver/HF solution to produce columns /wires on a regular silicon wafer. These columns /wires are firmly connected to the substrate and not readily detached or dispersed as wires.
  • the invention provides a method for forming silicon nanowires and nanowire composites.
  • the invention also provides a dispersed material consisting of highly pure silicon nanowires of substantially identical lengths, referred to as uniform dispersed material silicon nanowires.
  • a device quality silicon layer that is on a silicon on oxide substrate is etched with an HF/silver nitrate etching solution to form silicon nanowires attached to an oxide layer of the silicon on oxide substrate.
  • a silver film that forms during the etching is easily removed.
  • the nanowires are released from the surface of the oxide via gentle agitation.
  • Uniform length nanowires form having a length that is equal to the thickness of the device quality silicon layer.
  • the nanowires that form have pure crystalline silicon structure with no bulk contamination, and any residual silver on the surface of the nanowires after fabrication can be easily removed by selective etching.
  • FIG. 1 is a flowchart illustrating steps in a preferred embodiment silicon nanowire formation method of the invention
  • FIG. 2 is a flowchart illustrating steps in a preferred embodiment method for functionalizing silicon nanowires
  • FIG. 3 illustrates a preferred embodiment method for forming a silicon nanowire composite
  • FIG. 4 is an SEM image of silicon nanowires formed in an experiment conducted in accordance with the method of FIG. 1.
  • An embodiment of the invention is a method for forming silicon nanowires.
  • Methods of the invention form dispersions of free standing silicon nanowires that are straight and identical. Formation methods of the invention produce pure crystalline silicon nanowires with no bulk contamination. Dispersed material of the invention consists of quantities of such highly pure silicon nanowires of substantially identical lengths. Silicon nanowires formed by the invention exhibit the doping of the starting device quality silicon used in formation methods of the invention. In additional, the silicon nanowires can be doped using ion implantation or diffusive doping at higher temperatures after formation. Additionally, composites of the invention can be formed with silicon nanowires dispersed in a matrix, such as an RTV, polymer or epoxy matrix.
  • a preferred embodiment formation method of the invention conducts electroless etching with ionic silver HF acid of a Si on oxide (SOI) substrate to allow making free-standing nanowires by detachment at the oxide interface, and enables easy recovery of dispersions of nearly identical wires for subsequent controlled delivery as dispersed material or for incorporation in a matrix material.
  • SOI Si on oxide
  • a silicon on insulator (SOI) wafer is provided 10.
  • the SOI wafer has a device quality silicon layer with a predetermined thickness. The thickness is selected to achieve a desired length of silicon nanowire, as the thickness of the layer and length of the silicon nanowire produced are the same.
  • the lengths of pure silicon nanowires that are produced are formed by the method a substantially identically, namely the uniformity in length is entirely consistent with the uniformity in the thickness of the device quality silicon layer of the silicon on insulator (SOI) wafer.
  • a suitable SOI layer is, for example, a commercially available boron-doped (p- type) silicon (100) SOI wafer.
  • N-type device quality silicon SOI wafers can also be used.
  • the wafer is cleaned 12, for example with acetone, to remove organic contaminants.
  • the surface of the device quality silicon layer is then etched with an HF/silver nitrate solution 14.
  • the wafer is then dried 16, gently, such as by gentle blow drying or with a drying solvent.
  • a silver film that forms around the wafer is removed 18, by simple mechanical detaching or wet etching.
  • Silicon nanowires are harvested 20 from the wafer by gentle agitation, which can be achieved via sonication.
  • the nanowires themselves are pure crystalline silicon, but will have some residual silver on their surface.
  • the residual silver can be removed 22 by selective etching, such as etching in nitric acid.
  • the method produces a material consisting of a dispersion of highly pure silicon nanowires having substantially identical lengths.
  • the silicon nanowires produced are not necessarily luminescent, but the nanowires can be functionalized to be luminescent or for other pu ⁇ oses.
  • Silicon nanowires produced by the FIG. 1 process (or another process) can be, for example, functionalized for optoelectronics and sensing applications, as in a preferred method illustrated in FIG. 2.
  • a process for plating nanoparitcles that are fluorescent onto the nanowires can be adopted from PCT Publication WO 2007/018959.
  • the process involves treating a treating a silicon substrate with hexachloroplatinic acid (HCPA) and etching the silicon substrate with HF/H 2 O 2 to form silicon nanoparticles.
  • HCPA hexachloroplatinic acid
  • the process can also treat silicon nanowires to form silicon nanoparitcles on their surface, as is described with respect to FIG. 2.
  • silicon nanowires are harvested 24 in a dispersion solvent, such as methanol.
  • a plating solution is then added 26 to the nanowire dispersion solution.
  • a plating mixture is, for example, HCPA/HF.
  • the combined solution is stirred gently 28 for a time sufficient to permit plating of the nanowires. This can be a relatively short time period, e.g., 15min.
  • FIG. 3 illustrates a preferred embodiment method for forming a silicon nanowire composite by embedding the nanowires in a matrix.
  • step 40 recovered silicon nanowires are mixed with matrix precursors.
  • Example precursors include precursors for RTV, polyurethane or any other polymer material, or any epoxy material.
  • the mix is then sonicated in step 42, and the matrix is cured in step 44.
  • the result is a nanowire- composite, which can be an RTV, polymer, epoxy, etc. composite.
  • Nanowires embedded in the matrix can consist of a dispersion of highly pure silicon nanowires having substantially identical lengths.
  • the matrix material can be selected to be electrically nonconducting or electrically conducting depending on the application.
  • the matrix can also be a good or poor thermal conductor.
  • devices have been fabricated in experiments by sputtering metal contacts on the two faces of the composites. One face is contacted with a heat source such as a current driven thermal coil of nicrom wire. The electrical potential across the composite was measured, and compared to the response of a control device that had no wires embedded. The measurements reveal some enhanced thermoelectric response.
  • a commercial boron-doped silicon ( 100) (4- 8 ⁇ cm) silicon on insulator wafer (SOI) was used.
  • the wafer consists of three layers, a handle, an oxide layer, and a device quality silicon layer.
  • the handle is a thick silicon layer typically of the order of half a millimeter on the backside of the wafer.
  • the oxide layer is a few hundred nanometers thick silicon oxide layer.
  • a thin device quality silicon layer is on top of the oxide.
  • Various thicknesses of device quality silicon layers are available in commercial SOI wafers. The available thicknesses are typically in the range of about the range of 100 nm to tens of micrometers.
  • the SOI wafer is first cleaned by acetone, followed by etching in diluted aqueous HF solution.
  • An HF and silver nitrate solution was prepared as 5.0mol/L HF / 0.02mol/L silver nitrate.
  • the SOI wafer is immersed in the 5.0mol/L HF solution containing 0.02mol/L silver nitrate at 50°C.
  • the SOI wafer is removed and rinsed with de-ionized water and blown dry in air very gently. In the process, a thick silver film wrapping the silicon wafer forms, which can be simply mechanically detached or wet etched.
  • the wafer is then sonicated in a solvent to harvest the wires.
  • a simple selective chemical etching treatment in nitric acid permits removal of residual silver.
  • the length of the nanowires is controlled by the thickness of the device quality silicon layer.
  • the uniformity of the length is controlled by the uniformity of the layer. This was established by numerous experiments.
  • the commercial SOI wafer used in the experiments is rated at 10 ⁇ 0.5 ⁇ .
  • the cross section of the wire size achieved in the experiments was 50-90 nm. Adjustment of the etchant composition and a more uniform silicon layer is expected to achieve tighter control of the size and shape of the wire cross section.
  • FIG. 4 shows a scanning electron microscopy (SEM) of the wafer after etching but prior to separation of the nanowires from the wafer by sonication.
  • the silicon nanowires appear as piles as well as individual dispersed nanowires on both faces of the wafer. Those observed individually show that they of the same length and thickness.
  • the etched depth (i.e. the lengths of silicon nanowires) of the Si wafer is approximately lO ⁇ m, which is the thickness of the device quality silicon layer of the SOI wafer used to form the silicon nanowires.
  • the diameters of nanowires are in the range of 30- 200nm. Chemical analysis using the electron spectroscopy shows very little silver remaining.
  • the wires are weakly attached to the oxide layer. They may also detach during the process A brief acid treatment in HF or gentle sonication in a liquid of choice releases the wires into the liquid. Harsh or continued sonication may shatter or break the wires.
  • the sonicated nanowires can be deposited on a fresh silicon wafer or mixed in polymers to produce composites. The experiments showed that the wires produced by methods of the invention lack the metal contamination that is difficult to avoid with techniques that use nanoparticles as catalysts for the formation of nanowires.
  • nanowires produced by the invention are readily processes, since can be harvested as dispersions in any suitable liquid of choice. This permits the nanowires to be functionalized on their surface, such as by plating.

Abstract

The invention provides a method for forming silicon nanowires and composites in polymers. In a preferred method of the invention, a device quality silicon layer that is on a silicon on oxide substrate is etched with an HF/silver nitrate etching solution to form silicon nanowires attached to an oxide layer of the silicon on oxide substrate. A silver film that forms during the etching is easily removed. The nanowires are released from the surface of the oxide via a brief HF acid treatment and gentle agitation. Uniform length nanowires form having a length that is equal to the thickness of the device quality silicon layer. The nanowires that form have pure crystalline silicon structure with no bulk contamination, and any residual silver on the surface of the nanowires after fabrication can be easily removed by selective etching.

Description

SILICON NANOWIRE AND COMPOSITE FORMATION AND HIGHLY PURE AND UNIFORM LENGTH SILICON NANOWIRES
FIELD A field of the invention is silicon nanowires and composites.
BACKGROUND Significant interest exists in the possible use of silicon nanowires as basic charge carriers for electronic components. Silicon nanowires offer the promise of operational speeds that far exceed present state of the art solid state electronic devices. Silicon nanowires have the advantage of being compatible with existing process technology in the integrated circuit industry. When fabrication issues are solved, silicon nanowires will be used to form many electronic devices, such as field effect transistors (FETs), diodes, and logic gates. Such devices will incorporate silicon nanowires as charge carriers that will operate under physics laws of quantum mechanics. The potential exists for silicon nanowires to be powerful building blocks for nanoelectronics devices if the nanowires can be fabricated with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping. Silicon nanowire based devices should eventually form an important alternative to conventional planar technology. A silicon nanowire based FET, for example, will provide improved electrostatic control of the channel via the gate voltage and better suppression of short channel effects than conventional planar technology.
Additional promising applications for silicon nanowires are as biosensors for the real-time detection of biological molecules (i.e. DNA, RNA, proteins). Such sensors are based on the fact that changes in conduction occur when a charged object is brought in close proximity to the silicon nanowire surface. Efforts to fabricate silicon nanowires that have been used in the art include chemical vapor deposition (CVD), pulsed laser vaporization (PLV), and thermal evaporation (TE). CVD and vapor-liquid-solid PLV require catalysts, while oxide-assisted thermal evaporation is catalyst free. A catalyst free technique provides a likely important advantage in terms of purity control, especially for avoiding trace metals.
Silicon nanowires fabricated by CVD are now grown on surfaces catalyzed by metal nanoparticles, such as gold nanoparticles. With this technique, there is marginal control over the length, direction and straightness or curvature of the silicon nanowires that form. The cross section is governed generally by the diameter of the metal nanoparticle. In principle, the length increases with monotonically proportional to the growth time but is also statistical with length distribution. The wires are expected to be epitaxial but tend to have metal in its bulk. Previous researchers have used etching in ionic silver/HF solution to produce columns /wires on a regular silicon wafer. These columns /wires are firmly connected to the substrate and not readily detached or dispersed as wires.
SUMMARY OF THE INVENTION
The invention provides a method for forming silicon nanowires and nanowire composites. The invention also provides a dispersed material consisting of highly pure silicon nanowires of substantially identical lengths, referred to as uniform dispersed material silicon nanowires. In a preferred method of the invention, a device quality silicon layer that is on a silicon on oxide substrate is etched with an HF/silver nitrate etching solution to form silicon nanowires attached to an oxide layer of the silicon on oxide substrate. A silver film that forms during the etching is easily removed. The nanowires are released from the surface of the oxide via gentle agitation. Uniform length nanowires form having a length that is equal to the thickness of the device quality silicon layer. The nanowires that form have pure crystalline silicon structure with no bulk contamination, and any residual silver on the surface of the nanowires after fabrication can be easily removed by selective etching.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart illustrating steps in a preferred embodiment silicon nanowire formation method of the invention;
FIG. 2 is a flowchart illustrating steps in a preferred embodiment method for functionalizing silicon nanowires;
FIG. 3 illustrates a preferred embodiment method for forming a silicon nanowire composite; and
FIG. 4 is an SEM image of silicon nanowires formed in an experiment conducted in accordance with the method of FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the invention is a method for forming silicon nanowires. Methods of the invention form dispersions of free standing silicon nanowires that are straight and identical. Formation methods of the invention produce pure crystalline silicon nanowires with no bulk contamination. Dispersed material of the invention consists of quantities of such highly pure silicon nanowires of substantially identical lengths. Silicon nanowires formed by the invention exhibit the doping of the starting device quality silicon used in formation methods of the invention. In additional, the silicon nanowires can be doped using ion implantation or diffusive doping at higher temperatures after formation. Additionally, composites of the invention can be formed with silicon nanowires dispersed in a matrix, such as an RTV, polymer or epoxy matrix.
A preferred embodiment formation method of the invention conducts electroless etching with ionic silver HF acid of a Si on oxide (SOI) substrate to allow making free-standing nanowires by detachment at the oxide interface, and enables easy recovery of dispersions of nearly identical wires for subsequent controlled delivery as dispersed material or for incorporation in a matrix material.
Preferred embodiments of the invention will now be discussed with respect to the drawings. The drawings may include schematic representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows. Features may be exaggerated in the drawings for emphasis, and features may not be to scale.
Referring now to FIG. 1, a preferred method of fabrication is illustrated. In the method, a silicon on insulator (SOI) wafer is provided 10. The SOI wafer has a device quality silicon layer with a predetermined thickness. The thickness is selected to achieve a desired length of silicon nanowire, as the thickness of the layer and length of the silicon nanowire produced are the same. The lengths of pure silicon nanowires that are produced are formed by the method a substantially identically, namely the uniformity in length is entirely consistent with the uniformity in the thickness of the device quality silicon layer of the silicon on insulator (SOI) wafer. A suitable SOI layer is, for example, a commercially available boron-doped (p- type) silicon (100) SOI wafer. N-type device quality silicon SOI wafers can also be used. The wafer is cleaned 12, for example with acetone, to remove organic contaminants. The surface of the device quality silicon layer is then etched with an HF/silver nitrate solution 14. The wafer is then dried 16, gently, such as by gentle blow drying or with a drying solvent. A silver film that forms around the wafer is removed 18, by simple mechanical detaching or wet etching. Silicon nanowires are harvested 20 from the wafer by gentle agitation, which can be achieved via sonication. The nanowires themselves are pure crystalline silicon, but will have some residual silver on their surface. The residual silver can be removed 22 by selective etching, such as etching in nitric acid. The method produces a material consisting of a dispersion of highly pure silicon nanowires having substantially identical lengths. The silicon nanowires produced are not necessarily luminescent, but the nanowires can be functionalized to be luminescent or for other puφoses. Silicon nanowires produced by the FIG. 1 process (or another process) can be, for example, functionalized for optoelectronics and sensing applications, as in a preferred method illustrated in FIG. 2. A process for plating nanoparitcles that are fluorescent onto the nanowires can be adopted from PCT Publication WO 2007/018959. The process involves treating a treating a silicon substrate with hexachloroplatinic acid (HCPA) and etching the silicon substrate with HF/H2O2 to form silicon nanoparticles. The process can also treat silicon nanowires to form silicon nanoparitcles on their surface, as is described with respect to FIG. 2. First, silicon nanowires are harvested 24 in a dispersion solvent, such as methanol. A plating solution is then added 26 to the nanowire dispersion solution. A plating mixture is, for example, HCPA/HF. The combined solution is stirred gently 28 for a time sufficient to permit plating of the nanowires. This can be a relatively short time period, e.g., 15min. The solvent is then decanted (meaning drained) and the wires are hence removed 30 from the plating solution and rinsed 32, e.g., with de-ionized water to remove residual plating solution. HF/H2O2 is then added to the wires 34, which can typically be completed in about 30-45 seconds. The nanowires are then removed and rinsed 36, e.g., with de-ionized water. The nanowires are then dried 38, such as by air drying or adding a drying solvent. Once the nanowires are recovered and collected, a composite can be formed with the nanowires. FIG. 3 illustrates a preferred embodiment method for forming a silicon nanowire composite by embedding the nanowires in a matrix. In step 40, recovered silicon nanowires are mixed with matrix precursors. Example precursors include precursors for RTV, polyurethane or any other polymer material, or any epoxy material. The mix is then sonicated in step 42, and the matrix is cured in step 44. The result is a nanowire- composite, which can be an RTV, polymer, epoxy, etc. composite. Nanowires embedded in the matrix can consist of a dispersion of highly pure silicon nanowires having substantially identical lengths. The matrix material can be selected to be electrically nonconducting or electrically conducting depending on the application. The matrix can also be a good or poor thermal conductor. In one example application, devices have been fabricated in experiments by sputtering metal contacts on the two faces of the composites. One face is contacted with a heat source such as a current driven thermal coil of nicrom wire. The electrical potential across the composite was measured, and compared to the response of a control device that had no wires embedded. The measurements reveal some enhanced thermoelectric response.
Experiments Experiments have been conducted to demonstrate the formation method of the invention, and example silicon nanowires 10 μm long and 50 - 100 nm thick were produced and observed by scanning electron microscopy. The wires are readily dispersed and are pure crystalline silicon. The experiments also demonstrated that the length of the wires can be controlled in methods of the invention, as the length of nanowires is governed by the thickness of the silicon layer.
In the experiments, a commercial boron-doped silicon ( 100) (4- 8Ωcm) silicon on insulator wafer (SOI) was used. The wafer consists of three layers, a handle, an oxide layer, and a device quality silicon layer. The handle is a thick silicon layer typically of the order of half a millimeter on the backside of the wafer. The oxide layer is a few hundred nanometers thick silicon oxide layer. A thin device quality silicon layer is on top of the oxide. Various thicknesses of device quality silicon layers are available in commercial SOI wafers. The available thicknesses are typically in the range of about the range of 100 nm to tens of micrometers.
As preparation for the fabrication, the SOI wafer is first cleaned by acetone, followed by etching in diluted aqueous HF solution. An HF and silver nitrate solution was prepared as 5.0mol/L HF / 0.02mol/L silver nitrate. The SOI wafer is immersed in the 5.0mol/L HF solution containing 0.02mol/L silver nitrate at 50°C. After the etching process, the SOI wafer is removed and rinsed with de-ionized water and blown dry in air very gently. In the process, a thick silver film wrapping the silicon wafer forms, which can be simply mechanically detached or wet etched. The wafer is then sonicated in a solvent to harvest the wires. A simple selective chemical etching treatment in nitric acid permits removal of residual silver.
The length of the nanowires is controlled by the thickness of the device quality silicon layer. The uniformity of the length is controlled by the uniformity of the layer. This was established by numerous experiments. The commercial SOI wafer used in the experiments is rated at 10 ± 0.5 μ. The cross section of the wire size achieved in the experiments was 50-90 nm. Adjustment of the etchant composition and a more uniform silicon layer is expected to achieve tighter control of the size and shape of the wire cross section.
FIG. 4 shows a scanning electron microscopy (SEM) of the wafer after etching but prior to separation of the nanowires from the wafer by sonication. The silicon nanowires appear as piles as well as individual dispersed nanowires on both faces of the wafer. Those observed individually show that they of the same length and thickness. The etched depth (i.e. the lengths of silicon nanowires) of the Si wafer is approximately lOμm, which is the thickness of the device quality silicon layer of the SOI wafer used to form the silicon nanowires. The diameters of nanowires are in the range of 30- 200nm. Chemical analysis using the electron spectroscopy shows very little silver remaining.
The wires are weakly attached to the oxide layer. They may also detach during the process A brief acid treatment in HF or gentle sonication in a liquid of choice releases the wires into the liquid. Harsh or continued sonication may shatter or break the wires. Experiments also showed that the sonicated nanowires can be deposited on a fresh silicon wafer or mixed in polymers to produce composites.. The experiments showed that the wires produced by methods of the invention lack the metal contamination that is difficult to avoid with techniques that use nanoparticles as catalysts for the formation of nanowires. The silver used in the method of the invention stays on the outer surface of the wire if at all, and the small amount that may be present on the surface of the wire can easily be removed by with selective wet etching, such as by etching in nitric acid. Also, nanowires produced by the invention are readily processes, since can be harvested as dispersions in any suitable liquid of choice. This permits the nanowires to be functionalized on their surface, such as by plating.
While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.
Various features of the invention are set forth in the appended claims.

Claims

1. A method for forming silicon nanowires, the method comprising steps of: etching a device quality silicon layer that is on a silicon on oxide substrate with an HF/silver nitrate etching solution to form silicon nanowires attached to an oxide layer of the silicon on oxide substrate; and removing a silver film that forms during said etching.
2. The method of claim 1, further comprising a step of cleaning the silicon on oxide substrate prior to said step of etching.
3. The method of claim 1, further comprising a step of drying the silicon nanowires prior to said step of removing the silver film.
4. The method of claim 3, wherein said step of drying comprises gentle blow drying.
5. The method of claim 1, further comprising a step of removing any residual silver from the silicon nanowires.
6. The method of claim 5, wherein said step of removing any residual silver comprises wherein said step of removing comprises selective etching.
7. The method of claim 6, wherein said selective etching etches with nitric acid.
8. The method of claim 1 , further comprising a step of harvesting the silicon nanowires by gentle agitation.
9. The method of claim 8, wherein said gentle agitation comprises sonication.
10. The method of claim 1, further comprising a step of functionalizing the nanowires.
1 1. The method of claim 10, wherein said step of functionalizing comprises plating the nanowires with fluorescent nanoparticles.
12. The method of claim 1 , wherein said device quality silicon layer comprises a doped silicon layer.
13. The method of claim 1 , further comprising a step of forming a composite matrix including the nanowires.
14. The method of claim 13, wherein said step of forming a composite matrix comprises: mixing the nanowires in precursors for matrix material; and curing the matrix material.
15. Material consisting of a dispersion of a quantity of pure silicon nanowires having substantially identical lengths.
16. The material of claim 15, wherein the dispersion is contained within a matrix material.
17. The material of claim 16, wherein the matrix material comprises one of a polymer and an epoxy.
PCT/US2008/004983 2008-04-17 2008-04-17 Silicon nanowire and composite formation and highly pure and uniform length silicon nanowires WO2009128800A1 (en)

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