WO2009111164A3 - Structure and method for coupling signals to and/or from stacked semiconductor dies - Google Patents
Structure and method for coupling signals to and/or from stacked semiconductor dies Download PDFInfo
- Publication number
- WO2009111164A3 WO2009111164A3 PCT/US2009/034399 US2009034399W WO2009111164A3 WO 2009111164 A3 WO2009111164 A3 WO 2009111164A3 US 2009034399 W US2009034399 W US 2009034399W WO 2009111164 A3 WO2009111164 A3 WO 2009111164A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- external terminals
- die
- signals
- stacked semiconductor
- semiconductor dies
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
Abstract
Signals are coupled to/from stacked semiconductor dies through first and second sets of external terminals. The external terminals in the second set are connected to respective conductive paths extending through each of the dies. Signals are coupled to/from the first die through the first set of external terminals. Signals are also coupled to and from the second die through the conductive paths in the first die and the second set of external terminals. The external terminals in first and second sets of each of a plurality of pairs are connected to an electrical circuit through respective multiplexers. The multiplexers in each of the dies are controlled by respective control circuits that sense whether a die in the first set is active. The multiplexers connect the external terminals in either the first set or the second set depending on whether the bonding pad in the first set is active.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/074,562 US7847626B2 (en) | 2008-03-04 | 2008-03-04 | Structure and method for coupling signals to and/or from stacked semiconductor dies |
US12/074,562 | 2008-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009111164A2 WO2009111164A2 (en) | 2009-09-11 |
WO2009111164A3 true WO2009111164A3 (en) | 2009-12-17 |
Family
ID=41052981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/034399 WO2009111164A2 (en) | 2008-03-04 | 2009-02-18 | Structure and method for coupling signals to and/or from stacked semiconductor dies |
Country Status (3)
Country | Link |
---|---|
US (2) | US7847626B2 (en) |
TW (1) | TWI398939B (en) |
WO (1) | WO2009111164A2 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5430880B2 (en) * | 2008-06-04 | 2014-03-05 | ピーエスフォー ルクスコ エスエイアールエル | Memory module, method of using the same, and memory system |
US8338294B2 (en) * | 2011-03-31 | 2012-12-25 | Soitec | Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods |
US9164679B2 (en) | 2011-04-06 | 2015-10-20 | Patents1, Llc | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
US9170744B1 (en) | 2011-04-06 | 2015-10-27 | P4tents1, LLC | Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US9176671B1 (en) | 2011-04-06 | 2015-11-03 | P4tents1, LLC | Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9158546B1 (en) | 2011-04-06 | 2015-10-13 | P4tents1, LLC | Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory |
JP5822370B2 (en) * | 2011-07-05 | 2015-11-24 | インテル・コーポレーション | Self-disable chip enable input |
US9417754B2 (en) | 2011-08-05 | 2016-08-16 | P4tents1, LLC | User interface system, method, and computer program product |
CN107305861B (en) * | 2016-04-25 | 2019-09-03 | 晟碟信息科技(上海)有限公司 | Semiconductor device and its manufacturing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030062612A1 (en) * | 2001-09-29 | 2003-04-03 | Kabushiki Kaisha Toshiba | Stacked type semiconductor device |
US6624506B2 (en) * | 2000-04-20 | 2003-09-23 | Kabushiki Kaisha Toshiba | Multichip semiconductor device and memory card |
US20050181546A1 (en) * | 2002-07-08 | 2005-08-18 | Madurawe Raminda U. | Methods for fabricating fuse programmable three dimensional integrated circuits |
JP2007194444A (en) * | 2006-01-20 | 2007-08-02 | Elpida Memory Inc | Stacked semiconductor device |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5008548A (en) * | 1989-08-01 | 1991-04-16 | Nahum Gat | Personal UV radiometer |
DE19628270C2 (en) * | 1996-07-12 | 2000-06-21 | Ericsson Telefon Ab L M | Interference-free interface circuit |
KR100195745B1 (en) * | 1996-08-23 | 1999-06-15 | 전주범 | Add compare selecter of vitervi decoder |
US6070263A (en) * | 1998-04-20 | 2000-05-30 | Motorola, Inc. | Circuit for use in a Viterbi decoder |
US6169417B1 (en) * | 1998-05-22 | 2001-01-02 | Altera Corporation | Product-term macrocells for programmable logic device |
US6382758B1 (en) * | 2000-05-31 | 2002-05-07 | Lexmark International, Inc. | Printhead temperature monitoring system and method utilizing switched, multiple speed interrupts |
US6848074B2 (en) * | 2001-06-21 | 2005-01-25 | Arc International | Method and apparatus for implementing a single cycle operation in a data processing system |
JP3593104B2 (en) * | 2002-01-11 | 2004-11-24 | 沖電気工業株式会社 | Clock switching circuit |
US7137059B2 (en) * | 2002-11-20 | 2006-11-14 | Broadcom Corporation | Single stage implementation of min*, max*, min and /or max to perform state metric calculation in SISO decoder |
US7352602B2 (en) * | 2005-12-30 | 2008-04-01 | Micron Technology, Inc. | Configurable inputs and outputs for memory stacking system and method |
TWI319617B (en) * | 2006-09-12 | 2010-01-11 | Holtek Semiconductor Inc | Fuse option circuit |
-
2008
- 2008-03-04 US US12/074,562 patent/US7847626B2/en active Active
-
2009
- 2009-02-18 WO PCT/US2009/034399 patent/WO2009111164A2/en active Application Filing
- 2009-02-27 TW TW098106555A patent/TWI398939B/en active
-
2010
- 2010-11-17 US US12/948,655 patent/US20110063023A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6624506B2 (en) * | 2000-04-20 | 2003-09-23 | Kabushiki Kaisha Toshiba | Multichip semiconductor device and memory card |
US20030062612A1 (en) * | 2001-09-29 | 2003-04-03 | Kabushiki Kaisha Toshiba | Stacked type semiconductor device |
US20050181546A1 (en) * | 2002-07-08 | 2005-08-18 | Madurawe Raminda U. | Methods for fabricating fuse programmable three dimensional integrated circuits |
JP2007194444A (en) * | 2006-01-20 | 2007-08-02 | Elpida Memory Inc | Stacked semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US20090224822A1 (en) | 2009-09-10 |
US20110063023A1 (en) | 2011-03-17 |
TW200952145A (en) | 2009-12-16 |
TWI398939B (en) | 2013-06-11 |
US7847626B2 (en) | 2010-12-07 |
WO2009111164A2 (en) | 2009-09-11 |
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