WO2009002541A1 - Gate driving scheme for depletion mode devices in buck converters - Google Patents
Gate driving scheme for depletion mode devices in buck converters Download PDFInfo
- Publication number
- WO2009002541A1 WO2009002541A1 PCT/US2008/007982 US2008007982W WO2009002541A1 WO 2009002541 A1 WO2009002541 A1 WO 2009002541A1 US 2008007982 W US2008007982 W US 2008007982W WO 2009002541 A1 WO2009002541 A1 WO 2009002541A1
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- WIPO (PCT)
- Prior art keywords
- switch
- sync
- gate
- circuit
- capacitor
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0018—Circuits for equalisation of charge between batteries using separate charge circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B40/00—Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to gate drivers for depletion mode devices, e.g., in buck converters and more particularly to generating gate drive signals for providing negative voltage offset for turning off depletion mode devices.
- a circuit for driving a switching stage including control and sync switches series connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate driver including first and second switching stages for generating gate drive signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch; and a circuit connected to the first and second switching stages, the circuit comprising a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch, a first bias voltage from said first voltage source being switched by said first switching stage, said first switching stage having a first state wherein said sync switch is on, and a second state wherein said first bias voltage is switched to the gate of said sync switch to turn said sync switch off; and a gate driver including first and second switching stages for generating gate drive
- Figure 1 a is a diagram of a synchronous (sync) buck converter circuit with normal ON control and sync devices;
- Figure Ib is a graph illustrating signals for driving the control and sync devices of the sync buck converter circuit of Figure Ia;
- Figure 2a is a diagram of a sync buck converter circuit with normal OFF control and normal ON sync devices
- Figure 2b is a graph illustrating signals for driving the control and sync devices of the sync buck converter circuit of Figure 2a;
- Figures 3a-3f are diagrams of various circuits driving sync buck converters with both control and sync switches being normal ON devices;
- Figures 4a-4d are diagrams of various circuits driving sync buck converters with only the sync switch being a normal ON switch;
- Figures 5a-5b are diagrams of circuits driving sync buck converters with only the sync switches being normal ON devices.
- Figures 6 is a diagram of a circuit driving a sync buck converter with both the control and sync switches being normal ON switches.
- Figures Ia and 2a show two configurations of a synchronous Buck converter having a normal ON sync switch device G2.
- the converter of Figure Ia uses normal ON devices for both control switch Gl and sync switch device G2.
- the converter of Figure 2a uses the normal ON device only for sync switch G2, while using a normal OFF switch for control switch Ql.
- Figure Ib shows the gate waveforms required for driving control switch Gl and sync switch G2 of the converter circuit of Figure Ia
- Figure 2b shows the gate waveforms required for driving control switch Ql and sync switch G2 of the converter circuit of Figure 2a.
- Figures 3a-3f show configurations to drive the sync buck converter with both control and sync switch being normal ON devices.
- Figures 3 a-3f illustrate a converter stage having control and sync switches Gl and G2 series connected at a switching node SW.
- the sync switch has a Zener diode connected across it.
- Control switch Gl is further
- control and sync switches Gl and G2 are normal ON GaN HEMT (high electron mobility transistor) devices.
- a driver 12 controlling control and sync switches Gl and G2 includes high and low switching stages 14 and 16.
- Each switching stage includes a first P-channel switch 18, 22 and a second N-channel switch 20, 24.
- All switches can be of the same type, with appropriate control signals to ensure that the switches of each driver stage are switched on alternately, as known to those of skill in the art.
- the pairs of switches 18 and 20 and 22 and 24 are connected at switching nodes HDr for the high stage 14 and LDr for the low stage 16. Switching node HDr of the high stage of the driver is connected to a gate terminal of control switch Gl and switching node LDr of the low stage of the driver is connected to a gate terminal of sync switch G2.
- the circuit includes first and second voltage sources Vdrl and Vdr2, capacitor Cl and diode Dl.
- the source terminal of the switch 18 of the high stage 14 is connected to switching node SW.
- Capacitor Cl is connected between the source terminals of the switches 18 and 20 of the high stage 14.
- the positive terminal of second voltage source Vdr2 is connected to the drain of control switch Gl .
- Diode Dl is connected between the source terminal of the switch 20 of the high stage 14 (at anode) and a negative terminal of second voltage source Vdr2 (at cathode).
- the source terminal of the switch 22 of the low stage 16 is connected to the source of sync switch G2.
- the positive terminal of a first voltage source Vdrl is connected to the source terminal of the switch 22 of the low stage 16 and the negative terminal of first voltage source Vdrl is connected to the source terminal of the switch 24 of the low stage 16.
- switch 18 When switch 18 is turned on and switch 20 is off (dead times are being ignored herein for simplicity), the gate of Gl is connected to its source, and the control switch Gl is on.
- switch 22 is off and switch 24 is on. This places -Vdrl across the gate of G2 to source, so the sync switch is off.
- switch 18 is turned off, switch 20 goes on.
- capacitor Cl is charged up in the direction shown in Fig. 3a to Vdr2 above V IN via diode Dl through the control switch Gl.
- switch 20 goes on (and 18 off)
- the voltage across Cl is coupled across the gate-source path of the control switch such that the gate of Gl is negative with respect to its source. Accordingly, the control switch goes off.
- switch 22 goes or. and switch 24 goes off. This couples the source of the sync switch to its gate and thus the sync switch goes on.
- the circuit includes the voltage source Vdrl, capacitor Cl, and diode Dl .
- the cathode of diode Dl is connected to a positive terminal of the first voltage source Vdrl.
- Fig. 3b works similarly to that of Fig. 3 a.
- switch 18 When switch 18 is on, the gate of Gl is coupled to the source of the control switch, and it is on. At the same time, capacitor Cl charges up to V IN via Dl and the on control switch to ground.
- Switch 20 is off at this time.
- Switch 22 is off and switch 24 is on, so the gate of G2 has -Vdrl applied to it with respect to its source, so it is off.
- the circuits operate by using the driver circuits to switch voltage sources or stored energy across the gate-source paths of the control and sync switches to turn them on and off.
- the Buck circuit of the embodiment of Figure 3 c is similar to that of Figure 3b. It includes resistor Rl positioned between the capacitor Cl and the anode of diode Dl to limit charging of Cl from V IN -
- the Buck circuit embodiment of Figure 3d also includes only one voltage source Vdrl, capacitor Cl, diode Dl, and a N-channel switch MB S -
- the source terminal of the switch 18 of the high stage 14 is connected to switching node SW.
- Capacitor Cl is connected between the source terminals of the switches 18 and 20 of the high stage 14.
- the source terminal of the switch 22 of the low stage 16 is connected to the source of sync switch G2.
- the positive terminal of voltage source Vdrl is connected to the source terminal of the switch 22 of the low stage 16 and ihe negative terminal of the first voltage source Vdrl is connected to the source terminal of the switch 24 of the low stage 16.
- the anode of diode Dl is connected to the source terminal of the switch 20 of the high stage 14 and its cathode is connected to the drain of switch M B S-
- the gate of switch M B S is controlled by a node LDr and MBS is turned on when switch 22 is on (and the sync switch 62 is on).
- the source of MBS is connected to the source terminal of the switch 24 of the low stage 16.
- Figure 3e modifies the above circuit by replacing diode Dl with a resistor Rl.
- Switch MB S functions like a bootstrap circuit, charging up from Vdrl when switch 22 is on and the sync switch is on.
- capacitor Cl charges through Rl instead of diode Dl.
- the Buck circuit embodiment of Figure 3f includes only one voltage source Vdrl, three capacitors Cl, C2, and C3, and three diodes Dl, D2, and D3.
- ⁇ 00919004.1 ⁇ Cl is connected between the source terminals of the switches 18 and 20 of the high stage 14.
- the positive terminal of voltage source Vdrl is connected to the source terminal of the switch 22 of the low stage 16 and the negative terminal of the first voltage source Vdrl is connected to the source terminal of the switch 24 of the low stage 16.
- the anode of diode Dl is connected to the positive terminal of voltage source Vdrl and its cathode is connected to the source terminals of the switch 18 of the high stage 14.
- Capacitor C2 is connected between node HDr of the high stage 14 and the gate terminal of control switch Gl and the anode of diode D2 is connected between the gate terminal of control switch Gl and the source terminal of the switch 20 of the high stage 14, which is also connected to switching node SW.
- the capacitor C3 is connected between node LDr of the low stage 16 and the gate terminal of sync switch G2 and the anode of diode D3 is connected between the gate terminal of sync switch G2 and the source terminal of the switch 24 of the low stage 16, which is also connected to the drain of the sync switch.
- Capacitor Cl charges up from Vdrl through Dl when the sync switch G2 is on, like a bootstrap capacitor circuit.
- the normal ON control switch is on when switch 18 is turned on.
- the synchronous switch G2 is turned off when switch 24 goes on.
- Capacitor C3 charges to Vdrl through diode D3 when switch 22 is on.
- switch 24 goes on, the gate of G2 is made negative with respect to the source and the sync switch turns off.
- switch 20 is turned on and is off.
- Capacitor C2 is charged up when switch 18 is on by the charge on capacitor Cl .
- switch 20 goes on, the charge on capacitor C2 is placed across the gate-source path of Gl, such that the gate of Gl is negative with respect to the source, turning the control switch off.
- Figures 4a-4d show configurations for use with converters wherein only the sync switch is a normal ON switch and the control switch Gl is a normal OFF enhancement node device.
- the Buck circuit embodiment of Figure 4a includes one voltage source Vdrl , two capacitors Cl and C5, and two diodes Dl and D5.
- Capacitor Cl is connected between the source terminals of the switches 18 and 20 of the high stage 14.
- the positive terminal of voltage source Vdrl is connected to the source terminal of the switch 22 of the low stage 16 and the negative terminal of the first voltage source Vdrl is connected to the source terminal of the switch 24 of the low stage 16.
- the anode of diode Dl is connected to the positive terminal of voltage source Vdrl and its cathode is connected to the source terminal of the switch 18 of the high stage 14.
- Capacitor C5 is connected between node LDr of the low stage 16 and the gate terminal of sync switch G2 and the anode of diode D5 is connected between the gate terminal of sync switch G2 and the source terminal of the switch 24 of the low stage 16, which . is also connected to the drain of the sync switch.
- switch 22 When switch 22 is on, capacitor C5 charges through switch 22 and D5 from Vdrl .
- the normal ON sync switch G2 is on.
- Switch 20 is also on and the control switch Gl is off, as it is not a depletion device and its gate is connected to its source by switch 20.
- Capacitor Cl charges up to Vdrl through diode Dl and the on sync switch G2.
- switch 18 goes on and the charge on Cl is provided to the gate of Gl, turning the enhancement mode control switch on.
- the sync switch is turned off when switch 24 is turned on.
- the charge stored on C5 when switch 22 was on from source Vdrl is provided across the gate-source path of the sync switch G2 such that the gate is negative with respect to the source, turning the sync switch off.
- the Buck circuit embodiments of Figures 4b-4d include a second voltage source Vdr2.
- the anode of diode Dl is connected to the positive terminal of the second voltage source Vdr2 and Cl charges from Vdr2 when the sync switch G2 is on.
- the embodiment of Figure 4c modifies that of Figure 4b by replacing diode D5 with a P-channel controlled switch M5.
- Diode D5 and switch M5 may be integrated into the driver 12. Switch M5 is turned on when switch 22 is on.
- Figure 4d illustrates an embodiment (like Fig. 3a) having the drain terminal of the switch 22 of the low stage 16 connected to the gate terminal of sync switch G2 and voltage source Vdrl connected between the source terminals of the switches 22 and 24 of the low stage 16.
- Capacitor Cl is connected between the source terminals of the switches 18 and 20 of the high stage 14.
- Diode Dl connects to the positive terminal of voltage source Vdr2 and to the source terminal of the switch 18 of the high stage 14.
- the low driver operates similarly to the low driver of Fig. 3a.
- the above-described circuits drive depletion mode devices from OV to -Vcc, which is for example -7V. Slight modification of the above circuits can enable the driver from Vccl to Vcc2, e.g., -3 V to -10V or -4V to 3 V for normally ON devices as the control or sync FET.
- Figures 5a-5b show such modified configurations for use with sync buck converters where the control switch is an enhancement mode silicon FET and the sync switch is a normal ON device and having three voltage sources.
- Figure 5a illustrates a configuration similar to that of Figure 4b but adds a third voltage source.
- Figure 5b illustrates a configuration similar to that of Figure 4d but adds the third voltage source between the source terminal of the switch 22 of the low stage 16 and the gate terminal of sync switch G2.
- the depletion mode sync switch is turned off by the combined voltage Vdrvl + Vdrv3 charged across C5 via switch 22 when switch 24 is turned on.
- the sync switch is on when switch 22 turns on. This places -Vccl across the gate-source path. This transistor is on with -Vccl at its gate.
- FIG. 6 shows another modified configuration for use with sync buck converters with both switches being the normal ON type and employing two bias voltages.
- the switches Gl and G2 iemain on at a first negative gate-source voltage and turn off at an even more negative gate-source voltage.
- the Buck circuit embodiment of Figure 6 includes the two voltage sources Vccl and Vcc2, two capacitors C6 and C7, two diodes D6 and D7, and two N-channel switches Mbsl and Mbs2.
- Voltage source Vccl is connected between the source terminals of the switches 22 and 24 of the low stage 16 and voltage source Vcc2 is connected between the source terminal of the switch 22 of the low stage 16 and the source of sync switch G2.
- Capacitor C6 is connected between the source terminal of the switch 20 of the high stage 14 and switching node SW.
- Capacitor C7 is connected between the source terminal of the switch 18 of the high stage 14 and the switching node SW.
- a first terminal of the switch Mbsl is connected to the source terminal of the switch 20 of the high stage 14 via the diode D6 and its second terminal is connected to the source terminal of the switch 24 of the low stage 16.
- a first terminal of switch Mbs2 is connected to the source terminal of the switch 18 of the high stage 14 via diode D7 and its second terminal is connected to the source terminal of the switch 22 of the low stage 16.
- Gate terminals of switches Mbsl and Mbs2 are connected to node LDr of the low stage 16 and driven on when switch 22 is driven on.
- capacitors C6 and C7 are charged when switch 22 is turned on and the sync switch is thus on.
- Capacitor C6 charges to Vccl + Vcc2 through D6, MBSl and the sync switch.
- Capacitor C7 charges to Vcc2 through D7, MBS2 and the sync switch.
- switch 22 is on, the gate cf G2 is at -Vcc2 so G2 is on. This allows the capacitors C6 and C7 to charge as discussed.
- switch 20 When switch 22 is on, switch 20 is also on. This connects the gate of Gl to the voltage of C6 (-(Vccl + Vcc2)) such that the gate of Gl is more negative with respect to the source. Gl is thus off.
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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CN200880015972A CN101682720A (en) | 2007-06-27 | 2008-06-27 | Gate driving scheme for depletion mode devices in buck converters |
DE200811001273 DE112008001273B4 (en) | 2007-06-27 | 2008-06-27 | Control scheme for depletion elements in buck converters |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US94655007P | 2007-06-27 | 2007-06-27 | |
US60/946,550 | 2007-06-27 |
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WO2009002541A1 true WO2009002541A1 (en) | 2008-12-31 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2008/007982 WO2009002541A1 (en) | 2007-06-27 | 2008-06-27 | Gate driving scheme for depletion mode devices in buck converters |
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US (2) | US7839131B2 (en) |
CN (1) | CN101682720A (en) |
DE (1) | DE112008001273B4 (en) |
WO (1) | WO2009002541A1 (en) |
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CN101807905A (en) * | 2010-02-11 | 2010-08-18 | 西安能讯微电子有限公司 | Drive circuit of deplete semiconductor switching element and drive method thereof |
WO2016057878A1 (en) | 2014-10-10 | 2016-04-14 | Efficient Power Conversion Corporation | High voltage zero qrr bootstrap supply |
US10447159B2 (en) | 2015-05-29 | 2019-10-15 | Wupatec | DC-DC converter block, DC-DC converter comprising same and associated system envelope tracking system |
US10784794B2 (en) * | 2017-08-28 | 2020-09-22 | Efficient Power Conversion Corporation | GaN FET gate driver for self-oscillating converters |
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US8674670B2 (en) * | 2006-11-28 | 2014-03-18 | International Rectifier Corporation | DC/DC converter with depletion-mode III-nitride switches |
CN101682720A (en) * | 2007-06-27 | 2010-03-24 | 国际整流器公司 | Gate driving scheme for depletion mode devices in buck converters |
US8981380B2 (en) * | 2010-03-01 | 2015-03-17 | International Rectifier Corporation | Monolithic integration of silicon and group III-V devices |
US9219058B2 (en) * | 2010-03-01 | 2015-12-22 | Infineon Technologies Americas Corp. | Efficient high voltage switching circuits and monolithic integration of same |
US9263439B2 (en) * | 2010-05-24 | 2016-02-16 | Infineon Technologies Americas Corp. | III-nitride switching device with an emulated diode |
US8847563B2 (en) | 2010-07-15 | 2014-09-30 | Cree, Inc. | Power converter circuits including high electron mobility transistors for switching and rectifcation |
US20120274366A1 (en) | 2011-04-28 | 2012-11-01 | International Rectifier Corporation | Integrated Power Stage |
US9391604B2 (en) * | 2012-01-23 | 2016-07-12 | Infineon Technologies Austria Ag | Methods for monitoring functionality of a switch and driver units for switches |
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US9978862B2 (en) | 2013-04-30 | 2018-05-22 | Infineon Technologies Austria Ag | Power transistor with at least partially integrated driver stage |
US9799643B2 (en) * | 2013-05-23 | 2017-10-24 | Infineon Technologies Austria Ag | Gate voltage control for III-nitride transistors |
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US9281737B2 (en) * | 2014-02-03 | 2016-03-08 | Freescale Semiconductor, Inc. | Voltage converter |
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- 2008-06-27 DE DE200811001273 patent/DE112008001273B4/en active Active
- 2008-06-27 WO PCT/US2008/007982 patent/WO2009002541A1/en active Application Filing
- 2008-06-27 US US12/163,100 patent/US7839131B2/en active Active
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CN101807905A (en) * | 2010-02-11 | 2010-08-18 | 西安能讯微电子有限公司 | Drive circuit of deplete semiconductor switching element and drive method thereof |
WO2016057878A1 (en) | 2014-10-10 | 2016-04-14 | Efficient Power Conversion Corporation | High voltage zero qrr bootstrap supply |
EP3205021A4 (en) * | 2014-10-10 | 2018-06-13 | Efficient Power Conversion Corporation | High voltage zero qrr bootstrap supply |
US10084445B2 (en) | 2014-10-10 | 2018-09-25 | Efficient Power Conversion Corporation | High voltage zero QRR bootstrap supply |
US10447159B2 (en) | 2015-05-29 | 2019-10-15 | Wupatec | DC-DC converter block, DC-DC converter comprising same and associated system envelope tracking system |
US10784794B2 (en) * | 2017-08-28 | 2020-09-22 | Efficient Power Conversion Corporation | GaN FET gate driver for self-oscillating converters |
Also Published As
Publication number | Publication date |
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DE112008001273B4 (en) | 2015-02-12 |
US20110074375A1 (en) | 2011-03-31 |
US8072202B2 (en) | 2011-12-06 |
CN101682720A (en) | 2010-03-24 |
US7839131B2 (en) | 2010-11-23 |
US20090051225A1 (en) | 2009-02-26 |
DE112008001273T5 (en) | 2010-03-04 |
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