WO2008134455A3 - Command resequencing in memory operations - Google Patents

Command resequencing in memory operations Download PDF

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Publication number
WO2008134455A3
WO2008134455A3 PCT/US2008/061467 US2008061467W WO2008134455A3 WO 2008134455 A3 WO2008134455 A3 WO 2008134455A3 US 2008061467 W US2008061467 W US 2008061467W WO 2008134455 A3 WO2008134455 A3 WO 2008134455A3
Authority
WO
WIPO (PCT)
Prior art keywords
command signals
command
resequencing
memory operations
attributes
Prior art date
Application number
PCT/US2008/061467
Other languages
French (fr)
Other versions
WO2008134455A2 (en
Inventor
Michael J Cornwell
Christopher P Dudte
Thomas R Colligan
Original Assignee
Apple Inc
Michael J Cornwell
Christopher P Dudte
Thomas R Colligan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc, Michael J Cornwell, Christopher P Dudte, Thomas R Colligan filed Critical Apple Inc
Priority to EP08746818.7A priority Critical patent/EP2140362B1/en
Publication of WO2008134455A2 publication Critical patent/WO2008134455A2/en
Publication of WO2008134455A3 publication Critical patent/WO2008134455A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Abstract

Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.
PCT/US2008/061467 2007-04-25 2008-04-24 Command resequencing in memory operations WO2008134455A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP08746818.7A EP2140362B1 (en) 2007-04-25 2008-04-24 Command resequencing in memory operations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/739,878 2007-04-25
US11/739,878 US7996599B2 (en) 2007-04-25 2007-04-25 Command resequencing in memory operations

Publications (2)

Publication Number Publication Date
WO2008134455A2 WO2008134455A2 (en) 2008-11-06
WO2008134455A3 true WO2008134455A3 (en) 2009-03-26

Family

ID=39472670

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/061467 WO2008134455A2 (en) 2007-04-25 2008-04-24 Command resequencing in memory operations

Country Status (4)

Country Link
US (3) US7996599B2 (en)
EP (3) EP2544094B1 (en)
TW (1) TWI362589B (en)
WO (1) WO2008134455A2 (en)

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