WO2008133515A2

WO2008133515A2 - Fabrication of planar electronic circuit devices

Info

Publication number: WO2008133515A2
Application number: PCT/NL2008/050255
Authority: WO
Inventors: Alec Reader; Nicolaas Aldegonda Jan Maria Van Aerle; Tobias Balla
Original assignee: Polymer Vision Limited
Priority date: 2007-04-25
Filing date: 2008-04-25
Publication date: 2008-11-06
Also published as: GB0708032D0; GB2448730A; WO2008133515A3

Abstract

A method is provided of fabricating a multilayer planar electronic circuit device on a substrate comprising the steps providing a patterned layer of a first conducting material, depositing a layer of a first insulating material and providing a patterned layer of a second conducting material. The method enables the fabrication of complex electronic circuit devices by depositing core material layers and forming the required conducting structures using an imprinting technique. High tolerances are possible at fast processing speed, while keeping processing material costs low.

Description

Fabrication of Planar Electronic Circuit Devices

Field of the Invention

The present invention relates to the fabrication of multilayer planar electronic circuit devices, and in particular organic circuit devices.

Background to the Invention

Currently, planar electronic circuit devices have been made with various techniques, from optical lithography to microcontact printing and nanoimprint lithography. The devices may comprise components that provide memory or perform logic functions. Complementary metal-oxide semi-conductor (CMOS) imagers are now rapidly overtaking charge-coupled device (CCD) type imagers and employ CMOS type transistors. Some devices might include thin film transistors (TFTs) or crossbar circuits, which require various processing techniques depending on the materials used. For example, a metal may need a deposition technique based on vacuum technology such as Physical Vapour Deposition (PVD) or Chemical Vapour Deposition (CVD). These additional processing techniques can complicate the production line, increase production time, use materials that are not very easy to handle and the techniques may also be quite expensive. Therefore, less complex processes are required, which allow for the necessary minimum feature resolution to be achieved, whilst also permitting a fast throughput in device fabrication.

A particular application of the above type of planar electronic circuit is in organic displays. Organic displays have been made using Passive Matrix Organic Light Emitting Diodes (PMOLED) and Active Matrix Organic Light Emitting Diodes (AMOLED) among other techniques, with different control elements to switch the LEDs on and off. Passive matrix devices will typically have a controlling electrode structure, whereas active matrix devices will typically have a controlling structure comprising active electronic devices such as TFTs. Organic type displays necessarily also require a layer for generating or reflecting the light used for the display. A variety of materials and mechanisms are available, including electroluminescent, electrophosphorescent and electrophoretic materials. Any fabrication process used for display devices therefore also needs to able to accommodate the application and processing of these material layers. NL2008/050255

2

Current display production techniques are expensive. The majority are made using optical lithography that uses a stepper to pattern a large area. This method relies on current semiconductor technology to create patterns by using etch techniques to selectively remove material to create a mask. This process involves sacrificial materials and requires etches that can be expensive depending on the materials needed. The need in the industry is for the production of displays to be made faster, at a much lower cost to enable plastic display technology to grow in size. The application of printing techniques in the fabrication of displays is currently being considered by various manufacturers, but the tolerances are not sufficient for commercial applications and will take a number of years before the processing technique becomes a viable, competitive means of producing displays.

As with the underlying electronic circuit structure, there is a clear need for an inexpensive and efficient process for fabricating organic circuits and display devices.

Summary of the Invention

According to the present invention, there is provided a method of fabricating a multilayer planar electronic circuit device on a substrate comprising the steps of: providing a patterned layer of a first conducting material; depositing a layer of a first insulating material; providing a patterned layer of a second conducting material.

Several options are possible to provide a patterned layer of a conducting material. According to a first embodiment the step of providing a patterned layer of a conducting material comprises the substeps of depositing a layer of a conducting material and subsequently patterning the conducting material layer by imprinting to form a first conducting structure of the first conducting material.

Alternatively however, a patterned layer of a conducting material may be provided by the following subsequent steps. depositing a layer of a mixture of a polymer and an initiator, patterning said layer by imprinting, forming an electrically conductive metal region on the surface of the patterned layer by contacting the initiator with a solution comprising a reducing agent and a solution containing metal ions. Therewith the initiator, the reducing agent and the metal ion undergo a chemical reactions initiated by the initiator, leading to formation of a metal layer, as described in for example WO 2008/040936. The metal ion may be an ion of any conductive metal, particularly a transition group metal like, copper, silver, gold, nickel but also alloys of two or more metals can be used. The conductive metal layer may even include non-metallic elements, for example, the conductive metal may be nickel-phosphorous

It is of course alternatively possible to process different metals layer on top of each other by subsequent immersion of the patterned layer in different solutions.

In this way a non-malleable metal layer can be created by imprinting a polymer layer with initiator followed by the above process.

The initiator typically comprises a catalyst or catalyst precursor, being a salt or complex of a conductive metal, preferably a salt of a transition metal like palladium, platinum, or silver. The salt may be fully inorganic, such as for example palladium chloride, copper chloride, or partly organic such as for example palladium acetate, or an intermediate such as palladium cyanide, or the metal ion is bound in a complex such as with ethylenediaminetetraacetic acid (EDTA). Palladium acetate is a catalyst precursor of palladium. Palladium is a catalyst in metallisation reactions. The precursor catalyst can transform into the catalyst by reduction, like for example by exposing the precursor to a reducing agent. An example of a reducing agent is an aqueous solution of dimethylamine borane. A variety of different materials that can be used are described in WO 2008/040936 The present invention enables the fabrication of quite complex electronic circuit devices by depositing the core material layers using a deposition technique. Deposition of the various materials may be carried out by any suitable deposition method, such as spray-coating, slit-coating, slot-die coating, extrusion coating, printing like ink -jet printing, flexoprinting, offset printing or spin-coating or a combination thereof. Spin-coating is particularly suitable for coating smaller surfaces and has the advantage that it results in a good uniformity of the applied layer. However, part of the material applied by spin-coating is spun-off the substrate, and is lost therewith. An efficient use of coating material is promoted by first depositing the material by a method like spray coating or printing, and subsequently performing spinning as a 2^nd step. In this way a uniform layer thickness is obtained in combination with an efficient use of material. After deposition of the conductive material or precursor thereof, the required conducting structures are formed using an imprinting technique. The deposited layers of material are sufficiently malleable in the first instance to allow patterning of features by imprinting, or stamping. Imprint techniques involve less processing materials, which reduces costs and benefits the device as other materials may contaminate the material deposited. Moreover, imprinting enables the process to achieve dimensional tolerances required for device fabrication that cannot yet be achieved by other simple patterning techniques such as printing, whilst also enabling the processing speed and associated throughput that can be achieved by some of those techniques.

The sequence of steps a) providing a patterned layer of a first conducting material, b) depositing a layer of a first insulating material, c) providing a patterned layer of a second conducting material can be used to form various electronic components, e.g. capacitors. More complex electronic structures can be obtained if the method of fabricating the multilayer planar electronic circuit further comprises a step d) of depositing a layer of a semi-conducting material. The layer of semiconducting material may be deposited by any of the deposition techniques described above. Instead of applying the semi-conducting material directly, it may be applied as a precursor material or a precursor material mixed with a binding material and is transformed into a semi-conducting material by an irradiation or thermal anneal step.

The steps a-d need not necessarily be carried out in alphabetic order, but may be carried out in any of the following sequences abdc, abed, adbc, dabc, depending on the type of electronic circuit to be manufactured. For example bottom gate, top contact semiconductor elements (BG/TC) may be formed by a carrying out the steps in the sequence abdc; bottom gate, bottom contact semiconductor elements (BG/BC) may be formed by carrying out the steps in the sequence abed. Likewise a top gate, top contact semiconductor elements (TG/TC) may be formed by carrying out the steps in the sequence dabc, and top gate, bottom contact semiconductor elements (TG/BC) may be formed by carrying out the steps in the sequence adcb.

Other semiconductor elements may be manufactured too by adding further layers. For example a device operative as a variable capacitance is obtained if an additional semiconductor layer is applied of opposite polarity adjacent to the first semiconductor layer. Preferably, the method further comprises the step of depositing a layer of a second insulating material by spinning. A single insulating layer may be sufficient in some devices to provide the required electrical isolation of the conducting structures. However, in other devices at least a second layer of insulating material will be required.

Preferably, the method further comprises the step of disposing a base layer of a protective material onto the substrate, and wherein the layer of the first conducting material is deposited onto the protective base layer by spinning.

Preferably, the method further comprises the step of removing the multilayer planar electronic circuit from the substrate.

The substrate will typically act as a temporary and relatively rigid planar support on which the multilayer device can be fabricated, but from which the finished device can be removed. This is particularly advantageous where the materials used for the device are flexible and the resulting device can be flexed or even rolled. In this case the completed device may simply be peeled off the supporting substrate. When present, the protective base layer protects the device structure both during and subsequent to the removal from the substrate.

Preferably, at least one of the first and second conducting structures comprises an electrode structure. This is the most basic form of conducting structure. There may be either a simple or complex electrode structure in one or both layers. One electrode may operate as an anode and another as a cathode, although the electrodes may function differently when part of a semiconductor component.

More preferably, one of the first and second conducting structures comprises a bit-line electrode structure and the other of the first and second conducting structures comprises a word-line electrode structure. This structure permits the application of control signal to individual elements of the device forming a matrix.

At least one of the first and second conducting structures may comprise a via for providing an electrical conducting path through a material layer deposited over the conducting structure. For example, a layer of insulating material may be deposited between and over the conducting structure and the via path through this. The method may then also further comprise the step of etching a thickness of the material layer deposited over the conducting structure to expose the underlying via. Depending on the device to be fabricated, the order in which the material layers are deposited may vary. Moreover, some or all of the steps may be repeated to form a more complex multilayer structure. In one example, the material layers are deposited in the following order: first conducting material, first insulating material, semi-conducting material, second insulating material, and second conducting material.

The semiconducting layer may be created from a precursor material that can be transformed into the semiconductor by applying a thermal step or an irradiation step, for example by UV-light. To deposit a uniform layer from a solution one may add some binder like a polymer, for example polystyrene. This is especially helpful in case the precursor or the semiconductor consists of small molecules or a material that tends to crystallize easily.

If the device is to include one or more individual semiconductor components it is preferred that the method further comprises the step of patterning the semi- conducting material layer by imprinting to form a semi-conducting structure. For example, a thin film transistor (TFT) may be fabricated in this manner. In case the imprinting is done using the precursor a subsequent thermal or irradiation step is used to transform it into the semiconducting material.

For many semiconductor components it is necessary to provide electrical paths between the conducting layers and the semiconductor layer by forming a conducting via though the insulating layers. This may be done by patterning a conducting layer as described above. However, it may also be done by patterning an insulating layer to create a temporary void which is then filled with material to create the final via. Preferably, the method further comprises the step of patterning the first insulating material layer for forming at least one via therethrough. When a second insulating layer is present it is preferred that the method further comprises the step of patterning the second insulating material layer for forming at least one via therethrough Preferably, the first and second insulating material layers are patterned by imprinting to form the at least one via. As previously described imprinting is a simple mechanical technique suitable for patterning such structures. Alternatively, the first and second insulating material layers are patterned by etching to form the at least one via. Following patterning for the vias the method further comprises the step of depositing conducting or semiconducting material by spinning in a region of the first and/or second insulating material layer so patterned in order to form the via through the insulating material layer.

Although imprinting is a straightforward technique sufficient to form the desired structures, it will often leave a thin layer of unwanted material in the patterned regions due to the mechanical nature of the technique.

It is therefore preferred that the method further comprises the step of removing by etching a residual thickness of an imprinted material layer after the step of imprinting so as to leave behind only the desired structure formed of the imprinted material. Any suitable etching process may be used. One such process is reactive ion etching (RIE).

Where an etch step is required, the layer of residual material will typically be sufficiently thin that it can be removed in a single etch. By comparison, patterning a similar shape using standard optical lithography techniques, rather than imprinting, frequently requires multiple etches and deposition layers, which results in a slower and more expensive process.

A variety of materials are available that may be used in the fabrication method of the present invention. The key requirement, in addition to the fundamental properties (e.g. electrical) necessary to the function of the material layer, is that the material may be deposited by a spin technique and, where appropriate, is capable of being imprinted. Typically, materials that have been spun will be malleable enough for subsequent imprinting. A curing process may be required to harden the material post imprinting. Standard materials may be used, such as metals for the conducting layers. However, other less common materials can offer other advantages. Preferably, at least one of the conducting, semi-conducting and insulating materials is a polymer. Such materials can satisfy the material properties required for spin deposition and imprinting and can allow fabrication of a final device that may be flexed or rolled. By employing a suitable dopant in the polymer the material can exhibit the other necessary properties, such as electrical. In this way conducting, semiconducting and insulating layers of polymer may be achieved, which provide a flexible plastic structure.

The requisite form of the material required for spin deposition and subsequent imprinting may be achieved by preparing the material using particular, well-suited processes, such as a sol-Gel process. Using the fabrication method of the present invention a wide range of electronic components and devices may be fabricated. Preferably, a patterned region of the multilayer planar electronic circuit comprises a thin film transistor

(TFT). Such semiconductor components may form the basis for a range of complex electronic devices.

If the fabricated device is to perform a particular optical or optoelectronic function then it will typically be necessary to include one or more layers of material to provide the required function.

In this case the semi-conducting material could also be an electroluminescent material.

Alternatively, the method may further comprise the step of applying a layer of an electrophoretic material to the multilayer device. This layer may be embedded with the multilayer structure or be located near to the surface of it.

Using the method of the present invention a range of multilayer planar electronic circuit devices may be fabricated. The steps of the method may be repeated to form even more complicated multilayer structures, allowing for the possibility of component stacking and three-dimensional structures.

For example, structures performing memory and complex logic operations may be fabricated. Memory devices or devices comprising a memory cell will typically require the deposition of another material, such as a ferro-electric compound. Thus, a display device may be fabricated comprising all the necessary circuitry, including memory, logic and addressable display in a single chip by stacking the structures. In this way, a much reduced footprint for the device can be achieved, as compared to conventional devices where the different functions are implemented by circuitry on separate chips.

Light emitting diode (LED) devices may be fabricated where the semiconducting material is an electroluminescent material, for example. Other types of optical devices may be fabricated according to the materials and conducting structures fabricated. In this way optical display devices, including organic display devices, may be fabricated using the method of the present invention, and which may be either passive or active matrix type devices. Cheap flexible plastic displays could be fabricated from polymer based materials, which can be doped or adapted.

When applied to the fabrication of organic displays the method of the present invention uses fewer processing techniques and steps as compared to existing methods, namely polymer spin-on, imprinting and residue layer etch, and therefore is able to produce the stack needed to create pixels for displays more quickly and cheaply than these currently used methods. The imprinting technique is also scalable, enabling of various sizes of display using the same method.

Another application for the present invention is in the fabrication of CMOS image sensor devices. The fabrication technique readily lends itself to the fabrication of the requisite transistors and busses, and may extend to the formation of photodiode and filter components as well.

As will be appreciated by those skilled in the art, the present invention provides a simple, cost-effective technique for fabricating a multilayer planar electronic circuit device, with both high throughput and good feature resolution. The technique can be adapted for fabricating a huge range of devices and, in particular, enables the fabrication of new more compact three-dimensional device structures by vertically stacking circuits performing different functions.

Brief Description of the Drawings

Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:

Figure 1 is shows schematically a side view of a multilayer planar device structure fabricated according to the present invention; Figures 2 to 8 show the process steps to form a device using the method of the present invention;

Figures 2 (a), (b) and (c) show the initial steps to form the one conducting electrode structure of the device;

Figures 3 (a), (b) and (c), respectively, show a plan view, side view and perspective view of the structure of Figure 2 after the formation of vias in the first insulating layer;

Figure 4 shows a side view of the structure shown in Figure 3 after deposition and patterning of the semiconductor layer;

Figures 5 (a), (b) and (c), respectively, show a plan view, side view and perspective view of the structure of Figure 4 after the deposition of a second insulating layer and the formation of vias in it;

Figures 6A and 6B, respectively, show a plan view and a side view of the structure shown in Figure 5 after the formation of a conducting electrode and via by imprinting; Figures 7A and 7B, respectively, show a plan view and a side view of the structure shown in Figures 6A and 6B after etching the residual conducting layer;

Figures 8 (a), (b) and (c), respectively, show a plan view, side view and perspective view of the structure of Figure 6 after depositing another semiconducting layer and etching it to expose the vias; and,

Figures 9 (a), (b) and (c), respectively, show a rotated plan view, side view and perspective view of the structure of Figure 7 after the formation of a further conducting electrode structure;

Figures 10 to 17 shows the process steps to form an active matrix display device using the method of the present invention.

Figure 10 shows a perspective of the structure after deposition of a conducting layer on a substrate;

Figure 11 shows the structure of figure 10 after imprinting the conducting layer to form bit lines; Figure 12 shows the structure of figure 11 after etching the residual conducting layer;

Figure 13 shows the structure of figure 12 after spinning on a layer of dielectric;

Figures 14A and 14B, respectively, show a perspective view and a plan view of the structure of figure 13 after spinning on another conducting layer and patterning it by imprinting;

Figures 15A and 15B, respectively, show the structure of figures 14A and 14B after etching the residual conducting layer;

Figure 16 shows the structure of figure 15A after spinning on a semi- conducting layer; and,

Figure 17 shows the final structure after applying a layer of electrophoretic display material to the structure of figure 16.

Detailed Description Figure 1 illustrates schematically an example of a structure for a relatively simple device 10 that may be fabricated according to the present invention. The basic structure comprises six layers, including a polymer substrate 11, a first conducting layer 12, a dielectric polymer layer 13, a semi-conducting layer 14, a further dielectric polymer layer 15, and a second conducting layer 16. The polymer substrate 11 acts as a dielectric and is used as a carrier for the rest of the structure. This layer may provide a temporary base for the remainder of the structure or else be integral to it. In the latter case the layer may actually be a protective base layer for the structure and may be formed on a further supporting layer, which acts as the temporary substrate during device fabrication and from which the device is removed once fabrication is complete. The conducting layer 12 is spun on over the layer 11 and is imprinted with a specific pattern. For example, this may be horizontal lines, known as rows or wordlines, which can act as an anode. After imprint, a reactive ion etch (RIE) step is used to remove the residual layer and isolate the patterns created.

The dielectric polymer layer 13, which acts as an insulator, is then spun on over the patterned electrode structure, filling in regions where the conducting material has been removed. The semi-conducting polymer layer 14 is spun over dielectric layer 14 and forms the switching material where the word and bit line electrodes cross in the final structure. This layer is imprinted to produce the desire pattern and the unwanted thin residual layer removed by etching. The further dielectric polymer layer 15 is spun on covering and filling spaces in the semi-conducting structure and the second conducting layer 16 is spun on over this and is imprinted to formed the desired conducting pattern. For example, this may be vertical lines, known as columns or bitlines, which can act as a cathode. Again, a RIE step is used to remove the residual thickness of this layer from the imprinted regions.

The complete structure 10 forms a bit word line addressing system, able to switch on and off specific elements by creating a charge at the cross over points, thereby affecting an adjacent material. When used for a display device, an additional layer of material, such as an electrophoretic material, may be deposited on top of this structure. The bit word line electrode structure enables individual pixels of the electrophoretic material to be addressed, thereby providing a complete 2-D display. For a colour display another two electrophoretic material layers are required to provide a separate layer each for red, green and blue pixels, and a suitable controlling electrode structure is required. This can be achieved either by repeating the basic structure 10 shown in figure 1 or else by means of a complex layering technique to allow pixels of different material layers to be controlled by the same anode and cathode layer. Both types of structure can be fabricated using the method of the present invention, thereby illustrating its great flexibility. Figures 2 to 8 show the process steps for forming a device comprising semiconducting components using the method of the present invention. The final device may include simple or complex electronic circuitry suitable for a variety of applications, including possible display applications. In the first steps a layer of conducting material, such as a metal or conducting polymer, is spun directly on to a substrate (or alternatively on to a protective base layer of material disposed on the substrate). The conducting layer is then patterned by imprinting, as shown in figure 2(a) to form a line electrode 202 on the substrate 201. Typically, the mechanical imprinting process will not force all of the conducting material out of regions other than where the conducting line is formed, but will leave behind a thin residual layer of the material 203. This is undesirable as a well-defined line electrode is required that is electrically isolated from any other electrodes in the layer. Therefore, a simple etch is performed to remove a thickness of material at least equal to the residual thickness layer and leave a clean electrode structure, as shown in figure 2(b). A layer of insulating material 204, preferably a polymer dielectric, is spun on covering the electrode structure, as shown in figure 2(c). As illustrated, there may be a raised region where the insulating material covers the electrode, but this layer can be planarised if desired. In order to enable a conductive path between the line electrode and a semiconducting structure located above the insulating layer, a via 205 (or more than one) is formed in the insulating layer as illustrated in figure 3. The via 205 is located at a point directly above the line electrode, as shown in figure 3(a). The via can be formed by any suitable method, including etching. However, the via may be formed by imprinting followed by a subsequent etch to remove any residual thickness of insulating material inside the imprinted via.

Following this, a layer of semi-conducting material, preferably a semiconducting polymer, is spun over the imprinted insulating layer and filling the via 205. This layer is then patterned by imprinting to produce the desired semi- conducting structure 206 and any residual thickness removed by etching, as shown in figure 4.

A further insulating layer 207, preferably a polymer dielectric, is then spun on over the semi-conducting structure and two vias formed in it by imprinting and residual etch, as shown in figure 5. The path provided by the two vias, 208 and 209, to parts of the underlying semi-conducting structure is clearly apparent from figure 5(a). Subsequent to this another conducting layer is deposited by spinning, which also fills the imprinted parts of the insulating layer to form the electrically conducting vias, 208 and 209.

As shown in figure 6A the conducting layer is imprinted to form a further line electrode 210 and an electrically conducting via 211, leaving behind a residual thickness of conducting material 212 over the whole structure. This residual layer 212 is removed by etching leaving behind the clean structure as shown in figures 7A and 7B. A further layer of insulating material 213 as is shown in figure 8, is deposited and a thin etch step performed to reveal the conducting via 211. Finally, a further conducting layer is deposited by spinning and then a word line electrode 214 formed by imprinting and residual etch, as shown in figure 9. The structure shown in figure 9 represents the complete core of a potential device, which may be completed by the addition of other material layers.

Figures 9 to 17 show the process steps for forming an active matrix display device using the method of the present invention. The device is known as an Active Matrix Organic light Emitting Diode (AMOLED) display, and uses a Thin Film Transistor (TFT) matrix to control the organic layers to form a pixel. The complete structure is a little different to the examples described above, but still employs broadly the same fabrication technique. Again the process commences with the deposition of a layer of conducting material 302 onto a substrate 301 by spinning, as shown in figure 10. Bit line electrodes, 303 and 304, are formed by imprinting and then an etch step to remove the residual thickness 305, as shown in figures 11 and 12, respectively. Following this, a layer of dielectric 306 is deposited by spinning, covering the line electrodes, 303 and 304, as shown in figure 13. A second conducting layer is then deposited by spinning and patterned by imprinting to form the detailed structure desired, including a word line electrode 307 and drain electrodes 308 and 309, as shown in figures 14A and 14B. An etch step is employed to remove the residual layer thickness 310 of conducting material and leave behind the clean conducting structure, as shown in figures 15A and 15B.

The process is completed by spin depositing a layer of semi-conducting material 311 over the structure covering the electrode structures 307, 308 and 309, as shown in figure 16, and finally applying a layer of an electrophoretic display material 312 as is shown in figure 17. Depending upon the material, any suitable technique may be employed for this last step, including spin deposition. The completed structure allows for bit- word line addressing of individual pixels defined by the drain electrode regions 308 and 309, which influence the properties of the overlying electrophoretic material and thereby the way light emerges from those pixel regions of the device. Any of the device structures described above may actually comprise a base protective layer formed on the substrate and on which the remainder of the device structure is formed. This base layer may only be weakly attached to the substrate allowing the device to be "peeled off' the substrate once complete. The base layer continues to protect the structure which, if formed from flexible polymer materials, may be flexed or rolled, once removed from the temporary more rigid substrate. For some types of device it may be desirable to apply an upper protective layer during fabrication as well. These layers may be transparent when applied to optical devices. For image sensor type devices the overall fabrication process may further include steps to form colour filter structures, such as Bayer filters.

Claims

1. A method of fabricating a multilayer planar electronic circuit device on a substrate comprising the steps of: providing a patterned layer of a first conducting material ; depositing a layer of a first insulating material; providing a patterned layer of a second conducting material.

2. A method according to claim 1, wherein the step of providing a patterned layer of a conducting material comprises the substeps of depositing a layer of a conducting material patterning the conducting material layer by imprinting to form a first conducting structure of the first conducting material.

3. A method according to claim 1, wherein the step of providing a patterned layer of a conducting material comprises the substeps of depositing a layer of a mixture of a polymer and an initiator, patterning said layer by imprinting, forming an electrically conductive metal region on the surface of the patterned layer by contacting the initiator with a solution comprising a reducing agent and a solution containing metal ions.

4. Method according to claim 1,2 or 3, further comprising the step of depositing a layer of a semiconducting material.

5. A method according to one of the previous claims, wherein the step of depositing is carried out by spinning.

6. A method according to one of the previous claims, the method further comprising the step of depositing a layer of a second insulating material by spinning;

7. A method according to any preceding claim, the method further comprising the step of disposing a base layer of a protective material onto the substrate, and wherein the layer of the first conducting material is deposited onto the protective base layer by spinning.

8. A method according to any preceding claim, the method further comprising the step of removing the multilayer planar electronic circuit from the substrate.

9. A method according to any preceding claim, wherein at least one of the first and second conducting structures comprises an electrode structure.

10. A method according to claim 9, wherein one of the first and second conducting structures comprises a bit-line electrode structure and the other of the first and second conducting structures comprises a word-line electrode structure.

11. A method according to any preceding claim, wherein at least one of the first and second conducting structures comprises a via for providing an electrical conducting path through a material layer deposited over the conducting structure.

12. A method according to claim 11, wherein the method further comprises the step of etching a thickness of the material layer deposited over the conducting structure to expose the underlying via.

13. A method according to any preceding claim, wherein the method further comprises the step of patterning the semi-conducting material layer by imprinting to form a semi-conducting structure of the semi-conducting material.

14. A method according to any preceding claim, wherein the method further comprises the step of patterning the first insulating material layer for forming at least one via therethrough.

15. A method according to claim 6, wherein the method further comprises the step of patterning the second insulating material layer for forming at least one via therethrough.

16. A method according to claim 14 or claim 15, wherein the first and/or second insulating material layer is patterned by imprinting for forming at least one via therethrough.

17. A method according to claim 14 or claim 15, wherein the first and/or second insulating material layer is patterned by etching for forming at least one via therethrough.

18. A method according to any of claims 1 to 3, wherein the method further comprises the step of depositing conducting or semiconducting material by spinning in a region of the first and/or second insulating material layer patterned for forming at least one via in order to form the via through the insulating material layer.

19. A method according to any preceding claim, the method further comprising the step of removing by etching a residual thickness of an imprinted material layer after the step of imprinting so as to leave behind only the desired structure formed of the imprinted material.

20. A method according to claim 19, wherein the step of etching is performed using a reactive ion etch process.

21. A method according to any preceding claim, wherein at least one of the conducting, semi-conducting and insulating materials is a polymer.

22. A method according to preceding claim, wherein at least one of the conducting, semi-conducting and insulating materials is a material derived from a sol-Gel process.

23. A method according to any of the previous claims, wherein a patterned region of the multilayer planar electronic circuit comprises a thin film transistor (TFT).

24. A method according to any of the preceding claims, wherein the method further comprises the step of applying a layer of a memory material.

25. A method according to any of the claims 4 to 22, wherein the semi-conducting material is applied as a precursor material or a precursor material mixed with a binding material and is transformed into a semi-conducting material by an irradiation or thermal anneal step.

26. A method according to any of the preceding claims, wherein the semiconducting material is an electroluminescent material.

27. A method according to any of claims 1 to 24, wherein the method further comprises the step of applying a layer of an electrophoretic material.

28. A multilayer planar electronic circuit device fabricated according to the method of any preceding claim.

29. An optical image sensor device comprising a multilayer planar electronic circuit device fabricated according to the method of any of claims 1 to 27.

30. An optical light emitting diode device comprising a multilayer planar electronic circuit device fabricated according to the method of claim 26.

31. An organic optical display comprising a multilayer planar electronic circuit device fabricated according to the method of claim 26 or claim 27.