WO2008016829A2

WO2008016829A2 - Light emitting semiconductor device having an electrical confinement barrier near the active region

Info

Publication number: WO2008016829A2
Application number: PCT/US2007/074480
Authority: WO
Inventors: Ralph H. Johnson; James R. Biard; James K. Guenter
Original assignee: Finisar Corporation
Priority date: 2006-07-31
Filing date: 2007-07-26
Publication date: 2008-02-07
Also published as: US20060268954A1; US7920612B2; CN101162752A; WO2008016829A3; CN101162752B

Abstract

Light emitting semiconductor devices such as VCSELs, SELs, and LEDs are manufactured to have a thin electrical confinement barrier in a confining layer near the active region of the device. The thin confinement barrier comprises a III-V semiconductor material having a high aluminum content (e.g. 80%-100% of the type III material). The aluminum content of the adjacent spacer layer is lower than that of the confinement barrier. In one embodiment the spacer layer has an aluminum content of less than 40% and a direct bandgap. The aluminum profile reduces series resistance and improves the efficiency of the semiconductor device.

Description

LIGHT EMITTING SEMICONDUCTOR DEVICE HAVING AN ELECTRICAL CONFINEMENT BARRIER NEAR THE ACTIVE REGION

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to light emitting semiconductor devices such as semiconductor lasers and light emitting diodes. More specifically, the invention relates to confinement of a free carrier in the active region of the semiconductor device. 2. Related Technology

Vertical-Cavity Surface-Emitting Lasers (VCSELs), Surface Emitting Lasers (SELs) and Light Emitting Diodes (LEDs) are becoming increasingly important for a wide variety of applications including optical interconnection of integrated circuits, optical computing systems, optical recording and readout systems, and telecommunications.

VCSELs, SELs, and LEDs are generally formed as a semiconductor diode. A diode is formed from a junction between a p-type material and an n-type material. In VCSELs, the p-type semiconductor material is most often aluminum gallium arsenide (AlGaAs) doped with a material such as carbon that introduces free holes or positive charge carriers, while the n-type semiconductor materials is typically AlGaAs doped with a material such as silicon that introduces free electrons, or negative charge carriers.

The PN junction forms an active region. The active region typically includes a number of quantum wells. Free carriers in the form of holes and electrons are injected into the quantum wells when the PN junction is forward biased by an electrical current. At a sufficiently high bias current the injected minority carriers form a population inversion in the quantum wells that produces optical gain which is used inside a resonant cavity to cause lasing in semiconductor lasers such as VCSELs.

Free carriers that escape the quantum wells into the surrounding semiconductor and recombine there do not contribute to the optical gain and are parasitic currents which generate heat and reduce the efficiency of the light emitting device. This "carrier leakage" is one of the causes of the rollover of the light vs current curve. Current can only be increased so much and then light output reaches a maximum and drops off. Generally, higher temperatures result in lower maximum light output partially because the thermal energy of the carriers, electrons and holes, is increased allowing a larger fraction to contribute to carrier leakage. Electrical confinement in the active region can be particularly problematic in VCSEL devices, which tend to require high current densities for operation and is made worse in the highest frequency VCSELs where the highest current densities are used.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to light emitting semiconductor devices such as VCSELs, SELs, and LEDs having a thin electrical confinement barrier in a confining layer near the active region of the device. The thin confinement barrier comprises a III-V semiconductor material having a high aluminum content (e.g. 80%-100% of the type III material).

The confinement barrier is sandwiched between the active region and a spacer layer. The aluminum content in the confinement barrier is higher than the aluminum content in the spacer layer such that a narrow spike in aluminum content is formed. The aluminum spike increases the band gap of the electrical confinement barrier, thereby increasing the confinement of the electrons and holes in the active region. The confinement barrier allows the aluminum content in the spacer layer to be lowered (e.g., to less than 40%) while maintaining or improving the confinement of free carriers in the active region. The lower aluminum content in the spacer layer increases the thermal conductivity, increases the electron and hole mobility, and thereby reduces the electrical resistance and the thermal impedance of the semiconductor device improving efficiency.

The confinement barrier is made very thin (e.g., between 5 and 30 nm thick). The thinness of the confinement barrier minimizes vertical resistance and improves the manufacturability of the epitaxial structure. High aluminum content material typically requires higher temperatures for crystal growth. The higher temperatures can be difficult to work with and can degrade other semiconductor layers or cause imperfections in the crystal lattice. By making the confining layer thin, many of these problems are avoided or minimized.

In an exemplary embodiment, the confining layer also includes a doping increase. The confinement layer is doped with a p-type or n-type dopant depending on whether the confinement barrier is on the n-side or p-side of the active region. An increase in the dopant in the confinement barrier can advantageously improve carrier confinement in the device and increase the efficiency of the device at high temperatures or high current densities. The features of the confining layers in the devices of the present invention improve confinement of free carriers in the active region. This improved confinement leads to a higher percentage of the carriers recombining in the quantum wells where they provide the desired optical emission or optical gain. Devices including the thin confining layers according to the present invention also show improvements in thermal conductivity and electrical resitance because of the ability to use more thermally and electrically conductive low Al spacers and because the high Al confining layers are also higher thermal conductivity and mobility than intermediate compositions.

These and other advantages and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

Figure 1 is an illustration of an exemplary vertical cavity surface emitting laser according to the present invention;

Figure 2 illustrates the confining layers and active region of the laser of Figure 1 in more detail; Figure 3 is a diagram of the aluminum profile of an exemplary device according to the present invention;

Figure 4 is a diagram of the aluminum profile of another exemplary device according to the present invention; and

Figure 5 reveals transition ramps of composition change from one layer to another of a distributed Bragg period of a VCSEL mirror.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present invention relates to light emitting semiconductor devices such as VCSELs, SELs, and LEDs having a thin electrical confining layer near the active region of the device. Various aspects of the present invention will now be illustrated in the context of a VCSEL. However, those skilled in the art will recognize that the features of the present invention can be incorporated into other light emitting semiconductor devices that have an active region. Figure 1 shows a planar, current-guided, vertical cavity surface emitting laser

(VCSEL) 10 having periodic layer pairs for top and bottom Bragg mirrors. A substrate 14 is formed on a bottom contact 12 and is doped with a first type of impurities (i.e. p- type or n-type dopant). A bottom mirror stack 16 is formed on substrate 14 and a bottom confining layer 20 is formed on bottom stack 16. The bottom confining layer 20 and a top confining layer 24 sandwich an active region 22. An upper mirror stack 26 is formed on the top confining layer 24. A metal layer 13 forms a contact on a portion of stack 26.

An isolation region 30 restricts the area of the current flow 27 through the active region 22. Region 30 can be formed by an ion implantation and/or oxidation.

Stacks 16 and 26 can be distributed Bragg reflector (DBR) stacks, and include periodic layers 41 and 42 (Figure 5). Periodic layers 41 and 42 are typically AlGaAs and AlAs, respectively, but can be made from other III-V semiconductor materials. Stacks 16 and 26 can be doped or undoped and the doping can be n-type or p-type depending on the particular VCSEL design. Various portions of the present discussion may refer to several configurations of the VCSEL. Metal contact layers 12 and 13 can be ohmic contacts that allow appropriate electrical biasing of laser diode 10. When VCSEL 10 is forward biased with a voltage on contact 13 different than the one on contact 12, active region 22 emits light 32 which passes through stack 26.

Figure 2 illustrates the active region 22 and confining layers 20 and 24. In an exemplary embodiment, the active region 22 is formed from a plurality of quantum wells 27 that are separated by quantum well barriers 25. Confining layer 24 includes a spacer layer 28 and a confinement barrier 19. The confinement barrier 19 is sandwiched between the active region 22 and spacer layer 28. Alternatively or in addition to confinement barrier 19, a confining layer 20 includes a confinement barrier 21 adjacent a spacer layer 30. The confinement barrier 21 is sandwiched between the active region 22 and spacer layer 30.

The thickness of the quantum well layers 27 and quantum well barriers 25 depends on the particular configuration of the light emitting device. In an exemplary embodiment, the quantum well layers 27 and the quantum well barriers 25 have a thickness in a range from about 50 Angstroms to about 100 Angstroms.

The confining layer thickness is dependent upon the kind of device being fabricated. In a vertical cavity resonant device such as a VCSEL, or VECSEL it provides for resonant spacing between mirrors and provides that the quantum wells of the active region are centered on a peak of the optical field.

In one aspect of the invention the thickness of the one or more confinement barriers is limited to minimize the vertical resistance and facilitate the manufacturability of the device. In a preferred embodiment, the thickness of confinement barrier is less than about 50 nm and more preferably about 20 nm. Even more preferably the thickness of the confining layer is in a range from about 2 nm to about 50 nm, more preferably in a range from about 5 nm to about 30 nm, and most preferably between 8 nm and 30 nm. Another measurement for limiting the thickness of the confining layer is its thickness relative to the spacer layer. In a preferred embodiment the confinement barrier has a thickness that is less than 20% of the total thickness of the spacer layer.

The confining layers and active region are formed from one or more types of III- V semiconductor materials or the like. Suitable semiconductor materials include GaAs, AlAs, InP, AlGaAs, InGaAs, InAlAs, InGaP, AlGaAsP, AlGaInP, InGaAsP, InAlGaAs, or the like. In a preferred embodiment, the semiconductor material is Al_xGai_-xAs, where x is between 0.0 and 1.0 (i.e. aluminum is 0.0% to 100%). Al_xGai_-xAs is particularly useful for making 850 nm VCSELs, which require high current densities and high optical output.

The shape of the transitions between compositions are an important variable. In general, however, transitions can be made in a wide variety of shapes including steps, linear ramps, parabolic ramps and more complex ramps. Because a given electron affinity may occur for 2 compositions, steps between compositions in n-type material can be used between 2 different compositions which have similar electron affinities.

The confinement barriers are created by varying the aluminum content in the confining layer. Figure 3 is an example that may be used to form confinement barriers above and below an active region. Spacer layer 20 has a composition of Al_zGai_-zAs. The confinement barrier 21 begins at point 60 with a with a transition to point 62 with a change of composition from Al_zGai_-zAs to Al_yGai_-yAs. From point 64 to point 66 is a transition 68 of composition from Al_yGai_-yAs to Al_wGai_-wAs. Between point 66 and point 70 is a transition 72 from Al_wGai_-wAs to Al_vGai_-vAs, which may be the composition of barrier 25 of quantum well 27. Similar transitions are performed in reverse order to form confining layer 24, thereby creating transition 74, transition 76, and transition 78. The values of y, z, w, and v may be values selected from a range from 0.0 to 1.0 for a desired design anywhere between 0.0 and 1.0. In a preferred embodiment spacer layers 20 and 24 have an aluminum content in a range from about 12% to about 65% (i.e., z is in a range from about 0.12 to about 0.65), more preferably from about 15% to about 45% (z ~ 0.15 to 0.45). The aluminum content in the active region is typically between 0% and about 50%. The quantum well barriers preferably have an aluminum content in a range from 15% to about 50% (w ~ 0.15 to 0.50) and the quantum wells preferably have less than 15% aluminum, most preferably about 0% aluminum.

In a preferred embodiment, the aluminum content in the confinement barrier is in a range from about 60% to about 100% (y ~ 0.60 to 1.0), more preferably between about 70% and 100% (y ~ 0.70 to 1.0). For oxide confined lasers it can be advantageous to have an aluminum content in the confinement barrier that is less than 100% to avoid undesired oxidation. In this embodiment, the aluminum content in the confinement barrier is preferably less than about 85% (e.g. between 60% and 85%).

In one embodiment, the confinement barriers can be described according to the differential in aluminum content between the confinement barrier and the adjacent spacer layer. In a preferred embodiment, the percentage of aluminum content in the confining layer is greater by at least about 15%, more preferably greater by at least about 20%, and most preferably greater by at least about 25% (e.g., the spacer layer has 40% Al and the confinement barrier has 65% Al).

In one embodiment of the present invention, the confinement barriers 19 and 21 can include a doping spike in addition to the aluminum spike. The doping spike in the confinement barrier is preferably in a range from about 5x10¹⁷ to about 1x10¹⁹ on the bottom or n-side of the active region and preferably in a range from about 5xlO¹⁷ to about 6xlO¹⁸ in the confinement barrier on the upper or p-side of the active region. Most preferably the doping in either confinement barrier is in a range from about IxIO¹⁸ to about 3x10¹⁸. Similar to the aluminum spike, the doping spike in the confinement barrier is selected relative to the dopant level in the spacer layer. In an exemplary embodiment, the dopant level in the spacer layer is in a range from about IxIO¹⁷ to about IxIO¹⁸. In a preferred embodiment, the dopant in the confinement barriers is between about 1.5 and 8 times greater than in the spacer layers, more preferably between about 1.5 and 4 times greater than in the spacer layer.

The confinement barriers 19 and 21 advantageously provide confinement for free carriers in the active region. Barrier 19 and 21 can have the same or different peak levels of aluminum. Furthermore, device 10 can benefit from having just one confinement barrier either above or below the active region; however it is typically preferred to provide an n-side confinement barrier and a p-side confinement barrier.

The confinement barrier can be particularly advantageous for device operation at high temperature and/or high bias currents where minority carrier confinement may be lost. Loss of confinement is undesirable because it decreases the efficiency of the light emitting semiconductor device. With n-doping in the confinement barrier layer, the full bandgap of AlAs or similar material may be extended into the valence band. A confinement barrier layer thickness of 2 run to 20nm, more preferably 8 run to IOnm should be sufficient to confine the minority carriers. Thus, the minority carriers injected into the quantum well region may be contained in that region by the presence of the confinement barrier (i.e. a hole barrier confines holes and an electron barrier confines electrons). The loss of free carrier confinement can be dramatically reduced or even eliminated.

The A1.65Ga.35As alloy normally used in the spacer layer provides a large barrier to free carriers in the valence band which ensures good confinement at high bias levels and high temperature, but has an undesirable indirect bandgap. This gives relatively low electron mobility and high vertical series resistance for a given doping level in the n- spacer.

In an exemplary embodiment of the present invention, the one or more spacer layers can have an aluminum composition less than 45% (e.g. 0.389 or 0.328), which can benefit the device in several ways. First, the graded region between the Bragg mirror and spacer can be replaced with a step in composition to an alloy with the same electron affinity as the mirror layer. This reduces the barrier to electron flow found in previous designs using the linear grade in aluminum composition and result in a reduction in series resistance. The spacer layer can then be a direct bandgap semiconductor. The scattering of majority carriers from the indirect X conduction band to the direct F conduction band now occurs at the Bragg mirror rather than near the quantum wells. This can eliminate the risetime limitation associated with having that transition near the quantum wells. Second the fact that the spacer is a direct bandgap material gives it a much higher electron mobility. Therefore, a given series resistance can be obtained with a much lower donor doping concentration. This reduces the free carrier absorption close to the quantum wells where the E-field standing wave has the highest amplitude. Decreased free carrier absorption can improve the efficiency of the VCSEL.

Third, with the direct bandgap spacer, the ramp from e.g., 0.389 or 0.328 aluminum fraction to the 0.25 aluminum fraction in the quantum well barrier layer is all direct bandgap and should not impose a speed limitation on the VCSEL. Fourth, using a step function in the Al fraction from the Bragg mirror layer to the direct band gap spacer with the same electron affinity avoids DX center range of Al fraction between 0.40 and 0.60.

Figure 4 illustrates another exemplary embodiment. The lower spacer, 80, has an aluminum composition between 10 and 20 % and is doped n-type at 2el6-5el7/cm3. The lower spacer is followed by a linear ramp 81 to 25 % where the doping is ramped from that of the spacer to about 2el8/cm3 n-type with a linear ramp which is about 10 run thick. This is followed by a step at 82 to about 85 %. The 85 % layer 84 is doped about 2el8/cm3 n type and has a thickness between 12 and 25 nm. This is followed by a linear ramp 86 in composition to about 65 % which is 5 nm with a doping of 2el8/cm3 n-type. This is followed by a 10 nm region 88 of 65 % which is n doped at 2el8. This is followed by an undoped linear ramp 90 with a length of 15 nm from 65 % to 25 %. This is followed by the quantum well active region with quantum wells and barriers. The p-side begins with a ~3el8 p-doped ramp 92 which is about 7.5 nm thick to a composition of 85 %. The 85 % layer 94 is from ~2el8 p doped and is about 20 nm thick. This is followed by a 20 nm ramp 96 at a doping starting at 2el8 ramping to about 5el7/cm3 with a final composition which matches the p-spacer 98. The p-spacer has a composition of between 10 and 20 % and a doping of 5 el 7 p-type.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

What is claimed is:

I. A light emitting semiconductor device comprising a III-V semiconductor material and having improved electrical confinement in the active region, comprising: an active region; an electrical confining layer positioned adjacent the active region, the confining layer comprising: a spacer layer; a confinement barrier positioned between the spacer layer and the active region and having a thickness that is in a range from about 2 nm to about 50 nm, the confinement barrier having an aluminum content greater than that of the spacer layer, thereby creating a spike in the aluminum content near the active region.

2. A semiconductor device as in claim 1, wherein the electrical confining layer comprises a dopant increase in the confinement barrier.

3. A semiconductor device as in claim 1, wherein the aluminum content of the confinement barrier is greater than that of the spacer layer by between 10% and 40%.

4. A semiconductor device as in claim 1, wherein the aluminum content of the confinement barrier is greater than that of the spacer layer by greater than 40%.

5. A semiconductor device as in claim 1, wherein the aluminum content of the confinement barrier is greater than 80%.

6. A semiconductor device as in claim 1 , wherein the thickness of the confinement barrier is in a range from about 5 nm to about 20 nm.

7. A semiconductor device as in claim 1 , wherein the thickness of the confinement barrier is between 8 nm and 10 nm.

8. A semiconductor device as in claim 1, wherein the III-IV semiconductor material comprises Al_xGai_-xAs, wherein x is between 0.0 and 1.0.

9. A semiconductor device as in claim 1, wherein the confining layer is on the upper side of the active region.

10. A semiconductor device as in claim 1, wherein the confining layer is on the bottom side of the active region.

I I. A semiconductor device as in claim 10, further comprising a second confinement barrier within a confining layer on the upper side of the active region.

12. A semiconductor device as in claim 1 , wherein the spacer layer has a composition that gives it a direct band gap.

13. A semiconductor device having a confinement barrier to improve electron confinement in the active region, comprising: a substrate; and an epitaxial structure deposited on the substrate, the epitaxial structure comprising: a bottom mirror and an upper mirror; an active region between the bottom mirror and the upper mirror; a confining layer comprising a III- V semiconductor material and being positioned adjacent the active region, the confining layer having, a spacer layer; a confinement barrier positioned between the active region and the spacer layer, the confinement barrier having an aluminum content and a dopant level that is greater than that of the spacer layer.

14. A semiconductor device as in claim 13, wherein the confinement barrier is on a bottom side of the active region.

15. A semiconductor device as in claim 14, wherein the dopant level is between about 5 x 10¹⁷/cm³ to about 6 x 10¹⁸/cm³ in the confinement barrier.

16. A semiconductor device as in claim 14, wherein the dopant level is between about 1 x 10¹⁸/cm³ to about 3 x 10¹⁸/cm³ in the confinement barrier.

17. A semiconductor device as in claim 13, wherein the confining layer is on an upper side of the active region.

18. A semiconductor device as in claim 17, wherein the dopant level is between about 5 x 10¹⁷/cm³ to about 1 x 10¹⁹/cm³.

19. A semiconductor device as in claim 17, wherein the dopant level is between about 1 x 10¹⁸/cm³ to about 3 x 10¹⁸/cm³.

20. A semiconductor device as in claim 13, wherein the aluminum content of the confinement barrier is greater than that of the spacer layer by between 10% and 40%.

21. A semiconductor device as in claim 13, wherein the aluminum content of the confinement barrier is greater than that of the spacer layer by greater than 40%.

22. A semiconductor device as in claim 13, wherein the confining layer is less than about 20 nm thick.

23. A semiconductor device as in claim 13, wherein the aluminum content of the spacer layer is less than 45%.

24. A III-V semiconductor device having a confinement barrier to improve electron confinement in the active region, comprising: a substrate; and an epitaxial structure deposited on the substrate, the epitaxial structure comprising: a bottom mirror and an upper mirror; an active region between the bottom mirror and the upper mirror; a first confining layer above the active region, the confining layer comprising a first confinement barrier, the first confinement barrier having a thickness in a range from about 2 nm to about 50 nm, an aluminum content in a range from about 60% to about 100%, and a dopant level in a range of about 5 x 10¹⁷/cm³ to about 6 x 10¹⁸/cm³, and wherein the aluminum content and dopant level of the first confinement barrier is greater than that of the material directly above the first confinement barrier; and a second confining layer below the active region, the second confining layer comprising a second confinement barrier, the confinement barrier having a thickness in a range from about 2 nm to about 50 nm, an aluminum content in a range from about 60% to about 100%, and a dopant level in a range of about 5 x 10¹⁷/cm³ to about 1 x 10¹⁹/cm³, and wherein the aluminum content and dopant level of the confinement barrier is greater than that of the layer directly below the second confinement barrier.

25. A semiconductor device as in claim 24, wherein the aluminum content of the first and second confinement barriers is greater than that of the material respectively above and below by about by at least 15%.

26. A semiconductor device as in claim 24, wherein the aluminum content of the first and second confinement barriers is greater than that of the material respectively above and below by about by at least 30%.

27. A semiconductor device as in claim 24, wherein the semiconductor device is an oxidized laser.

28. A semiconductor device as in claim 24, wherein the dopant level in the first and second confinement barriers is between about 1 x 10¹⁸/cm³ to about 3 x 10¹⁸/cm³.