WO2007136655A3 - System to detect and identify errors in control information, read data and/or write data - Google Patents

System to detect and identify errors in control information, read data and/or write data Download PDF

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Publication number
WO2007136655A3
WO2007136655A3 PCT/US2007/011733 US2007011733W WO2007136655A3 WO 2007136655 A3 WO2007136655 A3 WO 2007136655A3 US 2007011733 W US2007011733 W US 2007011733W WO 2007136655 A3 WO2007136655 A3 WO 2007136655A3
Authority
WO
WIPO (PCT)
Prior art keywords
crc
integrated circuit
controller device
codes
generated
Prior art date
Application number
PCT/US2007/011733
Other languages
French (fr)
Other versions
WO2007136655A2 (en
Inventor
Ian Shaeffer
Craig Hampel
Original Assignee
Rambus Inc
Ian Shaeffer
Craig Hampel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Ian Shaeffer, Craig Hampel filed Critical Rambus Inc
Priority to JP2009511054A priority Critical patent/JP2009537899A/en
Priority to EP07794938A priority patent/EP2024834A2/en
Publication of WO2007136655A2 publication Critical patent/WO2007136655A2/en
Publication of WO2007136655A3 publication Critical patent/WO2007136655A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Abstract

An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.
PCT/US2007/011733 2006-05-18 2007-05-16 System to detect and identify errors in control information, read data and/or write data WO2007136655A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009511054A JP2009537899A (en) 2006-05-18 2007-05-16 System for detecting and identifying errors in control information, read data and / or write data
EP07794938A EP2024834A2 (en) 2006-05-18 2007-05-16 System to detect and identify errors in control information, read data and/or write data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/436,284 2006-05-18
US11/436,284 US20070271495A1 (en) 2006-05-18 2006-05-18 System to detect and identify errors in control information, read data and/or write data

Publications (2)

Publication Number Publication Date
WO2007136655A2 WO2007136655A2 (en) 2007-11-29
WO2007136655A3 true WO2007136655A3 (en) 2008-02-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/011733 WO2007136655A2 (en) 2006-05-18 2007-05-16 System to detect and identify errors in control information, read data and/or write data

Country Status (5)

Country Link
US (2) US20070271495A1 (en)
EP (1) EP2024834A2 (en)
JP (1) JP2009537899A (en)
KR (1) KR20090028538A (en)
WO (1) WO2007136655A2 (en)

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KR20090028538A (en) 2009-03-18
US20070271495A1 (en) 2007-11-22
EP2024834A2 (en) 2009-02-18
US20080163007A1 (en) 2008-07-03
US7836378B2 (en) 2010-11-16
WO2007136655A2 (en) 2007-11-29
JP2009537899A (en) 2009-10-29

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