WO2007117718A2 - Simplified pitch doubling process flow - Google Patents

Simplified pitch doubling process flow Download PDF

Info

Publication number
WO2007117718A2
WO2007117718A2 PCT/US2007/011525 US2007011525W WO2007117718A2 WO 2007117718 A2 WO2007117718 A2 WO 2007117718A2 US 2007011525 W US2007011525 W US 2007011525W WO 2007117718 A2 WO2007117718 A2 WO 2007117718A2
Authority
WO
WIPO (PCT)
Prior art keywords
mandrels
pattern
spacers
hard mask
mask layer
Prior art date
Application number
PCT/US2007/011525
Other languages
French (fr)
Other versions
WO2007117718A3 (en
Inventor
Ardavan Niroomand
Baosuo Zhou
Ramakanth Alapati
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to EP07794840.4A priority Critical patent/EP2011141B1/en
Priority to JP2009504360A priority patent/JP5229588B6/en
Priority to KR1020087027277A priority patent/KR101368544B1/en
Priority to CN2007800125255A priority patent/CN101416278B/en
Publication of WO2007117718A2 publication Critical patent/WO2007117718A2/en
Publication of WO2007117718A3 publication Critical patent/WO2007117718A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to integrated circuit fabrication, and more specifically to simplified processes for forming pitch doubled integrated circuit features.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • FE ferroelectric
  • DRAM typically comprises millions of identical circuit elements, known as memory cells.
  • a typical memory cell consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one binary digit ("bit") of data. A bit can be written to a memory cell through the transistor and read by sensing charge on the reference electrode of the storage capacitor.
  • bit binary digit
  • the sizes of the memory devices incorporating memory cells can likewise be decreased.
  • the storage capacities of these devices can be increased by fitting more memory cells into the memory devices.
  • flash memory for example, electrically erasable programmable read only memory or "EEPROM"
  • EEPROM electrically erasable programmable read only memory
  • a typical flash memory comprises a memory array, which includes a large number of memory cells.
  • the memory cells include a floating gate field effect transistor capable of holding a charge. The data in a memory cell is determined by the presence or absence of charge on the floating gate.
  • the cells are usually grouped into sections called “erase blocks.”
  • the memory cells of a flash memory array are typically arranged into a "NOR" architecture (in which each memory cell is directly coupled to a bit line) or a “NAND” architecture (in which memory cells are coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).
  • the memory cells within an erase block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
  • memory devices typically include large patterns or arrays of electrical devices and conductors that are used to interconnect the electrical devices.
  • the "pitch" of such a pattern is defined as the distance between an identical point in two neighboring features in the pattern. These features are typically defined by openings in, and are spaced apart from each other by, a material such as an insulator or conductor.
  • pitch can be understood as the sum of the width of a feature and the width of the space separating that feature from a neighboring feature.
  • a method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels.
  • the method further comprises using an atomic layer deposition technique to deposit an oxide material onto the plurality of mandrels.
  • the method further comprises anisotropically etching the oxide material from exposed horizontal surfaces.
  • the method further comprises etching the photoresist material selectively with respect to the oxide material, thereby forming a plurality of oxide spacers.
  • a method of forming a memory device comprises forming a plurality of mandrels over a substrate. The mandrels are separated by exposed portions of the substrate.
  • the method further comprises depositing a spacer material over the mandrels and over the exposed portions of the substrate using an atomic layer deposition technique conducted at a temperature less than about 100 0 C.
  • the method further comprises anisotropically etching the spacer material from (a) exposed horizontal surfaces of the plurality of mandrels and (b) the exposed portions of the substrate. Spacer material is left remaining on vertical sidewalls of the plurality of mandrels.
  • a method of forming an integrated circuit comprises forming a plurality of mandrels on a hard mask layer.
  • the mandrels comprise a photosensitive material.
  • the method further comprises depositing a spacer material using an atomic layer deposition technique.
  • the spacer material covers the plurality of mandrels.
  • the method further comprises anisotropically etching the spacer material from horizontal surfaces, thereby exposing photosensitive material.
  • the method further comprises removing exposed photosensitive material after anisotropically etching the spacer material, thereby leaving a pattern of spacers on the hard mask layer.
  • the method further comprises transferring the pattern of spacers to the hard mask layer.
  • the method further comprises etching the pattern of spacers from the hard mask layer.
  • a method of integrated circuit fabrication comprises using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer.
  • the mandrels comprise a photoresist material.
  • the method further comprises forming a pattern of spacers around the mandrels.
  • the pattern of spacers has a pitch that is smaller than a minimum resolvable pitch of the lithographic technique.
  • the pattern of spacers is formed from an oxide material.
  • the pattern of spacers is deposited using an atomic layer deposition technique at a temperature less than about 100 0 C.
  • a method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region.
  • the method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region.
  • the method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region.
  • the method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region.
  • the method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
  • a method of forming a memory device comprises forming a plurality of mandrels over a substrate in an array region of the memory device.
  • the mandrels optionally comprise a photoresist material.
  • the mandrels are separated by exposed portions the substrate.
  • the method further comprises depositing a spacer material over the mandrels, over the exposed portions of the substrate, and over a peripheral region of the memory device.
  • the method further comprises depositing a peripheral mask, over the spacer material in the peripheral region of the memory device.
  • the method further comprises anisotropically etching the spacer material from exposed horizontal surfaces. Spacer material is left remaining (a) on vertical sidewalls of the mandrels in the array region, and (b) between the substrate and the peripheral mask in the peripheral region.
  • a method of forming an integrated circuit comprises forming a plurality of mandrels on a hard mask layer in an array region.
  • the mandrels comprise a photoresist material.
  • the method further comprises depositing an oxide material over the array region and over a peripheral region that surrounds the array region.
  • the oxide material covers the plurality of mandrels.
  • the method further comprises forming a pattern of photoresist material over the oxide material in the peripheral region.
  • the method further comprises anisotropically etching the oxide material from horizontal surfaces in the array region.
  • the method further comprises removing exposed photoresist material from the array region and the peripheral region after anisotropically etching the oxide material.
  • a method of integrated circuit fabrication comprises using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer in an integrated circuit array region.
  • the mandrels comprise a photoresist material.
  • the method further comprises forming a pattern of spacers around the plurality of elongate mandrels.
  • the pattern of spacers have a pitch that is smaller than a minimum resolvable pitch of the lithographic technique.
  • the spacers are formed from an oxide material that is deposited at a temperature less than about 100 0 C.
  • a partially formed integrated circuit comprises a substrate.
  • the partially formed integrated circuit further comprises a hard mask layer positioned over the substrate.
  • the partially formed integrated circuit further comprises a plurality of spacer loops that are formed directly over the hard mask layer, and that are at least partially positioned in an array region of the partially formed integrated circuit.
  • the partially formed integrated circuit further comprises a mask at least partially defined in a peripheral region of the partially formed integrated circuit, wherein the mask is also directly formed over the hard mask layer.
  • Figure 1A is a schematic cross-sectional view of a substrate having a plurality of mask lines formed thereon.
  • Figure 1 B is a schematic cross-sectional view of the substrate of Figure 1A after performing an anisotropic etch process that transfers the mask pattern into a temporary layer.
  • Figure 1C is a schematic cross-sectional view of the substrate of Figure 1B after removing the mask lines and performing an isotropic "shrink" etch.
  • Figure 1D is a schematic cross-sectional view of the substrate of Figure 1C after blanket depositing a spacer material over mandrels left in the temporary layer.
  • Figure 1E is a schematic cross-sectional view of the substrate of Figure 1D " after performing a directional spacer etch to leave pitch-multiplied features or spacers.
  • Figure 1 F is a schematic cross-sectional view of the substrate of Figure 1 E after removing the mandrels.
  • Figure 2A is a schematic cross-sectional view of an example partially formed integrated circuit.
  • Figure 2B is a schematic top view of the partially formed integrated circuit of Figure 2A.
  • Figure 3A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 2A after forming lines in an array region in a photoresist layer.
  • Figure 3B is a schematic top view of the partially formed integrated circuit of Figure 3A.
  • Figure 4A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 3A after performing a trim etch.
  • Figure 4B is a schematic top view of the partially formed integrated circuit of Figure 4A.
  • Figure 5A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 4A after blanket depositing a low temperature spacer material over photoresist mandrels.
  • Figure 5B is a schematic top view of the partially formed integrated circuit of Figure 5A.
  • Figure 6A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 5A after defining features in the peripheral region.
  • Figure 6B is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer is blanket deposited over substantially the entire peripheral region.
  • Figure 6C is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer is patterned to define periphery features.
  • Figure 6D is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer partially overlaps the low temperature spacer material.
  • Figure 7A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 6A after performing an anisotropic etch of the low temperature spacer material.
  • Figure 7B is a schematic top view of the partially formed integrated circuit of Figure 7A.
  • Figure 8A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 7A after removing exposed photoresist material.
  • Figure 8B is a schematic top view of the partially formed integrated circuit of Figure 8A.
  • Figure 9A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 8A after transferring the pattern of spacers into underlying hard mask layers.
  • Figure 9B is a schematic top view of the partially formed integrated circuit of Figure 9A.
  • the lines 10 are optionally shrunk using an isotropic etch.
  • the pattern is then transferred by an etch step, such as an anisotropic etch step, to the layer of expendable material 20, thereby forming placeholders or mandrels 40.
  • the photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in Figure 1C.
  • a layer of spacer material 50 is subsequently deposited over the mandrels 40, as shown in Figure 1 D.
  • Spacers 60 are then formed on the sides of the mandrels 40 by preferentially etching the spacer material from the horizontal surfaces in a directional spacer etch, as shown in Figure 1 E.
  • the remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in Figure 1 F.
  • a given pattern area formerly defined one feature and one space (each having a width F, for a pitch of 2F)
  • the same pattern area now includes two features and two spaces, as defined by spacers 60 (each having a width ⁇ F, for a pitch of F). Consequently, the smallest feature size possible with a photolithographic technique is effectively decreased by using the pitch doubling technique.
  • pitch doubling or more generally, “pitch multiplication”.
  • pitch multiplication By forming multiple layers of spacers upon each other, the definable feature size can be made even smaller.
  • the terms “pitch multiplication” and “pitch doubling” refer to the process generally, regardless of the number of times the spacer formation process is employed.
  • Some proposed methods for forming patterns in the periphery and in the array of a memory device involve use of two separate carbon layers.
  • the mandrels used to define spacer loops are formed in an upper carbon layer.
  • the array pattern is transferred to a lower carbon layer. While this process does allow features of different sizes to be formed in the array and periphery regions, use of a low temperature oxide material to define the spacer loops allows mandrels to be formed from the existing photoresist layer. This advantageously allows the top carbon layer to be omitted, thereby simplifying production.
  • the feature pattern to be transferred to a substrate has a pitch below the minimum pitch of the photolithographic technique used for processing the substrate.
  • certain embodiments can be used to form arrays of features, including logic or gate arrays and volatile and non-volatile memory devices such as DRAM, phase change memory (“PCM”), programmable conductor random access memory (“PCRAM”), read only memory (“ROM”), flash memory.
  • pitch multiplication is usable to form, for example, transistor gate electrodes and conductive lines in the array region of the devices.
  • the logic array can be a field programmable gate array (“FPGA") having a core array similar to a memory array and a periphery with supporting logic circuits. Exemplary masking steps in the course of fabricating a memory device are illustrated in the figures and are described herein.
  • Figures 2A and 2B illustrate schematic cross-sectional and top views, respectively, of an example partially fabricated integrated circuit 100, such as a memory device.
  • Figure 2B illustrates that the integrated circuit 100 comprises a central array region 102 that is surrounded by a peripheral region 104. It will be appreciated that, after the integrated circuit 100 is fabricated, the array region 102 will typically be densely populated with conducting lines and electrical devices such as transistors and capacitors. Pitch multiplication can be used to form features in the array region 102, as discussed herein.
  • the peripheral region 104 optionally can include features more complicated and/or larger than those in the array region 102.
  • Conventional photolithography, rather than pitch multiplication, is typically used to pattern these more complicated and/or larger features, examples of which include various types of logic circuitry.
  • the geometric complexity of the logic circuits located in the peripheral region 104 makes using pitch multiplication difficult in this region of the integrated circuit 100.
  • the regular grid typical of array patterns is conducive to pitch multiplication.
  • some devices in the peripheral region 104 may require larger geometries due to electrical constraints, thereby making pitch multiplication less advantageous than conventional photolithography for such devices.
  • FIG. 2A illustrates that the partially formed integrated circuit 100 includes a substrate 106 having a first hard mask layer 108 formed thereover.
  • the first hard mask layer 108 comprises a material such as silicon nitride, silicon oxide, or an organic material, such as an amorphous carbon material, a polymer material, or a spin on dielectric material.
  • the first hard mask layer 108 comprises a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. In other modified embodiments, the first hard mask layer 108 is omitted.
  • An optional second hard mask layer 110 is formed over the first hard mask layer 108.
  • the second hard mask layer 110 preferably comprises an inorganic material-
  • Example materials for the second hard mask layer 110 include silicon nitride, polycrystalline silicon, or a dielectric antireflective coating ("DARC"), such as silicon-rich silicon oxynitride.
  • the material comprising the second hard mask layer 110 can be selectively etched with respect to subsequently- deposited spacer materials.
  • Use of a DARC for the second hard mask layer 110 can be particularly advantageous for forming patterns having pitches near the resolution limits of a photolithographic technique.
  • a DARC can enhance resolution by reducing light reflections, thus increasing the precision with which photolithography can define the edges of a pattern.
  • the second hard mask layer 110 is omitted in embodiments wherein the first hard mask layer 108 can be etched selectively with respect to subsequently deposited spacer materials. In still other embodiments, the second hard mask layer 110 is replaced with an organic spin on antireflective coating ("ARC") positioned between the first hard mask layer 108 and the subsequently described overlying array photoresist layer.
  • ARC organic spin on antireflective coating
  • An array photoresist layer 111 is formed over the second hard mask layer 110.
  • the array photoresist layer 111 preferably comprises photosensitive material, such as a photoresist material that is compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems such as 13.7 nm wavelength systems, or electron beam lithographic systems.
  • photoresist materials include argon fluoride sensitive photoresist (that is, photoresist suitable for use with an argon fluoride light source) and krypton fluoride sensitive photoresist (that is, photoresist suitable for use with a krypton fluoride light source).
  • Argon fluoride photoresists are preferably used with shorter wavelength photolithography systems, such as 193 nm wavelength systems.
  • Krypton fluoride photoresists are preferably used with longer wavelength photolithography systems, such as 248 nm wavelength systems.
  • the array photoresist layer 111 comprises a photoresist material that can be patterned by nano-imprint lithography, such as by using a mold or a mechanical force to pattern the photoresist material.
  • the materials for the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are chosen based on the chemistry and the process conditions for the various pattern forming and transfer steps disclosed herein.
  • the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can each be selectively etched with respect to each other.
  • a material is considered “selectively etched" (or “preferentially etched") when the etch rate for that material is greater than that for a neighboring material.
  • a "selectively etchable" material has an etch rate that is at least about 2 times greater, at least about 10 times greater, at least about 20 times greater, or at least about 40 times greater than that for a neighboring material.
  • etch rate that is at least about 2 times greater, at least about 10 times greater, at least about 20 times greater, or at least about 40 times greater than that for a neighboring material.
  • other layers are added if suitable other materials, chemistries and/or processes conditions are used.
  • the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can be formed using deposition processes such as spin-on coating, sputtering, chemical vapor deposition ("CVD"), or atomic layer deposition.
  • CVD chemical vapor deposition
  • a low temperature CVD process (less than about 550 0 C, less than about 450 0 C, or even less than about 400 0 C) advantageously reduces chemical and/or physical disruption of an amorphous carbon layer, and thus is useful for deposition of materials over an existing amorphous carbon layer, such as the first hard mask layer 108. Additional information regarding the formation of amorphous carbon layers, including doped amorphous carbon layers, is provided in U.S. Patent 6,573,030 (issued 3 June 2003) and U.S. Patent Application Publication 2005/0042879 (published 24 February 2005). The entire disclosure of this patent and patent application publication is hereby incorporated by reference herein.
  • the thicknesses of the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are also chosen depending upon compatibility with the etch chemistries and process conditions disclosed herein. For example, when etching a material through a mask of another material, such as when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree.
  • the upper layer is preferably sufficiently thick such that it is not completely worn away over the course of the pattern transfer.
  • the second hard mask layer 110 is preferably between about 10 nm and about 40 nm thick, and is more preferably between about 15 nm and about 30 nm thick.
  • the thickness of the array photoresist layer 111 depends on the wavelength of light used to pattern the array photoresist layer 111. In an example embodiment wherein 248 nm light is used to perform photolithography, the array photoresist layer 111 is preferably between about 50 nm and about 300 nm thick, and is more preferably between about 200 nm and 250 nm thick. This height can vary depending upon the wavelength of light used to pattern the photoresist layer. Because lines are subsequently formed in the array photoresist layer 111, in certain embodiments the height of the array photoresist layer 111 is limited by the structural integrity and the aspect ratio of the lines to be formed, since tall spacer lines may collapse or otherwise deform.
  • a pattern is defined in the array photoresist layer 111 that comprises trenches 122 delimited by lines 124.
  • this pattern can be found anywhere on the substrate; defining the pattern in the array region merely represents a particular embodiment with particular advantages.
  • the trenches 122 can be formed by, for example, photolithography with 248 nm or 193 nm light, in which the array photoresist layer 111 is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefinable material, which is photoresist in the illustrated embodiment, forms mask features such as the illustrated lines 124. In other embodiments, maskless lithography, or maskless photolithography can also be used to define the lines 124.
  • the pitch of the resulting lines 124 is equal to the sum of the width of a line 124 and the width of a neighboring trench 122.
  • the pitch can be at or near the limits of the photolithographic technique used to pattern the array photoresist layer 111.
  • the pitch of the lines 124 is preferably between about 80 nm and about 150 nm, and is more preferably between about 90 nm and about 120 nm.
  • the pitch is the minimum pitch of the photolithographic technique and the subsequently-formed pitch multiplied spacer pattern advantageously has a pitch below the minimum pitch of the photolithographic technique.
  • the lines 124 are formed having larger feature sizes, such as 200 nm, to reduce errors in the positions and sizes of the lines 124.
  • the trenches 122 are preferably widened by etching the lines 124, to form modified trenches 122' and modified lines 124'.
  • the lines 124 are preferably etched using a isotropic etch to "shrink" these features. Suitable etches include etches using an oxygen-containing plasma, such as a S0 2 /O 2 /N 2 /Ar plasma, a C£ 2 /O 2 /He plasma, or a HBr/O 2 /N 2 plasma.
  • the extent of the etch is preferably selected so that the width of the modified lines 124' is substantially equal to the desired spacing between subsequently-formed pitch doubled features.
  • the width of the lines 124 is reduced from between about 80 nm and about 120 nm to between about 35 nm and about 70 nm, and in another embodiment the width is reduced to between about 40 nm and about 50 nm.
  • the width-reducing etch allows the modified lines 124' to be narrower than would otherwise be possible using the photolithographic technique used to form the lines 124. Additionally, the etch can provide the modified lines 124' with smoothed edges, thus improving the uniformity of the modified lines 124'.
  • a blanket layer of low temperature spacer material 126 is deposited over the modified lines 124'.
  • the low temperature spacer material 126 comprises a layer of oxide material deposited using an atomic layer deposition ("ALD") technique.
  • ALD atomic layer deposition
  • photoresist materials are not as tolerant of high temperatures as inorganic or carbon materials. Therefore, forming the spacers from a low temperature oxide material advantageously allows a separate mandrel layer deposition, pattern and transfer to be eliminated, with the patterned array photoresist layer 111 serving the same function.
  • the low temperature spacer material is deposited at less than about 200 0 C in one embodiment, at less than about 100°C in another embodiment, at less than about 80 0 C in another embodiment, and at less than about 75°C in another embodiment.
  • the low temperature spacer material 126 is deposited in an ALD process using SiaC ⁇ , H 2 O and C5H5N precursors.
  • the spacer material 126 is deposited to a thickness that is between about 20 nm and about 65 nm in one embodiment, between about 25 nm and about 60 nm in another embodiment, and between about 30 nm and about 55 nm in another embodiment.
  • the spacer material thickness is between about 30 nm and about 40 nm, and in another embodiment, the spacer material thickness is between about 43 nm and about 55 nm.
  • the spacer material deposition rate is between about 1 A per cycle and about 4 A per cycle in one embodiment, and is about 2 A per cycle in another embodiment.
  • a periphery photoresist layer 128 is optionally deposited in the peripheral region 104, while at least a portion of the array region 102 is left open.
  • the periphery photoresist layer 128 is blanket deposited over substantially the entire peripheral region 104.
  • the periphery photoresist layer 128 is patterned to define periphery features.
  • Example periphery features include landing pads, transistors, local interconnects, and the like.
  • the periphery photoresist layer 128 is deposited over the looped ends of the low temperature spacer material 126 and the tips 124" of the modified lines 124', thereby blocking the tips 124" of the modified lines 124'.
  • the embodiment illustrated in Figure 6D is particularly advantageous for forming damascene structures because this configuration prevents the looped ends over the low temperature spacer material 126 from being operational during subsequent etching processes.
  • the second masking step of Figures 6A through 6D is omitted, is conducted at an earlier stage, or is conducted at a later stage. This leaves the spacer material 126 exposed in the peripheral region 104.
  • the periphery photoresist layer 128 is deposited in the same deposition step in which the array photoresist layer 111 is deposited.
  • the mask used to pattern the array photoresist layer 111 is configured so as to leave a photoresist pattern or blanket layer in the peripheral region 104. This process results in photoresist being deposited directly on the second hard mask layer 110 in the peripheral region 104, without the intervening spacer material 126.
  • the low temperature spacer material 126 is then subjected to an anisotropic etch to remove spacer material from horizontal surfaces of the partially formed integrated circuit 100.
  • an anisotropic etch also known as a spacer etch, can be performed using, for example a HBr/CJ ⁇ -containing plasma.
  • pitch multiplication has been accomplished to form spacers 130.
  • the pitch of the spacers 130 is roughly half that of the photoresist lines 124 and trenches 122 (see Figures 3A and 3B) originally formed by photolithography.
  • spacers 130 having a pitch of about 100 nm or less (for a width of about 50 nm) can be formed. Because the spacers 130 are formed on the sidewatls of the modified lines 124', the spacers 130 generally follow the outline of the pattern of modified lines 124' in the first or array photoresist layer 111 , and thus typically form a closed loop as illustrated in Figure 7B. However, in general, the configuration of the spacers 130 depends on the absence or presence and pattern of the second photoresist layer 128 (see discussion of Figures 6A through 6D and variations, above).
  • the remaining exposed photoresist material is selectively etched from the partially formed integrated circuit 100.
  • the periphery features are now defined by any remaining low temperature spacer material 126 in the peripheral region 104.
  • the array photoresist layer 111 is used as a mandrel to form the spacers 130.
  • the photoresist material is selectively removed using an organic strip process.
  • Preferred etch chemistries include an oxygen-containing plasma etch, such as an etch using SO 2 .
  • the photoresist material is selectively etched from only the array region 102 of the integrated circuit 100.
  • the photoresist material is etched from both the array region 102 and the peripheral region 104, followed by a subsequent deposition of photoresist material in the peripheral region 104.
  • the peripheral photoresist layer is omitted, the hard mask layer 110 is exposed in the peripheral array region 104.
  • FIG. 9A and 9B illustrate the pattern of spacers 130 defined in the first hard mask layer 108 and the second hard mask layer 110.
  • the second hard mask layer 110 is optionally etched from the structure illustrated in Figures 9A and 9B. This pattern can then be transferred into the underlying substrate 106 by etching of the underlying substrate 106.
  • the structure can also be otherwise processed (such as by doping, oxidizing, nitridizing, or selectively depositing) through the pattern defined in the first hard mask layer 108 and/or the second hard mask layer 110.
  • the substrate 106 can include previously deposited layers, such as insulating layers for damascene metallization, or metal layers for conventional metallization.
  • Certain of the techniques disclosed herein advantageously enable the formation of a pitch doubled pattern of spacers without the use of additional layers to define the array features, such as a top carbon layer and an amorphous silicon layer.
  • the photosensitive or photoresist material itself can be used to define mandrels which are used in a subsequent pitch multiplication technique.
  • This advantageously eliminates the need to pattern additional masking layers to define mandrels.
  • Such techniques advantageously allow process steps associated with such additional masking layers to be eliminated, such as additional dry develop steps and hard mask etch steps.
  • such techniques also advantageously allow the periphery photoresist layer 128 to be defined using the same low temperature spacer material that is used to form the spacers in the array region.
  • Certain of the embodiments disclosed herein also advantageously allow a hard mask material — as compared to a more vulnerable photoresist material — to be used to block and define features in the peripheral region 104 without requiring the use of a separate hard mask layer.

Abstract

A method for fabricating a semiconductor device (100) comprises patterning a layer of photoresist material (111) to form a plurality of mandrels (124). The method further comprises depositing an oxide material (126) over the plurality of mandrels (124) by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material (126) from exposed horizontal surfaces. The method further comprises selectively etching photoresist material (111).

Description

SIMPLIFIED PITCH DOUBLING PROCESS FLOW
FIELD OF THE INVENTION
[0001] The present invention relates generally to integrated circuit fabrication, and more specifically to simplified processes for forming pitch doubled integrated circuit features.
BACKGROUND OF THE INVENTION
[0002] Integrated circuits are continuously being made smaller as demand for portability, computing power, memory capacity and energy efficiency in modern electronics grows. Therefore, the size of the integrated circuit constituent features, such as electrical devices and interconnect line widths, is also decreasing continuously. The trend of decreasing feature size is evident in memory circuits or devices such as dynamic random access memory ("DRAM"), flash memory, nonvolatile memory, static random access memory ("SRAM"), ferroelectric ("FE") memory, logic gate arrays and so forth.
[0003] . For example, DRAM typically comprises millions of identical circuit elements, known as memory cells. A typical memory cell consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one binary digit ("bit") of data. A bit can be written to a memory cell through the transistor and read by sensing charge on the reference electrode of the storage capacitor. By decreasing the sizes of these constituent electrical devices and the conducting lines that interconnect them, the sizes of the memory devices incorporating memory cells can likewise be decreased. In similar fashion, the storage capacities of these devices can be increased by fitting more memory cells into the memory devices.
[0004] As another example, flash memory (for example, electrically erasable programmable read only memory or "EEPROM") is a type of memory that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. The memory cells include a floating gate field effect transistor capable of holding a charge. The data in a memory cell is determined by the presence or absence of charge on the floating gate. The cells are usually grouped into sections called "erase blocks." The memory cells of a flash memory array are typically arranged into a "NOR" architecture (in which each memory cell is directly coupled to a bit line) or a "NAND" architecture (in which memory cells are coupled into "strings" of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).. The memory cells within an erase block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
[0005] As is evident from the examples provided here, memory devices typically include large patterns or arrays of electrical devices and conductors that are used to interconnect the electrical devices. The "pitch" of such a pattern is defined as the distance between an identical point in two neighboring features in the pattern. These features are typically defined by openings in, and are spaced apart from each other by, a material such as an insulator or conductor. Thus, pitch can be understood as the sum of the width of a feature and the width of the space separating that feature from a neighboring feature.
BRIEF SUMMARY OF THE INVENTION
[0006] In one embodiment of the present invention, a method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises using an atomic layer deposition technique to deposit an oxide material onto the plurality of mandrels. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises etching the photoresist material selectively with respect to the oxide material, thereby forming a plurality of oxide spacers. [0007] In another embodiment of the present invention, a method of forming a memory device comprises forming a plurality of mandrels over a substrate. The mandrels are separated by exposed portions of the substrate. The method further comprises depositing a spacer material over the mandrels and over the exposed portions of the substrate using an atomic layer deposition technique conducted at a temperature less than about 1000C. The method further comprises anisotropically etching the spacer material from (a) exposed horizontal surfaces of the plurality of mandrels and (b) the exposed portions of the substrate. Spacer material is left remaining on vertical sidewalls of the plurality of mandrels.
[0008] In another embodiment of the present invention, a method of forming an integrated circuit comprises forming a plurality of mandrels on a hard mask layer. The mandrels comprise a photosensitive material. The method further comprises depositing a spacer material using an atomic layer deposition technique. The spacer material covers the plurality of mandrels. The method further comprises anisotropically etching the spacer material from horizontal surfaces, thereby exposing photosensitive material. The method further comprises removing exposed photosensitive material after anisotropically etching the spacer material, thereby leaving a pattern of spacers on the hard mask layer. The method further comprises transferring the pattern of spacers to the hard mask layer. The method further comprises etching the pattern of spacers from the hard mask layer.
[0009] In another embodiment of the present invention, a method of integrated circuit fabrication comprises using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer. The mandrels comprise a photoresist material. The method further comprises forming a pattern of spacers around the mandrels. The pattern of spacers has a pitch that is smaller than a minimum resolvable pitch of the lithographic technique. The pattern of spacers is formed from an oxide material. The pattern of spacers is deposited using an atomic layer deposition technique at a temperature less than about 1000C.
[0010] In another embodiment of the present invention, a method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
[0011] In another embodiment of the present invention, a method of forming a memory device comprises forming a plurality of mandrels over a substrate in an array region of the memory device. The mandrels optionally comprise a photoresist material. The mandrels are separated by exposed portions the substrate. The method further comprises depositing a spacer material over the mandrels, over the exposed portions of the substrate, and over a peripheral region of the memory device. The method further comprises depositing a peripheral mask, over the spacer material in the peripheral region of the memory device. The method further comprises anisotropically etching the spacer material from exposed horizontal surfaces. Spacer material is left remaining (a) on vertical sidewalls of the mandrels in the array region, and (b) between the substrate and the peripheral mask in the peripheral region.
[0012] In another embodiment of the present invention, a method of forming an integrated circuit comprises forming a plurality of mandrels on a hard mask layer in an array region. The mandrels comprise a photoresist material. The method further comprises depositing an oxide material over the array region and over a peripheral region that surrounds the array region. The oxide material covers the plurality of mandrels. The method further comprises forming a pattern of photoresist material over the oxide material in the peripheral region. The method further comprises anisotropically etching the oxide material from horizontal surfaces in the array region. The method further comprises removing exposed photoresist material from the array region and the peripheral region after anisotropically etching the oxide material. [0013] In another embodiment of the present invention, a method of integrated circuit fabrication comprises using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer in an integrated circuit array region. The mandrels comprise a photoresist material. The method further comprises forming a pattern of spacers around the plurality of elongate mandrels. The pattern of spacers have a pitch that is smaller than a minimum resolvable pitch of the lithographic technique. The spacers are formed from an oxide material that is deposited at a temperature less than about 1000C.
[0014] In another embodiment of the present invention, a partially formed integrated circuit comprises a substrate. The partially formed integrated circuit further comprises a hard mask layer positioned over the substrate. The partially formed integrated circuit further comprises a plurality of spacer loops that are formed directly over the hard mask layer, and that are at least partially positioned in an array region of the partially formed integrated circuit. The partially formed integrated circuit further comprises a mask at least partially defined in a peripheral region of the partially formed integrated circuit, wherein the mask is also directly formed over the hard mask layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Exemplary embodiments of the integrated circuits and integrated circuit fabrication techniques disclosed herein are illustrated in the accompanying drawings, which are for illustrative purposes only, and which are not necessarily drawn to scale. The drawings comprise the following figures, in which like numerals indicate like parts.
[0016] Figure 1A is a schematic cross-sectional view of a substrate having a plurality of mask lines formed thereon.
[0017] Figure 1 B is a schematic cross-sectional view of the substrate of Figure 1A after performing an anisotropic etch process that transfers the mask pattern into a temporary layer.
[0018] Figure 1C is a schematic cross-sectional view of the substrate of Figure 1B after removing the mask lines and performing an isotropic "shrink" etch. [0019] Figure 1D is a schematic cross-sectional view of the substrate of Figure 1C after blanket depositing a spacer material over mandrels left in the temporary layer.
[0020] Figure 1E is a schematic cross-sectional view of the substrate of Figure 1D "after performing a directional spacer etch to leave pitch-multiplied features or spacers.
[0021] Figure 1 F is a schematic cross-sectional view of the substrate of Figure 1 E after removing the mandrels.
[0022] Figure 2A is a schematic cross-sectional view of an example partially formed integrated circuit.
[0023] Figure 2B is a schematic top view of the partially formed integrated circuit of Figure 2A.
[0024] Figure 3A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 2A after forming lines in an array region in a photoresist layer.
[0025] Figure 3B is a schematic top view of the partially formed integrated circuit of Figure 3A.
[0026] Figure 4A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 3A after performing a trim etch.
[0027] Figure 4B is a schematic top view of the partially formed integrated circuit of Figure 4A.
[0028] Figure 5A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 4A after blanket depositing a low temperature spacer material over photoresist mandrels.
[0029] Figure 5B is a schematic top view of the partially formed integrated circuit of Figure 5A.
[0030] Figure 6A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 5A after defining features in the peripheral region. [0031] Figure 6B is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer is blanket deposited over substantially the entire peripheral region.
[0032] Figure 6C is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer is patterned to define periphery features.
[0033] Figure 6D is a schematic top view of the partially formed integrated circuit of Figure 6A, wherein a periphery photoresist layer partially overlaps the low temperature spacer material.
[0034] Figure 7A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 6A after performing an anisotropic etch of the low temperature spacer material.
[0035] Figure 7B is a schematic top view of the partially formed integrated circuit of Figure 7A.
[0036] Figure 8A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 7A after removing exposed photoresist material.
[0037] Figure 8B is a schematic top view of the partially formed integrated circuit of Figure 8A.
[0038] Figure 9A is a schematic cross-sectional view of the example partially formed integrated circuit of Figure 8A after transferring the pattern of spacers into underlying hard mask layers.
[0039] Figure 9B is a schematic top view of the partially formed integrated circuit of Figure 9A.
DETAILED DESCRIPTION OF THE INVENTION
[0040] As the size of the electrical devices and the conductors that comprise a memory device are made smaller and smaller, ever greater demands are placed on the techniques used to form these features. For example, photolithography is commonly used to pattern device features, such as conductive lines, on a substrate. The concept of pitch can be used to describe the size of these features. Due to optical factors such as light or radiation wavelength, however, photolithography techniques have a minimum pitch below which features cannot be formed reliably. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
[0041] One technique proposed for extending the capabilities of photolithographic techniques beyond their minimum pitch is the "pitch doubling" technique. This technique is illustrated in Figures 1A-1 F, and is described in U.S. Patent 5,328,810 (issued 12 July 1994), the entire disclosure of which is incorporated herein by reference. With reference to Figure 1A, photolithography is first used to form a pattern of lines 10 in a photoresist layer overlying a layer of a temporary or expendable material 20 and a substrate 30. Common wavelengths which are used in performing the photolithography include, but are not limited to, 157 nm, 193 nm, 248 nm or 365 nm. Before performing subsequent processing steps, the lines 10 are optionally shrunk using an isotropic etch. As shown in Figure 1B, the pattern is then transferred by an etch step, such as an anisotropic etch step, to the layer of expendable material 20, thereby forming placeholders or mandrels 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in Figure 1C. A layer of spacer material 50 is subsequently deposited over the mandrels 40, as shown in Figure 1 D. Spacers 60 are then formed on the sides of the mandrels 40 by preferentially etching the spacer material from the horizontal surfaces in a directional spacer etch, as shown in Figure 1 E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in Figure 1 F. Thus, where a given pattern area formerly defined one feature and one space (each having a width F, for a pitch of 2F), the same pattern area now includes two features and two spaces, as defined by spacers 60 (each having a width \F, for a pitch of F). Consequently, the smallest feature size possible with a photolithographic technique is effectively decreased by using the pitch doubling technique.
[0042] While pitch is actually reduced using these techniques, this reduction in pitch is conventionally referred to as "pitch doubling", or more generally, "pitch multiplication". This is because these techniques allow the number of features in a given region of the substrate to be doubled, or more generally, multiplied. Thus, using the conventional terminology, "multiplication" of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein. By forming multiple layers of spacers upon each other, the definable feature size can be made even smaller. Thus, the terms "pitch multiplication" and "pitch doubling" refer to the process generally, regardless of the number of times the spacer formation process is employed.
[0043] Some proposed methods for forming patterns in the periphery and in the array of a memory device involve use of two separate carbon layers. For example, in one such method, the mandrels used to define spacer loops are formed in an upper carbon layer. After pitch doubling and periphery patterning processes are performed, the array pattern is transferred to a lower carbon layer. While this process does allow features of different sizes to be formed in the array and periphery regions, use of a low temperature oxide material to define the spacer loops allows mandrels to be formed from the existing photoresist layer. This advantageously allows the top carbon layer to be omitted, thereby simplifying production.
[0044] In accordance with the foregoing, simplified and improved techniques have been developed for forming pitch doubled features in a semiconductor or integrated circuit device.
[0045] In certain embodiments, the feature pattern to be transferred to a substrate has a pitch below the minimum pitch of the photolithographic technique used for processing the substrate. Additionally, certain embodiments can be used to form arrays of features, including logic or gate arrays and volatile and non-volatile memory devices such as DRAM, phase change memory ("PCM"), programmable conductor random access memory ("PCRAM"), read only memory ("ROM"), flash memory. In such devices, pitch multiplication is usable to form, for example, transistor gate electrodes and conductive lines in the array region of the devices. Optionally, conventional photolithography can be combined in a particular sequence with the aforementioned simplified pitch doubling technique to simultaneously process larger features useful for logic circuits, such as local interconnects and complementary metal oxide semiconductor ("CMOS") circuits, in the peripheral region of the devices. For example, the logic array can be a field programmable gate array ("FPGA") having a core array similar to a memory array and a periphery with supporting logic circuits. Exemplary masking steps in the course of fabricating a memory device are illustrated in the figures and are described herein.
[0046] Figures 2A and 2B illustrate schematic cross-sectional and top views, respectively, of an example partially fabricated integrated circuit 100, such as a memory device. Figure 2B illustrates that the integrated circuit 100 comprises a central array region 102 that is surrounded by a peripheral region 104. It will be appreciated that, after the integrated circuit 100 is fabricated, the array region 102 will typically be densely populated with conducting lines and electrical devices such as transistors and capacitors. Pitch multiplication can be used to form features in the array region 102, as discussed herein.
[0047] On the other hand, the peripheral region 104 optionally can include features more complicated and/or larger than those in the array region 102. Conventional photolithography, rather than pitch multiplication, is typically used to pattern these more complicated and/or larger features, examples of which include various types of logic circuitry. The geometric complexity of the logic circuits located in the peripheral region 104 makes using pitch multiplication difficult in this region of the integrated circuit 100. In contrast, the regular grid typical of array patterns is conducive to pitch multiplication. Additionally, some devices in the peripheral region 104 may require larger geometries due to electrical constraints, thereby making pitch multiplication less advantageous than conventional photolithography for such devices. In addition to possible differences in relative scale, the relative positions, and the number of peripheral regions 104 and array regions 102 in the integrated circuit 100 can vary in other embodiments. In embodiments wherein different processing techniques are separately used to form features in the array region 102 and the peripheral region 104, the peripheral region 104 can be masked during processing of the array region. [0048] Figure 2A illustrates that the partially formed integrated circuit 100 includes a substrate 106 having a first hard mask layer 108 formed thereover. In an example embodiment, the first hard mask layer 108 comprises a material such as silicon nitride, silicon oxide, or an organic material, such as an amorphous carbon material, a polymer material, or a spin on dielectric material. In a preferred embodiment, the first hard mask layer 108 comprises a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. In other modified embodiments, the first hard mask layer 108 is omitted.
[0049] An optional second hard mask layer 110 is formed over the first hard mask layer 108. The second hard mask layer 110 preferably comprises an inorganic material- Example materials for the second hard mask layer 110 include silicon nitride, polycrystalline silicon, or a dielectric antireflective coating ("DARC"), such as silicon-rich silicon oxynitride. Preferably, the material comprising the second hard mask layer 110 can be selectively etched with respect to subsequently- deposited spacer materials. Use of a DARC for the second hard mask layer 110 can be particularly advantageous for forming patterns having pitches near the resolution limits of a photolithographic technique. In particular, a DARC can enhance resolution by reducing light reflections, thus increasing the precision with which photolithography can define the edges of a pattern. The second hard mask layer 110 is omitted in embodiments wherein the first hard mask layer 108 can be etched selectively with respect to subsequently deposited spacer materials. In still other embodiments, the second hard mask layer 110 is replaced with an organic spin on antireflective coating ("ARC") positioned between the first hard mask layer 108 and the subsequently described overlying array photoresist layer.
[0050] An array photoresist layer 111 , also referred to herein as a mandrel layer, is formed over the second hard mask layer 110. The array photoresist layer 111 preferably comprises photosensitive material, such as a photoresist material that is compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems such as 13.7 nm wavelength systems, or electron beam lithographic systems. Examples of preferred photoresist materials include argon fluoride sensitive photoresist (that is, photoresist suitable for use with an argon fluoride light source) and krypton fluoride sensitive photoresist (that is, photoresist suitable for use with a krypton fluoride light source). Argon fluoride photoresists are preferably used with shorter wavelength photolithography systems, such as 193 nm wavelength systems. Krypton fluoride photoresists are preferably used with longer wavelength photolithography systems, such as 248 nm wavelength systems. In a modified embodiment, the array photoresist layer 111 comprises a photoresist material that can be patterned by nano-imprint lithography, such as by using a mold or a mechanical force to pattern the photoresist material.
[0051] In general, the materials for the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are chosen based on the chemistry and the process conditions for the various pattern forming and transfer steps disclosed herein. For instance, in an example embodiment, the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can each be selectively etched with respect to each other. As used herein, a material is considered "selectively etched" (or "preferentially etched") when the etch rate for that material is greater than that for a neighboring material. For example, in certain embodiments, a "selectively etchable" material has an etch rate that is at least about 2 times greater, at least about 10 times greater, at least about 20 times greater, or at least about 40 times greater than that for a neighboring material. In modified embodiments other layers are added if suitable other materials, chemistries and/or processes conditions are used.
[0052] The first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 can be formed using deposition processes such as spin-on coating, sputtering, chemical vapor deposition ("CVD"), or atomic layer deposition. For example, a low temperature CVD process (less than about 5500C, less than about 4500C, or even less than about 4000C) advantageously reduces chemical and/or physical disruption of an amorphous carbon layer, and thus is useful for deposition of materials over an existing amorphous carbon layer, such as the first hard mask layer 108. Additional information regarding the formation of amorphous carbon layers, including doped amorphous carbon layers, is provided in U.S. Patent 6,573,030 (issued 3 June 2003) and U.S. Patent Application Publication 2005/0042879 (published 24 February 2005). The entire disclosure of this patent and patent application publication is hereby incorporated by reference herein.
[0053] The thicknesses of the first hard mask layer 108, the second hard mask layer 110, and the array photoresist layer 111 are also chosen depending upon compatibility with the etch chemistries and process conditions disclosed herein. For example, when etching a material through a mask of another material, such as when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Thus, the upper layer is preferably sufficiently thick such that it is not completely worn away over the course of the pattern transfer. In an example embodiment, the second hard mask layer 110 is preferably between about 10 nm and about 40 nm thick, and is more preferably between about 15 nm and about 30 nm thick.
[0054] The thickness of the array photoresist layer 111 depends on the wavelength of light used to pattern the array photoresist layer 111. In an example embodiment wherein 248 nm light is used to perform photolithography, the array photoresist layer 111 is preferably between about 50 nm and about 300 nm thick, and is more preferably between about 200 nm and 250 nm thick. This height can vary depending upon the wavelength of light used to pattern the photoresist layer. Because lines are subsequently formed in the array photoresist layer 111, in certain embodiments the height of the array photoresist layer 111 is limited by the structural integrity and the aspect ratio of the lines to be formed, since tall spacer lines may collapse or otherwise deform.
[0055] As illustrated in Figures 3A and 3B, a pattern is defined in the array photoresist layer 111 that comprises trenches 122 delimited by lines 124. In some embodiments this pattern can be found anywhere on the substrate; defining the pattern in the array region merely represents a particular embodiment with particular advantages. The trenches 122 can be formed by, for example, photolithography with 248 nm or 193 nm light, in which the array photoresist layer 111 is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefinable material, which is photoresist in the illustrated embodiment, forms mask features such as the illustrated lines 124. In other embodiments, maskless lithography, or maskless photolithography can also be used to define the lines 124.
[0056] The pitch of the resulting lines 124 is equal to the sum of the width of a line 124 and the width of a neighboring trench 122. To reduce the dimensions of features formed using this pattern of lines 124 and trenches 122, the pitch can be at or near the limits of the photolithographic technique used to pattern the array photoresist layer 111. For example, for photolithography using 248 nm light, the pitch of the lines 124 is preferably between about 80 nm and about 150 nm, and is more preferably between about 90 nm and about 120 nm. Thus, in an example embodiment the pitch is the minimum pitch of the photolithographic technique and the subsequently-formed pitch multiplied spacer pattern advantageously has a pitch below the minimum pitch of the photolithographic technique. In alternative embodiments, because the margin of error for position and feature size typically increases as the limits of a photolithographic technique are approached, the lines 124 are formed having larger feature sizes, such as 200 nm, to reduce errors in the positions and sizes of the lines 124.
[0057] As illustrated in Figures 4A and 4B, the trenches 122 are preferably widened by etching the lines 124, to form modified trenches 122' and modified lines 124'. The lines 124 are preferably etched using a isotropic etch to "shrink" these features. Suitable etches include etches using an oxygen-containing plasma, such as a S02/O2/N2/Ar plasma, a C£2/O2/He plasma, or a HBr/O2/N2 plasma. The extent of the etch is preferably selected so that the width of the modified lines 124' is substantially equal to the desired spacing between subsequently-formed pitch doubled features. For example, in an example embodiment the width of the lines 124 is reduced from between about 80 nm and about 120 nm to between about 35 nm and about 70 nm, and in another embodiment the width is reduced to between about 40 nm and about 50 nm. Advantageously, the width-reducing etch allows the modified lines 124' to be narrower than would otherwise be possible using the photolithographic technique used to form the lines 124. Additionally, the etch can provide the modified lines 124' with smoothed edges, thus improving the uniformity of the modified lines 124'. While the critical dimensions of the modified lines 124' can be etched below the resolution limits of the photolithographic technique, this etch does not alter the pitch of the modified trenches 122' and the modified lines 124', since the distance between identical points in these features remains the same.
[0058] As illustrated in Figures 5A and 5B, a blanket layer of low temperature spacer material 126 is deposited over the modified lines 124'. In an example embodiment, the low temperature spacer material 126 comprises a layer of oxide material deposited using an atomic layer deposition ("ALD") technique. Generally, photoresist materials are not as tolerant of high temperatures as inorganic or carbon materials. Therefore, forming the spacers from a low temperature oxide material advantageously allows a separate mandrel layer deposition, pattern and transfer to be eliminated, with the patterned array photoresist layer 111 serving the same function. The low temperature spacer material is deposited at less than about 2000C in one embodiment, at less than about 100°C in another embodiment, at less than about 800C in another embodiment, and at less than about 75°C in another embodiment.
[0059] In an example embodiment, the low temperature spacer material 126 is deposited in an ALD process using SiaCϋβ, H2O and C5H5N precursors. In such embodiments the spacer material 126 is deposited to a thickness that is between about 20 nm and about 65 nm in one embodiment, between about 25 nm and about 60 nm in another embodiment, and between about 30 nm and about 55 nm in another embodiment. In one embodiment, the spacer material thickness is between about 30 nm and about 40 nm, and in another embodiment, the spacer material thickness is between about 43 nm and about 55 nm. The spacer material deposition rate is between about 1 A per cycle and about 4 A per cycle in one embodiment, and is about 2 A per cycle in another embodiment.
[0060] As illustrated in Figures 6A through 6D, a periphery photoresist layer 128 is optionally deposited in the peripheral region 104, while at least a portion of the array region 102 is left open. In a preferred embodiment, illustrated in Figure 6B, the periphery photoresist layer 128 is blanket deposited over substantially the entire peripheral region 104. In an alternative embodiment, illustrated in Figure 6C, the periphery photoresist layer 128 is patterned to define periphery features. Example periphery features include landing pads, transistors, local interconnects, and the like. In another alternative embodiment, illustrated in Figure 6D, the periphery photoresist layer 128 is deposited over the looped ends of the low temperature spacer material 126 and the tips 124" of the modified lines 124', thereby blocking the tips 124" of the modified lines 124'. The embodiment illustrated in Figure 6D is particularly advantageous for forming damascene structures because this configuration prevents the looped ends over the low temperature spacer material 126 from being operational during subsequent etching processes.
[0061] In yet another modified embodiment, the second masking step of Figures 6A through 6D is omitted, is conducted at an earlier stage, or is conducted at a later stage. This leaves the spacer material 126 exposed in the peripheral region 104. For example, in one arrangement, the periphery photoresist layer 128 is deposited in the same deposition step in which the array photoresist layer 111 is deposited. In such embodiments, the mask used to pattern the array photoresist layer 111 is configured so as to leave a photoresist pattern or blanket layer in the peripheral region 104. This process results in photoresist being deposited directly on the second hard mask layer 110 in the peripheral region 104, without the intervening spacer material 126.
[0062] As illustrated in Figures 7A and 7B, the low temperature spacer material 126 is then subjected to an anisotropic etch to remove spacer material from horizontal surfaces of the partially formed integrated circuit 100. Such an etch, also known as a spacer etch, can be performed using, for example a HBr/CJ^-containing plasma. Thus, pitch multiplication has been accomplished to form spacers 130. In the illustrated embodiment, the pitch of the spacers 130 is roughly half that of the photoresist lines 124 and trenches 122 (see Figures 3A and 3B) originally formed by photolithography. Where the photoresist lines 124 had a pitch of about 200 nm, spacers 130 having a pitch of about 100 nm or less (for a width of about 50 nm) can be formed. Because the spacers 130 are formed on the sidewatls of the modified lines 124', the spacers 130 generally follow the outline of the pattern of modified lines 124' in the first or array photoresist layer 111 , and thus typically form a closed loop as illustrated in Figure 7B. However, in general, the configuration of the spacers 130 depends on the absence or presence and pattern of the second photoresist layer 128 (see discussion of Figures 6A through 6D and variations, above).
[0063] As illustrated in Figures 8A and 8B, the remaining exposed photoresist material is selectively etched from the partially formed integrated circuit 100. This includes the first or array photoresist layer 111, as well as any second or periphery photoresist material 128. This results in the formation of freestanding spacers 130 separated by modified trenches 122'. The periphery features are now defined by any remaining low temperature spacer material 126 in the peripheral region 104. Thus, the array photoresist layer 111 is used as a mandrel to form the spacers 130. The photoresist material is selectively removed using an organic strip process. Preferred etch chemistries include an oxygen-containing plasma etch, such as an etch using SO2. In embodiments wherein the peripheral photoresist layer 128 is deposited directly on the second hard mask layer 110, the photoresist material is selectively etched from only the array region 102 of the integrated circuit 100. Alternatively, in such embodiments the photoresist material is etched from both the array region 102 and the peripheral region 104, followed by a subsequent deposition of photoresist material in the peripheral region 104. In embodiments wherein the peripheral photoresist layer is omitted, the hard mask layer 110 is exposed in the peripheral array region 104.
[0064] After the freestanding spacers 130 are formed, subsequent processing steps can be conducted, such as a dry develop step and an in situ etch step. The subsequent processing steps can be used to transfer the pattern of spacers 130 and periphery features to the underlying first hard mask layer 108 and/or the second hard mask layer 110, as illustrated in Figures 9A and 9B. Specifically, Figures 9A and 9B illustrate the pattern of spacers 130 defined in the first hard mask layer 108 and the second hard mask layer 110. The second hard mask layer 110 is optionally etched from the structure illustrated in Figures 9A and 9B. This pattern can then be transferred into the underlying substrate 106 by etching of the underlying substrate 106. The structure can also be otherwise processed (such as by doping, oxidizing, nitridizing, or selectively depositing) through the pattern defined in the first hard mask layer 108 and/or the second hard mask layer 110. As noted herein, the substrate 106 can include previously deposited layers, such as insulating layers for damascene metallization, or metal layers for conventional metallization.
[0065] Certain of the techniques disclosed herein advantageously enable the formation of a pitch doubled pattern of spacers without the use of additional layers to define the array features, such as a top carbon layer and an amorphous silicon layer. Specifically, by forming low temperature oxide spacers directly on the array photoresist layer 111 as disclosed herein, the photosensitive or photoresist material itself can be used to define mandrels which are used in a subsequent pitch multiplication technique. This advantageously eliminates the need to pattern additional masking layers to define mandrels. Such techniques advantageously allow process steps associated with such additional masking layers to be eliminated, such as additional dry develop steps and hard mask etch steps. Furthermore, such techniques also advantageously allow the periphery photoresist layer 128 to be defined using the same low temperature spacer material that is used to form the spacers in the array region. Certain of the embodiments disclosed herein also advantageously allow a hard mask material — as compared to a more vulnerable photoresist material — to be used to block and define features in the peripheral region 104 without requiring the use of a separate hard mask layer.
SCOPE OF THE INVENTION
[0066] While the foregoing detailed description discloses several embodiments of the present invention, it should be understood that this disclosure is illustrative only and is not limiting of the present invention. It should be appreciated that the specific configurations and operations disclosed can differ from those described above, and that the methods described herein can be used in contexts other than integrated circuit fabrication.

Claims

WE CLAIM:
1. A method for fabricating a semiconductor device, the method comprising: patterning a layer of photoresist material to form a plurality of mandrels; using an atomic layer deposition technique to deposit an oxide material onto the plurality of mandrels; anisotropically etching the oxide material from exposed horizontal surfaces; and etching the photoresist material selectively with respect to the oxide material, thereby forming a plurality of oxide spacers.
2. The method of Claim 1 , wherein the oxide material is deposited using a precursor selected from the group consisting of Si2Cf6, H2O and C5H5N.
3. The method of Claim 1, wherein: the plurality of mandrels are formed in a device array region; and the oxide material is also deposited over a device peripheral region.
4. The method of Claim 3, further comprising forming a pattern of photoresist material over the oxide material in the device peripheral region.
5. The method of Claim 4, wherein etching the photoresist material selectively further comprises etching photoresist material from the device peripheral region selectively.
6. The method of Claim 1 , further comprising isotropically etching the plurality of mandrels to form a plurality of modified mandrels before depositing the oxide material.
7. The method of Claim 6, wherein isotropically etching the plurality of mandrels comprises using an oxygen-containing plasma selected from the group consisting of a SO2ZO2ZN2VAr plasma, a Cf2ZO2ZHe plasma, and a HBrZO2ZN2 plasma.
8. The method of Claim 6, wherein the modified mandrels have a width between about 35 nm and about 70 nm.
9. The method of Claim 1 , wherein patterning the layer of photoresist comprises using nano-imprint lithography.
10. The method of Claim 1, wherein anisotropically etching the oxide material comprises using a HBr/C^-containing plasma.
11. The method of Claim 1 , wherein the oxide material is deposited at a temperature less than about 1000C.
12. The method of Claim 1 , wherein the oxide material is deposited at a temperature less than about 800C.
13. The method of Claim 1 , wherein the layer of photoresist material is patterned over a hard mask layer.
14. The method of Claim 1 , wherein the layer of photoresist material is patterned over a silicon oxynitride layer that is positioned over a carbon layer.
15. The method of Claim 1 , wherein the plurality of mandrels have a height between about 50- nm and about 300 nm.
16. The method of Claim 1 , wherein the layer of photoresist material comprises a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.
17. A method of forming a memory device, the method comprising: forming a plurality of mandrels over a substrate, the mandrels separated by exposed portions of the substrate; depositing a spacer material over the mandrels and over the exposed portions of the substrate using an atomic layer deposition technique conducted at a temperature less than about 100°C; and anisotropically etching the spacer material from (a) exposed horizontal surfaces of the plurality of mandrels and (b) the exposed portions of the substrate, thereby leaving spacer material remaining on vertical sidewalls of the plurality of mandrels.
18. The method of Claim 17, wherein the substrate includes a hard mask directly under the spacer material.
19. The method of Claim 17, further comprising removing the plurality of mandrels, thereby leaving a pattern of spacers positioned over the substrate.
20. The method of Claim 19, wherein the spacers comprising the pattern of spacers have a width of about 50 nm or less.
21. The method of Claim 19, wherein the spacer material is deposited to a thickness x over the mandrels, and wherein the spacers comprising the pattern of spacers comprising the pattern of spacers have a width x.
22. The method of Claim 19, further comprising transferring the pattern of spacers into an amorphous carbon hard mask.
23. A method of forming an integrated circuit, the method comprising: forming a plurality of mandrels on a hard mask layer, wherein the mandrels comprise a photosensitive material; depositing a spacer material using an atomic layer deposition technique, wherein the spacer material covers the plurality of mandrels; anisotropically etching the spacer material from horizontal surfaces, thereby exposing photosensitive material; removing exposed photosensitive material after anisotropically etching the spacer material, thereby leaving a pattern of spacers on the hard mask layer; transferring the pattern of spacers to the hard mask layer; and etching the pattern of spacers from the hard mask layer.
24. The method of Claim 23, wherein the hard mask layer comprises carbon.
25. The method of Claim 23, wherein: the mandrels are formed in an array region of the integrated circuit; and the spacer material is deposited over (a) the array region of the integrated circuit and (b) a peripheral region of the integrated circuit, the peripheral region surrounding the array region.
26. The method of Claim 25, further comprising: forming a pattern of photosensitive material over the spacer material in the peripheral region before anisotropically etching; and removing exposed photosensitive material from the peripheral region after anisotropically etching the spacer material.
27. The method of Claim 23, wherein the hard mask layer comprises carbon and a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.
28. The method of Claim 23, wherein the hard mask layer is positioned over a semiconductor substrate.
29. The method of Claim 23, wherein the spacer material is deposited at a temperature less than about 1000C.
30. The method of Claim 23, further comprising isotropically etching the plurality of mandrels before depositing the spacer material.
31. A method of integrated circuit fabrication, the method comprising: using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer, wherein the mandrels comprise a photoresist material; and forming a pattern of spacers around the mandrels, wherein: the pattern of spacers has a pitch that is smaller than a minimum resolvable pitch of the lithographic technique, the pattern of spacers is formed from an oxide material, and the pattern of spacers is deposited using an atomic layer deposition technique at a temperature less than about 1000C.
32. The method of Claim 31 , wherein the pattern of spacers is deposited at a temperature less than about 80°C.
33. The method of Claim 31 , wherein the pattern of spacers is deposited at a temperature less than about 300C.
34. The method of Claim 31 , further comprising transferring the pattern of spacers into the hard mask layer.
35. The method of Claim 34, wherein transferring the pattern of spacers into the hard mask layer further comprises exposing a portion of a substrate that underlies the hard mask layer.
36. The method of Claim 31 , wherein the pattern of spacers comprises a pattern of spacer loops formed around the mandrels.
37. The method of Claim 31, wherein the hard mask layer comprises a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.
38. The method of Claim 31 , wherein the hard mask layer comprises a dielectric antireflective coating.
39. The method of Claim 31 , wherein the hard mask layer comprises an organic antireflective coating.
40. The method of Claim 31 , wherein the hard mask layer is formed over a semiconductor substrate.
41. The method of Claim 31 , wherein the hard mask layer is formed over a semiconductor substrate and an amorphous carbon layer.
42. The method of Claim 31 , wherein the mandrels have a height between about 50 nm and about 300 nm.
43. The method of Claim 31 , wherein the mandrels have a height between about 200 nm and about 250 nm.
44. The method of Claim 31 , wherein the mandrels comprise a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.
45. The method of Claim 31 , wherein the pattern of spacers has a pitch between about 70 nm and about 120 nm.
46. The method of Claim 31, wherein the patterns has a pitch between about 80 nm and about 100 nm.
PCT/US2007/011525 2006-04-07 2007-05-14 Simplified pitch doubling process flow WO2007117718A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07794840.4A EP2011141B1 (en) 2006-04-07 2007-05-14 Simplified pitch doubling process flow
JP2009504360A JP5229588B6 (en) 2007-05-14 Simplified pitch doubling process
KR1020087027277A KR101368544B1 (en) 2007-05-14 2007-05-14 Simplified pitch doubling process flow
CN2007800125255A CN101416278B (en) 2006-04-07 2007-05-14 Simplified technological process for doubling range interval

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/400,603 2006-04-07
US11/400,603 US7902074B2 (en) 2006-04-07 2006-04-07 Simplified pitch doubling process flow

Publications (2)

Publication Number Publication Date
WO2007117718A2 true WO2007117718A2 (en) 2007-10-18
WO2007117718A3 WO2007117718A3 (en) 2007-11-29

Family

ID=38541931

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/011525 WO2007117718A2 (en) 2006-04-07 2007-05-14 Simplified pitch doubling process flow

Country Status (4)

Country Link
US (5) US7902074B2 (en)
EP (1) EP2011141B1 (en)
CN (1) CN101416278B (en)
WO (1) WO2007117718A2 (en)

Cited By (279)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009246332A (en) * 2008-03-28 2009-10-22 Samsung Electronics Co Ltd Method of forming fine pattern of semiconductor device
JP2009267111A (en) * 2008-04-25 2009-11-12 Tokyo Electron Ltd Manufacturing method for semiconductor device, manufacturing apparatus, computer program, and computer-readable memory medium
JP2009302143A (en) * 2008-06-10 2009-12-24 Toshiba Corp Manufacturing method of semiconductor device
JP2010245518A (en) * 2009-04-01 2010-10-28 Asm Japan Kk Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature
JP2011040656A (en) * 2009-08-17 2011-02-24 Nippon Telegr & Teleph Corp <Ntt> Method of forming microstructure
JP2011238919A (en) * 2010-05-06 2011-11-24 Asml Netherlands Bv Production of alignment mark
US8357618B2 (en) 2007-10-26 2013-01-22 Applied Materials, Inc. Frequency doubling using a photo-resist template mask
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10249577B2 (en) 2016-05-17 2019-04-02 Asm Ip Holding B.V. Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US10262859B2 (en) 2016-03-24 2019-04-16 Asm Ip Holding B.V. Process for forming a film on a substrate using multi-port injection assemblies
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10283353B2 (en) 2017-03-29 2019-05-07 Asm Ip Holding B.V. Method of reforming insulating film deposited on substrate with recess pattern
US10312055B2 (en) 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
US10312129B2 (en) 2015-09-29 2019-06-04 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US10340125B2 (en) 2013-03-08 2019-07-02 Asm Ip Holding B.V. Pulsed remote plasma method and system
US10340135B2 (en) 2016-11-28 2019-07-02 Asm Ip Holding B.V. Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US10361201B2 (en) 2013-09-27 2019-07-23 Asm Ip Holding B.V. Semiconductor structure and device formed using selective epitaxial process
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US10366864B2 (en) 2013-03-08 2019-07-30 Asm Ip Holding B.V. Method and system for in-situ formation of intermediate reactive species
US10364493B2 (en) 2016-08-25 2019-07-30 Asm Ip Holding B.V. Exhaust apparatus and substrate processing apparatus having an exhaust line with a first ring having at least one hole on a lateral side thereof placed in the exhaust line
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film
US10381226B2 (en) 2016-07-27 2019-08-13 Asm Ip Holding B.V. Method of processing substrate
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
US10435790B2 (en) 2016-11-01 2019-10-08 Asm Ip Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
US10438965B2 (en) 2014-12-22 2019-10-08 Asm Ip Holding B.V. Semiconductor device and manufacturing method thereof
US10446393B2 (en) 2017-05-08 2019-10-15 Asm Ip Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US10480072B2 (en) 2009-04-06 2019-11-19 Asm Ip Holding B.V. Semiconductor processing reactor and components thereof
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10504742B2 (en) 2017-05-31 2019-12-10 Asm Ip Holding B.V. Method of atomic layer etching using hydrogen plasma
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
US10529542B2 (en) 2015-03-11 2020-01-07 Asm Ip Holdings B.V. Cross-flow reactor and method
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10535516B2 (en) 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
US10541173B2 (en) 2016-07-08 2020-01-21 Asm Ip Holding B.V. Selective deposition method to form air gaps
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10559458B1 (en) 2018-11-26 2020-02-11 Asm Ip Holding B.V. Method of forming oxynitride film
US10566223B2 (en) 2012-08-28 2020-02-18 Asm Ip Holdings B.V. Systems and methods for dynamic semiconductor process scheduling
US10561975B2 (en) 2014-10-07 2020-02-18 Asm Ip Holdings B.V. Variable conductance gas distribution apparatus and method
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10600673B2 (en) 2015-07-07 2020-03-24 Asm Ip Holding B.V. Magnetic susceptor to baseplate seal
US10604847B2 (en) 2014-03-18 2020-03-31 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
US10605530B2 (en) 2017-07-26 2020-03-31 Asm Ip Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
US10607895B2 (en) 2017-09-18 2020-03-31 Asm Ip Holdings B.V. Method for forming a semiconductor device structure comprising a gate fill metal
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10622375B2 (en) 2016-11-07 2020-04-14 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US10643904B2 (en) 2016-11-01 2020-05-05 Asm Ip Holdings B.V. Methods for forming a semiconductor device and related semiconductor device structures
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10658181B2 (en) 2018-02-20 2020-05-19 Asm Ip Holding B.V. Method of spacer-defined direct patterning in semiconductor fabrication
US10655221B2 (en) 2017-02-09 2020-05-19 Asm Ip Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
US10665452B2 (en) 2016-05-02 2020-05-26 Asm Ip Holdings B.V. Source/drain performance through conformal solid state doping
US10683571B2 (en) 2014-02-25 2020-06-16 Asm Ip Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
US10685834B2 (en) 2017-07-05 2020-06-16 Asm Ip Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US10707106B2 (en) 2011-06-06 2020-07-07 Asm Ip Holding B.V. High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
US10714385B2 (en) 2016-07-19 2020-07-14 Asm Ip Holding B.V. Selective deposition of tungsten
US10714335B2 (en) 2017-04-25 2020-07-14 Asm Ip Holding B.V. Method of depositing thin film and method of manufacturing semiconductor device
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10731249B2 (en) 2018-02-15 2020-08-04 Asm Ip Holding B.V. Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
US10734497B2 (en) 2017-07-18 2020-08-04 Asm Ip Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
US10734244B2 (en) 2017-11-16 2020-08-04 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by the same
US10741385B2 (en) 2016-07-28 2020-08-11 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10767789B2 (en) 2018-07-16 2020-09-08 Asm Ip Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
US10787741B2 (en) 2014-08-21 2020-09-29 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
US10804098B2 (en) 2009-08-14 2020-10-13 Asm Ip Holding B.V. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US10811256B2 (en) 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
USD900036S1 (en) 2017-08-24 2020-10-27 Asm Ip Holding B.V. Heater electrical connector and adapter
US10832903B2 (en) 2011-10-28 2020-11-10 Asm Ip Holding B.V. Process feed management for semiconductor substrate processing
US10829852B2 (en) 2018-08-16 2020-11-10 Asm Ip Holding B.V. Gas distribution device for a wafer processing apparatus
US10847365B2 (en) 2018-10-11 2020-11-24 Asm Ip Holding B.V. Method of forming conformal silicon carbide film by cyclic CVD
US10847371B2 (en) 2018-03-27 2020-11-24 Asm Ip Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US10844484B2 (en) 2017-09-22 2020-11-24 Asm Ip Holding B.V. Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10854498B2 (en) 2011-07-15 2020-12-01 Asm Ip Holding B.V. Wafer-supporting device and method for producing same
USD903477S1 (en) 2018-01-24 2020-12-01 Asm Ip Holdings B.V. Metal clamp
US10851456B2 (en) 2016-04-21 2020-12-01 Asm Ip Holding B.V. Deposition of metal borides
US10858737B2 (en) 2014-07-28 2020-12-08 Asm Ip Holding B.V. Showerhead assembly and components thereof
US10867786B2 (en) 2018-03-30 2020-12-15 Asm Ip Holding B.V. Substrate processing method
US10865475B2 (en) 2016-04-21 2020-12-15 Asm Ip Holding B.V. Deposition of metal borides and silicides
US10867788B2 (en) 2016-12-28 2020-12-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
US10883175B2 (en) 2018-08-09 2021-01-05 Asm Ip Holding B.V. Vertical furnace for processing substrates and a liner for use therein
US10886123B2 (en) 2017-06-02 2021-01-05 Asm Ip Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
US10892156B2 (en) 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10910262B2 (en) 2017-11-16 2021-02-02 Asm Ip Holding B.V. Method of selectively depositing a capping layer structure on a semiconductor device structure
US10914004B2 (en) 2018-06-29 2021-02-09 Asm Ip Holding B.V. Thin-film deposition method and manufacturing method of semiconductor device
US10923344B2 (en) 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
US10928731B2 (en) 2017-09-21 2021-02-23 Asm Ip Holding B.V. Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same
US10934619B2 (en) 2016-11-15 2021-03-02 Asm Ip Holding B.V. Gas supply unit and substrate processing apparatus including the gas supply unit
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11001925B2 (en) 2016-12-19 2021-05-11 Asm Ip Holding B.V. Substrate processing apparatus
US11018047B2 (en) 2018-01-25 2021-05-25 Asm Ip Holding B.V. Hybrid lift pin
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US11056567B2 (en) 2018-05-11 2021-07-06 Asm Ip Holding B.V. Method of forming a doped metal carbide film on a substrate and related semiconductor device structures
US11069510B2 (en) 2017-08-30 2021-07-20 Asm Ip Holding B.V. Substrate processing apparatus
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
US11114294B2 (en) 2019-03-08 2021-09-07 Asm Ip Holding B.V. Structure including SiOC layer and method of forming same
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
US11127617B2 (en) 2017-11-27 2021-09-21 Asm Ip Holding B.V. Storage device for storing wafer cassettes for use with a batch furnace
US11127589B2 (en) 2019-02-01 2021-09-21 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
US11171025B2 (en) 2019-01-22 2021-11-09 Asm Ip Holding B.V. Substrate processing device
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
US11205585B2 (en) 2016-07-28 2021-12-21 Asm Ip Holding B.V. Substrate processing apparatus and method of operating the same
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
US11222772B2 (en) 2016-12-14 2022-01-11 Asm Ip Holding B.V. Substrate processing apparatus
US11227789B2 (en) 2019-02-20 2022-01-18 Asm Ip Holding B.V. Method and apparatus for filling a recess formed within a substrate surface
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11233133B2 (en) 2015-10-21 2022-01-25 Asm Ip Holding B.V. NbMC layers
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US11251040B2 (en) 2019-02-20 2022-02-15 Asm Ip Holding B.V. Cyclical deposition method including treatment step and apparatus for same
US11251068B2 (en) 2018-10-19 2022-02-15 Asm Ip Holding B.V. Substrate processing apparatus and substrate processing method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11274369B2 (en) 2018-09-11 2022-03-15 Asm Ip Holding B.V. Thin film deposition method
US11282698B2 (en) 2019-07-19 2022-03-22 Asm Ip Holding B.V. Method of forming topology-controlled amorphous carbon polymer film
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
US11289326B2 (en) 2019-05-07 2022-03-29 Asm Ip Holding B.V. Method for reforming amorphous carbon polymer film
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
US11315794B2 (en) 2019-10-21 2022-04-26 Asm Ip Holding B.V. Apparatus and methods for selectively etching films
US11339476B2 (en) 2019-10-08 2022-05-24 Asm Ip Holding B.V. Substrate processing device having connection plates, substrate processing method
US11342216B2 (en) 2019-02-20 2022-05-24 Asm Ip Holding B.V. Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
US11345999B2 (en) 2019-06-06 2022-05-31 Asm Ip Holding B.V. Method of using a gas-phase reactor system including analyzing exhausted gas
US11355338B2 (en) 2019-05-10 2022-06-07 Asm Ip Holding B.V. Method of depositing material onto a surface and structure formed according to the method
US11361990B2 (en) 2018-05-28 2022-06-14 Asm Ip Holding B.V. Substrate processing method and device manufactured by using the same
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11378337B2 (en) 2019-03-28 2022-07-05 Asm Ip Holding B.V. Door opener and substrate processing apparatus provided therewith
US11390946B2 (en) 2019-01-17 2022-07-19 Asm Ip Holding B.V. Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
US11393690B2 (en) 2018-01-19 2022-07-19 Asm Ip Holding B.V. Deposition method
US11390945B2 (en) 2019-07-03 2022-07-19 Asm Ip Holding B.V. Temperature control assembly for substrate processing apparatus and method of using same
US11401605B2 (en) 2019-11-26 2022-08-02 Asm Ip Holding B.V. Substrate processing apparatus
US11414760B2 (en) 2018-10-08 2022-08-16 Asm Ip Holding B.V. Substrate support unit, thin film deposition apparatus including the same, and substrate processing apparatus including the same
US11424119B2 (en) 2019-03-08 2022-08-23 Asm Ip Holding B.V. Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11430640B2 (en) 2019-07-30 2022-08-30 Asm Ip Holding B.V. Substrate processing apparatus
US11437241B2 (en) 2020-04-08 2022-09-06 Asm Ip Holding B.V. Apparatus and methods for selectively etching silicon oxide films
US11443926B2 (en) 2019-07-30 2022-09-13 Asm Ip Holding B.V. Substrate processing apparatus
US11447864B2 (en) 2019-04-19 2022-09-20 Asm Ip Holding B.V. Layer forming method and apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
US11469098B2 (en) 2018-05-08 2022-10-11 Asm Ip Holding B.V. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
US11476109B2 (en) 2019-06-11 2022-10-18 Asm Ip Holding B.V. Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11482412B2 (en) 2018-01-19 2022-10-25 Asm Ip Holding B.V. Method for depositing a gap-fill layer by plasma-assisted deposition
US11482533B2 (en) 2019-02-20 2022-10-25 Asm Ip Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
US11482418B2 (en) 2018-02-20 2022-10-25 Asm Ip Holding B.V. Substrate processing method and apparatus
US11488819B2 (en) 2018-12-04 2022-11-01 Asm Ip Holding B.V. Method of cleaning substrate processing apparatus
US11488854B2 (en) 2020-03-11 2022-11-01 Asm Ip Holding B.V. Substrate handling device with adjustable joints
US11495459B2 (en) 2019-09-04 2022-11-08 Asm Ip Holding B.V. Methods for selective deposition using a sacrificial capping layer
US11492703B2 (en) 2018-06-27 2022-11-08 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11499222B2 (en) 2018-06-27 2022-11-15 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
US11499226B2 (en) 2018-11-02 2022-11-15 Asm Ip Holding B.V. Substrate supporting unit and a substrate processing device including the same
US11515187B2 (en) 2020-05-01 2022-11-29 Asm Ip Holding B.V. Fast FOUP swapping with a FOUP handler
US11515188B2 (en) 2019-05-16 2022-11-29 Asm Ip Holding B.V. Wafer boat handling device, vertical batch furnace and method
US11521851B2 (en) 2020-02-03 2022-12-06 Asm Ip Holding B.V. Method of forming structures including a vanadium or indium layer
US11527400B2 (en) 2019-08-23 2022-12-13 Asm Ip Holding B.V. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US11530483B2 (en) 2018-06-21 2022-12-20 Asm Ip Holding B.V. Substrate processing system
US11530876B2 (en) 2020-04-24 2022-12-20 Asm Ip Holding B.V. Vertical batch furnace assembly comprising a cooling gas supply
US11551925B2 (en) 2019-04-01 2023-01-10 Asm Ip Holding B.V. Method for manufacturing a semiconductor device
US11551912B2 (en) 2020-01-20 2023-01-10 Asm Ip Holding B.V. Method of forming thin film and method of modifying surface of thin film
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11605528B2 (en) 2019-07-09 2023-03-14 Asm Ip Holding B.V. Plasma device using coaxial waveguide, and substrate treatment method
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
US11610774B2 (en) 2019-10-02 2023-03-21 Asm Ip Holding B.V. Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process
US11610775B2 (en) 2016-07-28 2023-03-21 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11615970B2 (en) 2019-07-17 2023-03-28 Asm Ip Holding B.V. Radical assist ignition plasma system and method
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
US11626308B2 (en) 2020-05-13 2023-04-11 Asm Ip Holding B.V. Laser alignment fixture for a reactor system
US11626316B2 (en) 2019-11-20 2023-04-11 Asm Ip Holding B.V. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11629407B2 (en) 2019-02-22 2023-04-18 Asm Ip Holding B.V. Substrate processing apparatus and method for processing substrates
US11637011B2 (en) 2019-10-16 2023-04-25 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
US11639811B2 (en) 2017-11-27 2023-05-02 Asm Ip Holding B.V. Apparatus including a clean mini environment
US11639548B2 (en) 2019-08-21 2023-05-02 Asm Ip Holding B.V. Film-forming material mixed-gas forming device and film forming device
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
US11646184B2 (en) 2019-11-29 2023-05-09 Asm Ip Holding B.V. Substrate processing apparatus
US11644758B2 (en) 2020-07-17 2023-05-09 Asm Ip Holding B.V. Structures and methods for use in photolithography
US11646204B2 (en) 2020-06-24 2023-05-09 Asm Ip Holding B.V. Method for forming a layer provided with silicon
US11658035B2 (en) 2020-06-30 2023-05-23 Asm Ip Holding B.V. Substrate processing method
US11658029B2 (en) 2018-12-14 2023-05-23 Asm Ip Holding B.V. Method of forming a device structure using selective deposition of gallium nitride and system for same
US11664245B2 (en) 2019-07-16 2023-05-30 Asm Ip Holding B.V. Substrate processing device
US11664199B2 (en) 2018-10-19 2023-05-30 Asm Ip Holding B.V. Substrate processing apparatus and substrate processing method
US11664267B2 (en) 2019-07-10 2023-05-30 Asm Ip Holding B.V. Substrate support assembly and substrate processing device including the same
US11674220B2 (en) 2020-07-20 2023-06-13 Asm Ip Holding B.V. Method for depositing molybdenum layers using an underlayer
US11680839B2 (en) 2019-08-05 2023-06-20 Asm Ip Holding B.V. Liquid level sensor for a chemical source vessel
US11685991B2 (en) 2018-02-14 2023-06-27 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate
US11688603B2 (en) 2019-07-17 2023-06-27 Asm Ip Holding B.V. Methods of forming silicon germanium structures
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
US11705333B2 (en) 2020-05-21 2023-07-18 Asm Ip Holding B.V. Structures including multiple carbon layers and methods of forming and using same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11725277B2 (en) 2011-07-20 2023-08-15 Asm Ip Holding B.V. Pressure transmitter for a semiconductor processing environment
US11725280B2 (en) 2020-08-26 2023-08-15 Asm Ip Holding B.V. Method for forming metal silicon oxide and metal silicon oxynitride layers
US11735422B2 (en) 2019-10-10 2023-08-22 Asm Ip Holding B.V. Method of forming a photoresist underlayer and structure including same
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11767589B2 (en) 2020-05-29 2023-09-26 Asm Ip Holding B.V. Substrate processing device
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781221B2 (en) 2019-05-07 2023-10-10 Asm Ip Holding B.V. Chemical source vessel with dip tube
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
US11804364B2 (en) 2020-05-19 2023-10-31 Asm Ip Holding B.V. Substrate processing apparatus
US11814747B2 (en) 2019-04-24 2023-11-14 Asm Ip Holding B.V. Gas-phase reactor system-with a reaction chamber, a solid precursor source vessel, a gas distribution system, and a flange assembly
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
US11823876B2 (en) 2019-09-05 2023-11-21 Asm Ip Holding B.V. Substrate processing apparatus
US11823866B2 (en) 2020-04-02 2023-11-21 Asm Ip Holding B.V. Thin film forming method
US11827981B2 (en) 2020-10-14 2023-11-28 Asm Ip Holding B.V. Method of depositing material on stepped structure
US11830738B2 (en) 2020-04-03 2023-11-28 Asm Ip Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11828707B2 (en) 2020-02-04 2023-11-28 Asm Ip Holding B.V. Method and apparatus for transmittance measurements of large articles
US11840761B2 (en) 2019-12-04 2023-12-12 Asm Ip Holding B.V. Substrate processing apparatus
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
US11873557B2 (en) 2020-10-22 2024-01-16 Asm Ip Holding B.V. Method of depositing vanadium metal
US11885023B2 (en) 2018-10-01 2024-01-30 Asm Ip Holding B.V. Substrate retaining apparatus, system including the apparatus, and method of using same
US11885013B2 (en) 2019-12-17 2024-01-30 Asm Ip Holding B.V. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
US11887857B2 (en) 2020-04-24 2024-01-30 Asm Ip Holding B.V. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
US11885020B2 (en) 2020-12-22 2024-01-30 Asm Ip Holding B.V. Transition metal deposition method
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
US11891696B2 (en) 2020-11-30 2024-02-06 Asm Ip Holding B.V. Injector configured for arrangement within a reaction chamber of a substrate processing apparatus
US11901179B2 (en) 2020-10-28 2024-02-13 Asm Ip Holding B.V. Method and device for depositing silicon onto substrates
US11898243B2 (en) 2020-04-24 2024-02-13 Asm Ip Holding B.V. Method of forming vanadium nitride-containing layer
US11915929B2 (en) 2019-11-26 2024-02-27 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
US11923181B2 (en) 2019-11-29 2024-03-05 Asm Ip Holding B.V. Substrate processing apparatus for minimizing the effect of a filling gas during substrate processing

Families Citing this family (161)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
WO2008022097A2 (en) * 2006-08-15 2008-02-21 Api Nanofabrication And Research Corp. Methods for forming patterned structures
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US7807578B2 (en) * 2007-06-01 2010-10-05 Applied Materials, Inc. Frequency doubling using spacer mask
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8980756B2 (en) 2007-07-30 2015-03-17 Micron Technology, Inc. Methods for device fabrication using pitch reduction
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US20090035902A1 (en) * 2007-07-31 2009-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated method of fabricating a memory device with reduced pitch
KR101095772B1 (en) * 2007-10-17 2011-12-21 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7846812B2 (en) * 2007-12-18 2010-12-07 Micron Technology, Inc. Methods of forming trench isolation and methods of forming floating gate transistors
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8304174B2 (en) * 2007-12-28 2012-11-06 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US7856613B1 (en) 2008-01-30 2010-12-21 Cadence Design Systems, Inc. Method for self-aligned doubled patterning lithography
JP2009200080A (en) * 2008-02-19 2009-09-03 Tokyo Electron Ltd Plasma etching method, plasma etching apparatus, control program and computer readable storage medium
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
JP2009295785A (en) * 2008-06-05 2009-12-17 Toshiba Corp Method of manufacturing semiconductor device
KR101203201B1 (en) * 2008-06-13 2012-11-21 도쿄엘렉트론가부시키가이샤 Semiconductor device manufacturing method
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8680650B2 (en) * 2009-02-03 2014-03-25 Micron Technology, Inc. Capacitor structures having improved area efficiency
JP5329265B2 (en) * 2009-03-09 2013-10-30 株式会社日立国際電気 Semiconductor device manufacturing method and substrate processing apparatus
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) * 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
JP5356516B2 (en) 2009-05-20 2013-12-04 株式会社東芝 Concave and convex pattern forming method
US8268730B2 (en) * 2009-06-03 2012-09-18 Micron Technology, Inc. Methods of masking semiconductor device structures
JP2010283213A (en) * 2009-06-05 2010-12-16 Tokyo Electron Ltd Substrate processing method
US7972926B2 (en) 2009-07-02 2011-07-05 Micron Technology, Inc. Methods of forming memory cells; and methods of forming vertical structures
CN102054668B (en) * 2009-10-28 2012-02-22 中国科学院微电子研究所 Method for masking medium etching by electronic beam positive photoresist Zep 520
US8003482B2 (en) 2009-11-19 2011-08-23 Micron Technology, Inc. Methods of processing semiconductor substrates in forming scribe line alignment marks
US8153522B2 (en) 2010-03-02 2012-04-10 Micron Technology, Inc. Patterning mask and method of formation of mask using step double patterning
US8621398B2 (en) * 2010-05-14 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Automatic layout conversion for FinFET device
US8541765B2 (en) 2010-05-25 2013-09-24 Micron Technology, Inc. Resistance variable memory cell structures and methods
US8512938B2 (en) 2010-06-14 2013-08-20 Micron Technology, Inc. Methods of forming a pattern in a material and methods of forming openings in a material to be patterned
US8574954B2 (en) 2010-08-31 2013-11-05 Micron Technology, Inc. Phase change memory structures and methods
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8288083B2 (en) 2010-11-05 2012-10-16 Micron Technology, Inc. Methods of forming patterned masks
US8901016B2 (en) 2010-12-28 2014-12-02 Asm Japan K.K. Method of forming metal oxide hardmask
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
KR20130015145A (en) * 2011-08-02 2013-02-13 삼성전자주식회사 Method of forming fine patterns for semiconductor device
US8309462B1 (en) * 2011-09-29 2012-11-13 Sandisk Technologies Inc. Double spacer quadruple patterning with self-connected hook-up
TWI473205B (en) * 2011-11-24 2015-02-11 Powerchip Technology Corp Method for forming contact hole
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8551690B2 (en) 2012-01-20 2013-10-08 Micron Technology, Inc. Methods of forming patterns
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
KR101908980B1 (en) 2012-04-23 2018-10-17 삼성전자주식회사 Field effect transistor
US9006911B2 (en) * 2012-05-16 2015-04-14 Nanya Technology Corporation Method for forming patterns of dense conductor lines and their contact pads, and memory array having dense conductor lines and contact pads
CN103474389B (en) * 2012-06-06 2016-03-02 中芯国际集成电路制造(上海)有限公司 The manufacture method of metal interconnect structure
JP6236918B2 (en) * 2012-06-26 2017-11-29 大日本印刷株式会社 Method for producing template for nanoimprint
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8735296B2 (en) 2012-07-18 2014-05-27 International Business Machines Corporation Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9111857B2 (en) * 2012-09-21 2015-08-18 Micron Technology, Inc. Method, system and device for recessed contact in memory array
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US8697538B1 (en) * 2012-11-07 2014-04-15 Winbond Electronics Corp. Method of forming pattern in substrate
US8932956B2 (en) 2012-12-04 2015-01-13 International Business Machines Corporation Far back end of the line stack encapsulation
US8999852B2 (en) 2012-12-12 2015-04-07 Micron Technology, Inc. Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
US8889558B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8889559B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US9213239B2 (en) 2013-01-22 2015-12-15 Micron Technology, Inc. Methods of forming patterns for semiconductor device structures
US8623770B1 (en) 2013-02-21 2014-01-07 HGST Netherlands B.V. Method for sidewall spacer line doubling using atomic layer deposition of a titanium oxide
US8937018B2 (en) 2013-03-06 2015-01-20 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9437443B2 (en) 2013-06-12 2016-09-06 Globalfoundries Inc. Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides
US9583381B2 (en) 2013-06-14 2017-02-28 Micron Technology, Inc. Methods for forming semiconductor devices and semiconductor device structures
US9190291B2 (en) 2013-07-03 2015-11-17 United Microelectronics Corp. Fin-shaped structure forming process
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US10179947B2 (en) 2013-11-26 2019-01-15 Asm Ip Holding B.V. Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition
US9177797B2 (en) * 2013-12-04 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using high selectivity spacers for pitch reduction
US9123825B2 (en) 2014-01-13 2015-09-01 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits using laser interference lithography techniques
KR102233577B1 (en) * 2014-02-25 2021-03-30 삼성전자주식회사 Method for forming patterns of a semiconductor device
US9508713B2 (en) 2014-03-05 2016-11-29 International Business Machines Corporation Densely spaced fins for semiconductor fin field effect transistors
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US9373678B2 (en) * 2014-06-17 2016-06-21 Globalfoundries Inc. Non-planar capacitors with finely tuned capacitance values and methods of forming the non-planar capacitors
KR102257038B1 (en) 2014-06-23 2021-05-28 삼성전자주식회사 Method for forming fine patterns of semiconductor devices, and method for forming semiconductor devices using the same, and semiconductor devices formed by using the same
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
KR102300403B1 (en) 2014-11-19 2021-09-09 에이에스엠 아이피 홀딩 비.브이. Method of depositing thin film
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9478415B2 (en) 2015-02-13 2016-10-25 Asm Ip Holding B.V. Method for forming film having low resistance and shallow junction depth
US9299924B1 (en) 2015-06-29 2016-03-29 International Business Machines Corporation Injection pillar definition for line MRAM by a self-aligned sidewall transfer
US9899291B2 (en) 2015-07-13 2018-02-20 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
KR102280471B1 (en) 2015-07-20 2021-07-22 삼성전자주식회사 Method of forming active patterns, active pattern array, and method of manufacturing semiconductor device
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10087525B2 (en) 2015-08-04 2018-10-02 Asm Ip Holding B.V. Variable gap hard stop design
US9647114B2 (en) 2015-08-14 2017-05-09 Asm Ip Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
US20170053793A1 (en) * 2015-08-17 2017-02-23 Tokyo Electron Limited Method and system for sculpting spacer sidewall mask
US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9601693B1 (en) 2015-09-24 2017-03-21 Lam Research Corporation Method for encapsulating a chalcogenide material
US20170092576A1 (en) * 2015-09-29 2017-03-30 HGST Netherlands B.V. Contacting nano-imprinted cross-point arrays to a substrate
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9882028B2 (en) * 2016-06-29 2018-01-30 International Business Machines Corporation Pitch split patterning for semiconductor devices
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US10177025B2 (en) 2016-07-28 2019-01-08 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10629435B2 (en) * 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel
TWI697032B (en) * 2016-10-24 2020-06-21 聯華電子股份有限公司 Method of fabricating semiconductor device
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US10832908B2 (en) 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US10431457B2 (en) 2016-11-25 2019-10-01 United Microelectronics Corp. Method for forming patterned structure
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
CN108389796A (en) * 2017-02-03 2018-08-10 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US10103040B1 (en) 2017-03-31 2018-10-16 Asm Ip Holding B.V. Apparatus and method for manufacturing a semiconductor device
USD830981S1 (en) 2017-04-07 2018-10-16 Asm Ip Holding B.V. Susceptor for semiconductor substrate processing apparatus
CN109309091A (en) 2017-07-28 2019-02-05 联华电子股份有限公司 Patterning method
US10236177B1 (en) 2017-08-22 2019-03-19 ASM IP Holding B.V.. Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN107731665B (en) * 2017-11-13 2023-07-25 长鑫存储技术有限公司 Integrated circuit fabrication for pitch multiplication
CN109872946B (en) 2017-12-04 2020-12-01 联华电子股份有限公司 Method for forming semiconductor device
US10290508B1 (en) 2017-12-05 2019-05-14 Asm Ip Holding B.V. Method for forming vertical spacers for spacer-defined patterning
US10755969B2 (en) 2018-01-01 2020-08-25 International Business Machines Corporation Multi-patterning techniques for fabricating an array of metal lines with different widths
US10276434B1 (en) 2018-01-02 2019-04-30 International Business Machines Corporation Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
US11404275B2 (en) 2018-03-02 2022-08-02 Lam Research Corporation Selective deposition using hydrolysis
US10475648B1 (en) * 2018-05-01 2019-11-12 United Microelectronics Corp. Method for patterning a semiconductor structure
US20190390341A1 (en) 2018-06-26 2019-12-26 Lam Research Corporation Deposition tool and method for depositing metal oxide films on organic materials
US10522395B1 (en) 2018-08-21 2019-12-31 Micron Technology, Inc. Methods of forming a pattern
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
CN112309843A (en) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 Selective deposition method for achieving high dopant doping
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. Substrate processing apparatus and substrate processing method
US11482414B2 (en) 2019-12-18 2022-10-25 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Ultra-low temperature ALD to form high-quality Si-containing film
US11437317B2 (en) 2020-02-10 2022-09-06 International Business Machines Corporation Single-mask alternating line deposition
US20220189771A1 (en) * 2020-12-10 2022-06-16 Applied Materials, Inc. Underlayer film for semiconductor device formation
KR20220087229A (en) 2020-12-17 2022-06-24 삼성전자주식회사 Semiconductor devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005034215A1 (en) * 2003-09-30 2005-04-14 Infineon Technologies Ag Method for the production of a hard mask and hard mask arrangement
US20060046484A1 (en) * 2004-09-02 2006-03-02 Abatchev Mirzafer K Method for integrated circuit fabrication using pitch multiplication
WO2006127586A2 (en) * 2005-05-23 2006-11-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features

Family Cites Families (232)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748237Y2 (en) 1978-12-28 1982-10-22
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4246822A (en) 1979-02-09 1981-01-27 Kawai Musical Instrument Mfg. Co. Ltd. Data transfer apparatus for digital polyphonic tone synthesizer
US4508579A (en) 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
DE3112672C1 (en) 1981-03-31 1983-06-01 M.A.N.- Roland Druckmaschinen AG, 6050 Offenbach Stop for the trailing edge of the sheet in sheet delivery on sheet-processing machines
US4432132A (en) 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4419809A (en) 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
DE3242113A1 (en) 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart METHOD FOR PRODUCING A THIN DIELECTRIC INSULATION IN A SILICON SEMICONDUCTOR BODY
US4716131A (en) 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4570325A (en) 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
US4713756A (en) 1985-02-28 1987-12-15 Westinghouse Electric Corp. Non-volatile memory device for a programmable controller
US4648937A (en) 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
GB8528967D0 (en) 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
DE3682395D1 (en) 1986-03-27 1991-12-12 Ibm METHOD FOR PRODUCING SIDE STRUCTURES.
US4751645A (en) 1986-08-12 1988-06-14 Abrams William R Method for sonic analysis of an anomaly in a seafloor topographic representation
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
JPS6435916U (en) 1987-08-28 1989-03-03
US4776922A (en) 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5053105A (en) 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
DE4034612A1 (en) 1990-10-31 1992-05-07 Huels Chemische Werke Ag METHOD FOR PRODUCING ORGANOSILANES CONTAINING METHACRYLOXY OR ACRYLOXY GROUPS
IT1243919B (en) 1990-11-20 1994-06-28 Cons Ric Microelettronica PROCEDURE FOR OBTAINING PLANARIZED SUBMICHROMETRIC GROOVES IN INTEGRATED CIRCUITS REALIZED WITH ULSI TECHNOLOGY
JPH05343370A (en) 1992-06-10 1993-12-24 Toshiba Corp Forming method for fine pattern
US5330879A (en) 1992-07-16 1994-07-19 Micron Technology, Inc. Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
DE4236609A1 (en) 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
US5407785A (en) 1992-12-18 1995-04-18 Vlsi Technology, Inc. Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures
US5470661A (en) 1993-01-07 1995-11-28 International Business Machines Corporation Diamond-like carbon films from a hydrocarbon helium plasma
JP3311070B2 (en) 1993-03-15 2002-08-05 株式会社東芝 Semiconductor device
US6042998A (en) 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
JP3720064B2 (en) 1994-01-20 2005-11-24 株式会社ルネサステクノロジ Semiconductor integrated circuit
KR970007173B1 (en) 1994-07-14 1997-05-03 현대전자산업 주식회사 Fine patterning method
JPH0855920A (en) 1994-08-15 1996-02-27 Toshiba Corp Manufacture of semiconductor device
JPH0855908A (en) 1994-08-17 1996-02-27 Toshiba Corp Semiconductor device
US5600153A (en) 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
TW366367B (en) 1995-01-26 1999-08-11 Ibm Sputter deposition of hydrogenated amorphous carbon film
US5795830A (en) 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
KR100190757B1 (en) 1995-06-30 1999-06-01 김영환 Method of forming mosfet
JP3393286B2 (en) 1995-09-08 2003-04-07 ソニー株式会社 Pattern formation method
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JPH09293793A (en) 1996-04-26 1997-11-11 Mitsubishi Electric Corp Semiconductor device provided with thin film transistor and manufacture thereof
TW329539B (en) 1996-07-05 1998-04-11 Mitsubishi Electric Corp The semiconductor device and its manufacturing method
JP3164026B2 (en) * 1996-08-21 2001-05-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6395613B1 (en) 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US5895740A (en) 1996-11-13 1999-04-20 Vanguard International Semiconductor Corp. Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers
US6288431B1 (en) 1997-04-04 2001-09-11 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
KR100231134B1 (en) 1997-06-14 1999-11-15 문정환 Method for forming metal interconnector of semiconductor device
DE19728559A1 (en) * 1997-07-04 1999-01-07 Km Europa Metal Ag Cable head of a high-current multi-cable for DC applications
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
KR100247862B1 (en) 1997-12-11 2000-03-15 윤종용 Semiconductor device and method for manufacturing the same
US6143476A (en) 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
US6291334B1 (en) 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6004862A (en) 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
JP2975917B2 (en) 1998-02-06 1999-11-10 株式会社半導体プロセス研究所 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
US5933725A (en) 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6020255A (en) 1998-07-13 2000-02-01 Taiwan Semiconductor Manufacturing Company Dual damascene interconnect process with borderless contact
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6333866B1 (en) 1998-09-28 2001-12-25 Texas Instruments Incorporated Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US6071789A (en) 1998-11-10 2000-06-06 Vanguard International Semiconductor Corporation Method for simultaneously fabricating a DRAM capacitor and metal interconnections
US6204187B1 (en) 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
US6271141B2 (en) 1999-03-23 2001-08-07 Micron Technology, Inc. Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines
US6211044B1 (en) 1999-04-12 2001-04-03 Advanced Micro Devices Process for fabricating a semiconductor device component using a selective silicidation reaction
JP2000307084A (en) 1999-04-23 2000-11-02 Hitachi Ltd Semiconductor integrated circuit device and its manufacture
US6110837A (en) 1999-04-28 2000-08-29 Worldwide Semiconductor Manufacturing Corp. Method for forming a hard mask of half critical dimension
US6136662A (en) 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
JP2000357736A (en) 1999-06-15 2000-12-26 Toshiba Corp Semiconductor device and manufacture thereof
DE19928781C1 (en) 1999-06-23 2000-07-06 Siemens Ag DRAM cell array has deep word line trenches for increasing transistor channel length and has no fixed potential word lines separating adjacent memory cells
US6330777B1 (en) 1999-07-20 2001-12-18 Tcw Technologies Inc. Three dimensional metal structural assembly and production method
JP2001077196A (en) 1999-09-08 2001-03-23 Sony Corp Manufacture of semiconductor device
US6282113B1 (en) 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6362057B1 (en) * 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
US6582891B1 (en) 1999-12-02 2003-06-24 Axcelis Technologies, Inc. Process for reducing edge roughness in patterned photoresist
KR100311050B1 (en) 1999-12-14 2001-11-05 윤종용 Method for manufacturing electrode of capacitor
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6967140B2 (en) 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6297554B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Dual damascene interconnect structure with reduced parasitic capacitance
US6423474B1 (en) 2000-03-21 2002-07-23 Micron Technology, Inc. Use of DARC and BARC in flash memory processing
JP3805603B2 (en) 2000-05-29 2006-08-02 富士通株式会社 Semiconductor device and manufacturing method thereof
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6455372B1 (en) 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics
US6348380B1 (en) 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
SE517275C2 (en) 2000-09-20 2002-05-21 Obducat Ab Wet etching of substrate involves arranging on the substrate a passivating substance comprising active substance reacting with component contained in etchant to form etch protecting compound
US6335257B1 (en) 2000-09-29 2002-01-01 Vanguard International Semiconductor Corporation Method of making pillar-type structure on semiconductor substrate
US6667237B1 (en) 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
JP2002124585A (en) 2000-10-17 2002-04-26 Hitachi Ltd Nonvolatile semiconductor memory device and production method therefor
US6534243B1 (en) 2000-10-23 2003-03-18 Advanced Micro Devices, Inc. Chemical feature doubling process
US6926843B2 (en) 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US6664028B2 (en) 2000-12-04 2003-12-16 United Microelectronics Corp. Method of forming opening in wafer layer
JP3406302B2 (en) 2001-01-16 2003-05-12 株式会社半導体先端テクノロジーズ Method of forming fine pattern, method of manufacturing semiconductor device, and semiconductor device
US6531727B2 (en) 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6424001B1 (en) 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6597203B2 (en) 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US6545904B2 (en) 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
US7176109B2 (en) 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
US6475867B1 (en) 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US6548347B2 (en) 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6740594B2 (en) 2001-05-31 2004-05-25 Infineon Technologies Ag Method for removing carbon-containing polysilane from a semiconductor without stripping
US6960806B2 (en) 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
JP2003031686A (en) 2001-07-16 2003-01-31 Sony Corp Semiconductor storage device and its manufacturing method
ATE544176T1 (en) * 2001-07-18 2012-02-15 Infineon Technologies Ag SELECTIVE BASE SETTING
US6522584B1 (en) 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6599684B2 (en) 2001-08-13 2003-07-29 Eastman Kodak Company Color photothermographic element comprising a dye-forming system for forming a novel infrared dye
US6744094B2 (en) 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
TW497138B (en) 2001-08-28 2002-08-01 Winbond Electronics Corp Method for improving consistency of critical dimension
DE10142590A1 (en) * 2001-08-31 2003-04-03 Infineon Technologies Ag Production of resist structures used in semiconductor industry comprises applying a resist film on a substrate, forming a resist structure with bars from the film, and removing reinforced sections
US7045383B2 (en) 2001-09-19 2006-05-16 BAE Systems Information and Ovonyx, Inc Method for making tapered opening for programmable resistance memory element
JP2003133437A (en) 2001-10-24 2003-05-09 Hitachi Ltd Semiconductor device and manufacturing method thereof
US7226853B2 (en) 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure
TW576864B (en) 2001-12-28 2004-02-21 Toshiba Corp Method for manufacturing a light-emitting device
US6638441B2 (en) 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
DE10207131B4 (en) 2002-02-20 2007-12-20 Infineon Technologies Ag Process for forming a hardmask in a layer on a flat disk
US6620715B1 (en) 2002-03-29 2003-09-16 Cypress Semiconductor Corp. Method for forming sub-critical dimension structures in an integrated circuit
US6759180B2 (en) 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
US20030207584A1 (en) 2002-05-01 2003-11-06 Swaminathan Sivakumar Patterning tighter and looser pitch geometries
US6951709B2 (en) 2002-05-03 2005-10-04 Micron Technology, Inc. Method of fabricating a semiconductor multilevel interconnect structure
US6602779B1 (en) 2002-05-13 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6703312B2 (en) 2002-05-17 2004-03-09 International Business Machines Corporation Method of forming active devices of different gatelengths using lithographic printed gate images of same length
US6818141B1 (en) 2002-06-10 2004-11-16 Advanced Micro Devices, Inc. Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines
US6734107B2 (en) 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6559017B1 (en) 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
US6777725B2 (en) 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
KR100476924B1 (en) * 2002-06-14 2005-03-17 삼성전자주식회사 Method Of Forming Fine Pattern Of Semiconductor Device
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
AU2003280498A1 (en) 2002-06-27 2004-01-19 Advanced Micro Devices, Inc. Method of defining the dimensions of circuit elements by using spacer deposition techniques
US6835663B2 (en) 2002-06-28 2004-12-28 Infineon Technologies Ag Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
US6500756B1 (en) 2002-06-28 2002-12-31 Advanced Micro Devices, Inc. Method of forming sub-lithographic spaces between polysilicon lines
US6689695B1 (en) 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US20040018738A1 (en) 2002-07-22 2004-01-29 Wei Liu Method for fabricating a notch gate structure of a field effect transistor
US6734063B2 (en) 2002-07-22 2004-05-11 Infineon Technologies Ag Non-volatile memory cell and fabrication method
US6913871B2 (en) 2002-07-23 2005-07-05 Intel Corporation Fabricating sub-resolution structures in planar lightwave devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6764949B2 (en) 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6673684B1 (en) 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
US6939808B2 (en) 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
KR100480610B1 (en) 2002-08-09 2005-03-31 삼성전자주식회사 Forming method for fine patterns using silicon oxide layer
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US6888187B2 (en) 2002-08-26 2005-05-03 International Business Machines Corporation DRAM cell with enhanced SER immunity
US7205598B2 (en) 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
US6794699B2 (en) 2002-08-29 2004-09-21 Micron Technology Inc Annular gate and technique for fabricating an annular gate
US6756284B2 (en) 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
JP4034164B2 (en) 2002-10-28 2008-01-16 富士通株式会社 Method for manufacturing fine pattern and method for manufacturing semiconductor device
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6804142B2 (en) 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7119020B2 (en) 2002-12-04 2006-10-10 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6686245B1 (en) 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US6916594B2 (en) 2002-12-30 2005-07-12 Hynix Semiconductor Inc. Overcoating composition for photoresist and method for forming photoresist pattern using the same
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US7084076B2 (en) 2003-02-27 2006-08-01 Samsung Electronics, Co., Ltd. Method for forming silicon dioxide film using siloxane
TWI262960B (en) 2003-02-27 2006-10-01 Samsung Electronics Co Ltd Method for forming silicon dioxide film using siloxane
JP3920235B2 (en) * 2003-03-24 2007-05-30 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US7015124B1 (en) 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
JP4578785B2 (en) 2003-05-21 2010-11-10 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6835662B1 (en) 2003-07-14 2004-12-28 Advanced Micro Devices, Inc. Partially de-coupled core and periphery gate module process
DE10332725A1 (en) 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Method for self-adjusting reduction of structures
US7105431B2 (en) 2003-08-22 2006-09-12 Micron Technology, Inc. Masking methods
KR100536801B1 (en) 2003-10-01 2005-12-14 동부아남반도체 주식회사 Semiconductor device and fabrication method thereof
US6867116B1 (en) 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
JP2005150333A (en) 2003-11-14 2005-06-09 Sony Corp Method of manufacturing semiconductor device
KR101002928B1 (en) 2003-11-29 2010-12-27 주식회사 하이닉스반도체 Fabricating method of minute line in semiconductor device
JP2005191254A (en) * 2003-12-25 2005-07-14 Fujitsu Ltd Method of manufacturing semiconductor device
KR100554514B1 (en) * 2003-12-26 2006-03-03 삼성전자주식회사 Method for forming pattern and gate electrode in semiconductor processing
KR100545697B1 (en) * 2003-12-29 2006-01-24 주식회사 하이닉스반도체 Trench device isolation method for semiconductor devices
US6998332B2 (en) 2004-01-08 2006-02-14 International Business Machines Corporation Method of independent P and N gate length control of FET device made by sidewall image transfer technique
US6875703B1 (en) 2004-01-20 2005-04-05 International Business Machines Corporation Method for forming quadruple density sidewall image transfer (SIT) structures
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
US7064078B2 (en) 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US6989308B2 (en) * 2004-03-11 2006-01-24 International Business Machines Corporation Method of forming FinFET gates without long etches
WO2005094231A2 (en) 2004-03-19 2005-10-13 The Regents Of The University Of California Methods for fabrication of positional and compositionally controlled nanostructures on substrate
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
US7183205B2 (en) 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7473644B2 (en) 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
US7074666B2 (en) 2004-07-28 2006-07-11 International Business Machines Corporation Borderless contact structures
KR100704470B1 (en) 2004-07-29 2007-04-10 주식회사 하이닉스반도체 Method for fabrication of semiconductor device using amorphous carbon layer to sacrificial hard mask
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7175944B2 (en) 2004-08-31 2007-02-13 Micron Technology, Inc. Prevention of photoresist scumming
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
KR100614651B1 (en) 2004-10-11 2006-08-22 삼성전자주식회사 Apparatus And Method For Pattern Exposure, Photomask Used Therefor, Design Method For The Photomask, Illuminating System Therefor and Implementing Method For The Illuminating System
US7208379B2 (en) 2004-11-29 2007-04-24 Texas Instruments Incorporated Pitch multiplication process
US7298004B2 (en) 2004-11-30 2007-11-20 Infineon Technologies Ag Charge-trapping memory cell and method for production
KR100596795B1 (en) 2004-12-16 2006-07-05 주식회사 하이닉스반도체 Capacitor of semiconductor device and method for forming the same
US7254890B2 (en) * 2004-12-30 2007-08-14 Lexmark International, Inc. Method of making a microfluid ejection head structure
US7183142B2 (en) 2005-01-13 2007-02-27 International Business Machines Corporation FinFETs with long gate length at high density
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
KR100787352B1 (en) * 2005-02-23 2007-12-18 주식회사 하이닉스반도체 Composition for Hard Mask and Method for Forming Pattern of Semiconductor Device using it
US7329613B2 (en) * 2005-03-11 2008-02-12 International Business Machines Corporation Structure and method for forming semiconductor wiring levels using atomic layer deposition
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7431927B2 (en) 2005-03-24 2008-10-07 Epitomics, Inc. TNFα-neutralizing antibodies
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100640639B1 (en) 2005-04-19 2006-10-31 삼성전자주식회사 Semiconductor device having fine contact and method of manufacturing the same
US7547599B2 (en) 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
KR100648859B1 (en) * 2005-06-07 2006-11-24 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
JP2006351861A (en) 2005-06-16 2006-12-28 Toshiba Corp Manufacturing method of semiconductor device
TW200705541A (en) * 2005-07-25 2007-02-01 Li Bing Huan Manufacturing method of nano-sticker
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7291563B2 (en) * 2005-08-18 2007-11-06 Micron Technology, Inc. Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7323374B2 (en) * 2005-09-19 2008-01-29 International Business Machines Corporation Dense chevron finFET and method of manufacturing same
KR100675897B1 (en) * 2005-09-30 2007-02-02 주식회사 하이닉스반도체 Method for forming transistor of semiconductor device
US7244638B2 (en) 2005-09-30 2007-07-17 Infineon Technologies Ag Semiconductor memory device and method of production
KR101200938B1 (en) 2005-09-30 2012-11-13 삼성전자주식회사 Method for forming patterns of semiconductor device
KR100714305B1 (en) 2005-12-26 2007-05-02 삼성전자주식회사 Method of forming self aligned double pattern
US8716772B2 (en) 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
KR100672123B1 (en) 2006-02-02 2007-01-19 주식회사 하이닉스반도체 Method for forming micro pattern in semiconductor device
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US20070210449A1 (en) * 2006-03-07 2007-09-13 Dirk Caspary Memory device and an array of conductive lines and methods of making the same
US7351666B2 (en) * 2006-03-17 2008-04-01 International Business Machines Corporation Layout and process to contact sub-lithographic structures
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US7825460B2 (en) 2006-09-06 2010-11-02 International Business Machines Corporation Vertical field effect transistor arrays and methods for fabrication thereof
US20080292991A1 (en) 2007-05-24 2008-11-27 Advanced Micro Devices, Inc. High fidelity multiple resist patterning
US7851135B2 (en) 2007-11-30 2010-12-14 Hynix Semiconductor Inc. Method of forming an etching mask pattern from developed negative and positive photoresist layers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005034215A1 (en) * 2003-09-30 2005-04-14 Infineon Technologies Ag Method for the production of a hard mask and hard mask arrangement
US20060046484A1 (en) * 2004-09-02 2006-03-02 Abatchev Mirzafer K Method for integrated circuit fabrication using pitch multiplication
WO2006127586A2 (en) * 2005-05-23 2006-11-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features

Cited By (348)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8357618B2 (en) 2007-10-26 2013-01-22 Applied Materials, Inc. Frequency doubling using a photo-resist template mask
TWI493598B (en) * 2007-10-26 2015-07-21 Applied Materials Inc Frequency doubling using a photo-resist template mask
JP2009246332A (en) * 2008-03-28 2009-10-22 Samsung Electronics Co Ltd Method of forming fine pattern of semiconductor device
KR101448854B1 (en) * 2008-03-28 2014-10-14 삼성전자주식회사 Method of forming fine patterns of semiconductor device
JP2009267111A (en) * 2008-04-25 2009-11-12 Tokyo Electron Ltd Manufacturing method for semiconductor device, manufacturing apparatus, computer program, and computer-readable memory medium
JP2009302143A (en) * 2008-06-10 2009-12-24 Toshiba Corp Manufacturing method of semiconductor device
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
KR101680379B1 (en) 2009-04-01 2016-11-28 에이에스엠 저펜 가부시기가이샤 Method of Depositing Silicon Oxide Film by Plasma Enhanced Atomic Layer Deposition at Low Temperature
JP2010245518A (en) * 2009-04-01 2010-10-28 Asm Japan Kk Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature
US10480072B2 (en) 2009-04-06 2019-11-19 Asm Ip Holding B.V. Semiconductor processing reactor and components thereof
US10844486B2 (en) 2009-04-06 2020-11-24 Asm Ip Holding B.V. Semiconductor processing reactor and components thereof
US10804098B2 (en) 2009-08-14 2020-10-13 Asm Ip Holding B.V. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
JP2011040656A (en) * 2009-08-17 2011-02-24 Nippon Telegr & Teleph Corp <Ntt> Method of forming microstructure
JP2011238919A (en) * 2010-05-06 2011-11-24 Asml Netherlands Bv Production of alignment mark
US10707106B2 (en) 2011-06-06 2020-07-07 Asm Ip Holding B.V. High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
US10854498B2 (en) 2011-07-15 2020-12-01 Asm Ip Holding B.V. Wafer-supporting device and method for producing same
US11725277B2 (en) 2011-07-20 2023-08-15 Asm Ip Holding B.V. Pressure transmitter for a semiconductor processing environment
US10832903B2 (en) 2011-10-28 2020-11-10 Asm Ip Holding B.V. Process feed management for semiconductor substrate processing
US10566223B2 (en) 2012-08-28 2020-02-18 Asm Ip Holdings B.V. Systems and methods for dynamic semiconductor process scheduling
US11501956B2 (en) 2012-10-12 2022-11-15 Asm Ip Holding B.V. Semiconductor reaction chamber showerhead
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US10340125B2 (en) 2013-03-08 2019-07-02 Asm Ip Holding B.V. Pulsed remote plasma method and system
US10366864B2 (en) 2013-03-08 2019-07-30 Asm Ip Holding B.V. Method and system for in-situ formation of intermediate reactive species
US10361201B2 (en) 2013-09-27 2019-07-23 Asm Ip Holding B.V. Semiconductor structure and device formed using selective epitaxial process
US10683571B2 (en) 2014-02-25 2020-06-16 Asm Ip Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
US10604847B2 (en) 2014-03-18 2020-03-31 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US10858737B2 (en) 2014-07-28 2020-12-08 Asm Ip Holding B.V. Showerhead assembly and components thereof
US10787741B2 (en) 2014-08-21 2020-09-29 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US10561975B2 (en) 2014-10-07 2020-02-18 Asm Ip Holdings B.V. Variable conductance gas distribution apparatus and method
US11795545B2 (en) 2014-10-07 2023-10-24 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10438965B2 (en) 2014-12-22 2019-10-08 Asm Ip Holding B.V. Semiconductor device and manufacturing method thereof
US10529542B2 (en) 2015-03-11 2020-01-07 Asm Ip Holdings B.V. Cross-flow reactor and method
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US11742189B2 (en) 2015-03-12 2023-08-29 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US11242598B2 (en) 2015-06-26 2022-02-08 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10600673B2 (en) 2015-07-07 2020-03-24 Asm Ip Holding B.V. Magnetic susceptor to baseplate seal
US10312129B2 (en) 2015-09-29 2019-06-04 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US11233133B2 (en) 2015-10-21 2022-01-25 Asm Ip Holding B.V. NbMC layers
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US11676812B2 (en) 2016-02-19 2023-06-13 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on top/bottom portions
US10720322B2 (en) 2016-02-19 2020-07-21 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on top surface
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US10262859B2 (en) 2016-03-24 2019-04-16 Asm Ip Holding B.V. Process for forming a film on a substrate using multi-port injection assemblies
US10851456B2 (en) 2016-04-21 2020-12-01 Asm Ip Holding B.V. Deposition of metal borides
US10865475B2 (en) 2016-04-21 2020-12-15 Asm Ip Holding B.V. Deposition of metal borides and silicides
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US10665452B2 (en) 2016-05-02 2020-05-26 Asm Ip Holdings B.V. Source/drain performance through conformal solid state doping
US11101370B2 (en) 2016-05-02 2021-08-24 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US10249577B2 (en) 2016-05-17 2019-04-02 Asm Ip Holding B.V. Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US10541173B2 (en) 2016-07-08 2020-01-21 Asm Ip Holding B.V. Selective deposition method to form air gaps
US11649546B2 (en) 2016-07-08 2023-05-16 Asm Ip Holding B.V. Organic reactants for atomic layer deposition
US11094582B2 (en) 2016-07-08 2021-08-17 Asm Ip Holding B.V. Selective deposition method to form air gaps
US11749562B2 (en) 2016-07-08 2023-09-05 Asm Ip Holding B.V. Selective deposition method to form air gaps
US10714385B2 (en) 2016-07-19 2020-07-14 Asm Ip Holding B.V. Selective deposition of tungsten
US10381226B2 (en) 2016-07-27 2019-08-13 Asm Ip Holding B.V. Method of processing substrate
US11694892B2 (en) 2016-07-28 2023-07-04 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11205585B2 (en) 2016-07-28 2021-12-21 Asm Ip Holding B.V. Substrate processing apparatus and method of operating the same
US11107676B2 (en) 2016-07-28 2021-08-31 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11610775B2 (en) 2016-07-28 2023-03-21 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10741385B2 (en) 2016-07-28 2020-08-11 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10364493B2 (en) 2016-08-25 2019-07-30 Asm Ip Holding B.V. Exhaust apparatus and substrate processing apparatus having an exhaust line with a first ring having at least one hole on a lateral side thereof placed in the exhaust line
US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US10943771B2 (en) 2016-10-26 2021-03-09 Asm Ip Holding B.V. Methods for thermally calibrating reaction chambers
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10435790B2 (en) 2016-11-01 2019-10-08 Asm Ip Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US11810788B2 (en) 2016-11-01 2023-11-07 Asm Ip Holding B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10643904B2 (en) 2016-11-01 2020-05-05 Asm Ip Holdings B.V. Methods for forming a semiconductor device and related semiconductor device structures
US10720331B2 (en) 2016-11-01 2020-07-21 ASM IP Holdings, B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10622375B2 (en) 2016-11-07 2020-04-14 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US10644025B2 (en) 2016-11-07 2020-05-05 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US10934619B2 (en) 2016-11-15 2021-03-02 Asm Ip Holding B.V. Gas supply unit and substrate processing apparatus including the gas supply unit
US11396702B2 (en) 2016-11-15 2022-07-26 Asm Ip Holding B.V. Gas supply unit and substrate processing apparatus including the gas supply unit
US10340135B2 (en) 2016-11-28 2019-07-02 Asm Ip Holding B.V. Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
US11222772B2 (en) 2016-12-14 2022-01-11 Asm Ip Holding B.V. Substrate processing apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11001925B2 (en) 2016-12-19 2021-05-11 Asm Ip Holding B.V. Substrate processing apparatus
US10784102B2 (en) 2016-12-22 2020-09-22 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11251035B2 (en) 2016-12-22 2022-02-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10867788B2 (en) 2016-12-28 2020-12-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10655221B2 (en) 2017-02-09 2020-05-19 Asm Ip Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
US11410851B2 (en) 2017-02-15 2022-08-09 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10468262B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by a cyclical deposition and related semiconductor device structures
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US11658030B2 (en) 2017-03-29 2023-05-23 Asm Ip Holding B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10283353B2 (en) 2017-03-29 2019-05-07 Asm Ip Holding B.V. Method of reforming insulating film deposited on substrate with recess pattern
US10714335B2 (en) 2017-04-25 2020-07-14 Asm Ip Holding B.V. Method of depositing thin film and method of manufacturing semiconductor device
US10950432B2 (en) 2017-04-25 2021-03-16 Asm Ip Holding B.V. Method of depositing thin film and method of manufacturing semiconductor device
US10446393B2 (en) 2017-05-08 2019-10-15 Asm Ip Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
US10892156B2 (en) 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US10504742B2 (en) 2017-05-31 2019-12-10 Asm Ip Holding B.V. Method of atomic layer etching using hydrogen plasma
US10886123B2 (en) 2017-06-02 2021-01-05 Asm Ip Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10685834B2 (en) 2017-07-05 2020-06-16 Asm Ip Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
US11164955B2 (en) 2017-07-18 2021-11-02 Asm Ip Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
US10734497B2 (en) 2017-07-18 2020-08-04 Asm Ip Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
US11695054B2 (en) 2017-07-18 2023-07-04 Asm Ip Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
US11004977B2 (en) 2017-07-19 2021-05-11 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US11802338B2 (en) 2017-07-26 2023-10-31 Asm Ip Holding B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10312055B2 (en) 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
US10605530B2 (en) 2017-07-26 2020-03-31 Asm Ip Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
US11417545B2 (en) 2017-08-08 2022-08-16 Asm Ip Holding B.V. Radiation shield
US11587821B2 (en) 2017-08-08 2023-02-21 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10672636B2 (en) 2017-08-09 2020-06-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
USD900036S1 (en) 2017-08-24 2020-10-27 Asm Ip Holding B.V. Heater electrical connector and adapter
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US11069510B2 (en) 2017-08-30 2021-07-20 Asm Ip Holding B.V. Substrate processing apparatus
US11581220B2 (en) 2017-08-30 2023-02-14 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US10607895B2 (en) 2017-09-18 2020-03-31 Asm Ip Holdings B.V. Method for forming a semiconductor device structure comprising a gate fill metal
US10928731B2 (en) 2017-09-21 2021-02-23 Asm Ip Holding B.V. Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same
US10844484B2 (en) 2017-09-22 2020-11-24 Asm Ip Holding B.V. Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US11387120B2 (en) 2017-09-28 2022-07-12 Asm Ip Holding B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US11094546B2 (en) 2017-10-05 2021-08-17 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10734223B2 (en) 2017-10-10 2020-08-04 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10923344B2 (en) 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
US10734244B2 (en) 2017-11-16 2020-08-04 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by the same
US10910262B2 (en) 2017-11-16 2021-02-02 Asm Ip Holding B.V. Method of selectively depositing a capping layer structure on a semiconductor device structure
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
US11127617B2 (en) 2017-11-27 2021-09-21 Asm Ip Holding B.V. Storage device for storing wafer cassettes for use with a batch furnace
US11639811B2 (en) 2017-11-27 2023-05-02 Asm Ip Holding B.V. Apparatus including a clean mini environment
US11682572B2 (en) 2017-11-27 2023-06-20 Asm Ip Holdings B.V. Storage device for storing wafer cassettes for use with a batch furnace
US11501973B2 (en) 2018-01-16 2022-11-15 Asm Ip Holding B.V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
US11393690B2 (en) 2018-01-19 2022-07-19 Asm Ip Holding B.V. Deposition method
US11482412B2 (en) 2018-01-19 2022-10-25 Asm Ip Holding B.V. Method for depositing a gap-fill layer by plasma-assisted deposition
USD903477S1 (en) 2018-01-24 2020-12-01 Asm Ip Holdings B.V. Metal clamp
US11018047B2 (en) 2018-01-25 2021-05-25 Asm Ip Holding B.V. Hybrid lift pin
USD913980S1 (en) 2018-02-01 2021-03-23 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US10535516B2 (en) 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US11735414B2 (en) 2018-02-06 2023-08-22 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US11387106B2 (en) 2018-02-14 2022-07-12 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US11685991B2 (en) 2018-02-14 2023-06-27 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10731249B2 (en) 2018-02-15 2020-08-04 Asm Ip Holding B.V. Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
US10658181B2 (en) 2018-02-20 2020-05-19 Asm Ip Holding B.V. Method of spacer-defined direct patterning in semiconductor fabrication
US11482418B2 (en) 2018-02-20 2022-10-25 Asm Ip Holding B.V. Substrate processing method and apparatus
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
US11398382B2 (en) 2018-03-27 2022-07-26 Asm Ip Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US10847371B2 (en) 2018-03-27 2020-11-24 Asm Ip Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
US10867786B2 (en) 2018-03-30 2020-12-15 Asm Ip Holding B.V. Substrate processing method
US11469098B2 (en) 2018-05-08 2022-10-11 Asm Ip Holding B.V. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
US11056567B2 (en) 2018-05-11 2021-07-06 Asm Ip Holding B.V. Method of forming a doped metal carbide film on a substrate and related semiconductor device structures
US11908733B2 (en) 2018-05-28 2024-02-20 Asm Ip Holding B.V. Substrate processing method and device manufactured by using the same
US11361990B2 (en) 2018-05-28 2022-06-14 Asm Ip Holding B.V. Substrate processing method and device manufactured by using the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11837483B2 (en) 2018-06-04 2023-12-05 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US11296189B2 (en) 2018-06-21 2022-04-05 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
US11530483B2 (en) 2018-06-21 2022-12-20 Asm Ip Holding B.V. Substrate processing system
US11492703B2 (en) 2018-06-27 2022-11-08 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11499222B2 (en) 2018-06-27 2022-11-15 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11814715B2 (en) 2018-06-27 2023-11-14 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11168395B2 (en) 2018-06-29 2021-11-09 Asm Ip Holding B.V. Temperature-controlled flange and reactor system including same
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10914004B2 (en) 2018-06-29 2021-02-09 Asm Ip Holding B.V. Thin-film deposition method and manufacturing method of semiconductor device
US11646197B2 (en) 2018-07-03 2023-05-09 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755923B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US11923190B2 (en) 2018-07-03 2024-03-05 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10767789B2 (en) 2018-07-16 2020-09-08 Asm Ip Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US10883175B2 (en) 2018-08-09 2021-01-05 Asm Ip Holding B.V. Vertical furnace for processing substrates and a liner for use therein
US10829852B2 (en) 2018-08-16 2020-11-10 Asm Ip Holding B.V. Gas distribution device for a wafer processing apparatus
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
US11274369B2 (en) 2018-09-11 2022-03-15 Asm Ip Holding B.V. Thin film deposition method
US11804388B2 (en) 2018-09-11 2023-10-31 Asm Ip Holding B.V. Substrate processing apparatus and method
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
US11885023B2 (en) 2018-10-01 2024-01-30 Asm Ip Holding B.V. Substrate retaining apparatus, system including the apparatus, and method of using same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
US11414760B2 (en) 2018-10-08 2022-08-16 Asm Ip Holding B.V. Substrate support unit, thin film deposition apparatus including the same, and substrate processing apparatus including the same
US10847365B2 (en) 2018-10-11 2020-11-24 Asm Ip Holding B.V. Method of forming conformal silicon carbide film by cyclic CVD
US10811256B2 (en) 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
US11251068B2 (en) 2018-10-19 2022-02-15 Asm Ip Holding B.V. Substrate processing apparatus and substrate processing method
US11664199B2 (en) 2018-10-19 2023-05-30 Asm Ip Holding B.V. Substrate processing apparatus and substrate processing method
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film
US11735445B2 (en) 2018-10-31 2023-08-22 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
US11499226B2 (en) 2018-11-02 2022-11-15 Asm Ip Holding B.V. Substrate supporting unit and a substrate processing device including the same
US11866823B2 (en) 2018-11-02 2024-01-09 Asm Ip Holding B.V. Substrate supporting unit and a substrate processing device including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11244825B2 (en) 2018-11-16 2022-02-08 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US11798999B2 (en) 2018-11-16 2023-10-24 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US11411088B2 (en) 2018-11-16 2022-08-09 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10559458B1 (en) 2018-11-26 2020-02-11 Asm Ip Holding B.V. Method of forming oxynitride film
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
US11488819B2 (en) 2018-12-04 2022-11-01 Asm Ip Holding B.V. Method of cleaning substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
US11769670B2 (en) 2018-12-13 2023-09-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
US11658029B2 (en) 2018-12-14 2023-05-23 Asm Ip Holding B.V. Method of forming a device structure using selective deposition of gallium nitride and system for same
US11390946B2 (en) 2019-01-17 2022-07-19 Asm Ip Holding B.V. Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
US11171025B2 (en) 2019-01-22 2021-11-09 Asm Ip Holding B.V. Substrate processing device
US11127589B2 (en) 2019-02-01 2021-09-21 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
US11615980B2 (en) 2019-02-20 2023-03-28 Asm Ip Holding B.V. Method and apparatus for filling a recess formed within a substrate surface
US11798834B2 (en) 2019-02-20 2023-10-24 Asm Ip Holding B.V. Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
US11482533B2 (en) 2019-02-20 2022-10-25 Asm Ip Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
US11342216B2 (en) 2019-02-20 2022-05-24 Asm Ip Holding B.V. Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
US11251040B2 (en) 2019-02-20 2022-02-15 Asm Ip Holding B.V. Cyclical deposition method including treatment step and apparatus for same
US11227789B2 (en) 2019-02-20 2022-01-18 Asm Ip Holding B.V. Method and apparatus for filling a recess formed within a substrate surface
US11629407B2 (en) 2019-02-22 2023-04-18 Asm Ip Holding B.V. Substrate processing apparatus and method for processing substrates
US11424119B2 (en) 2019-03-08 2022-08-23 Asm Ip Holding B.V. Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
US11114294B2 (en) 2019-03-08 2021-09-07 Asm Ip Holding B.V. Structure including SiOC layer and method of forming same
US11901175B2 (en) 2019-03-08 2024-02-13 Asm Ip Holding B.V. Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
US11378337B2 (en) 2019-03-28 2022-07-05 Asm Ip Holding B.V. Door opener and substrate processing apparatus provided therewith
US11551925B2 (en) 2019-04-01 2023-01-10 Asm Ip Holding B.V. Method for manufacturing a semiconductor device
US11447864B2 (en) 2019-04-19 2022-09-20 Asm Ip Holding B.V. Layer forming method and apparatus
US11814747B2 (en) 2019-04-24 2023-11-14 Asm Ip Holding B.V. Gas-phase reactor system-with a reaction chamber, a solid precursor source vessel, a gas distribution system, and a flange assembly
US11781221B2 (en) 2019-05-07 2023-10-10 Asm Ip Holding B.V. Chemical source vessel with dip tube
US11289326B2 (en) 2019-05-07 2022-03-29 Asm Ip Holding B.V. Method for reforming amorphous carbon polymer film
US11355338B2 (en) 2019-05-10 2022-06-07 Asm Ip Holding B.V. Method of depositing material onto a surface and structure formed according to the method
US11515188B2 (en) 2019-05-16 2022-11-29 Asm Ip Holding B.V. Wafer boat handling device, vertical batch furnace and method
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
US11345999B2 (en) 2019-06-06 2022-05-31 Asm Ip Holding B.V. Method of using a gas-phase reactor system including analyzing exhausted gas
US11908684B2 (en) 2019-06-11 2024-02-20 Asm Ip Holding B.V. Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method
US11476109B2 (en) 2019-06-11 2022-10-18 Asm Ip Holding B.V. Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
US11746414B2 (en) 2019-07-03 2023-09-05 Asm Ip Holding B.V. Temperature control assembly for substrate processing apparatus and method of using same
US11390945B2 (en) 2019-07-03 2022-07-19 Asm Ip Holding B.V. Temperature control assembly for substrate processing apparatus and method of using same
US11605528B2 (en) 2019-07-09 2023-03-14 Asm Ip Holding B.V. Plasma device using coaxial waveguide, and substrate treatment method
US11664267B2 (en) 2019-07-10 2023-05-30 Asm Ip Holding B.V. Substrate support assembly and substrate processing device including the same
US11664245B2 (en) 2019-07-16 2023-05-30 Asm Ip Holding B.V. Substrate processing device
US11615970B2 (en) 2019-07-17 2023-03-28 Asm Ip Holding B.V. Radical assist ignition plasma system and method
US11688603B2 (en) 2019-07-17 2023-06-27 Asm Ip Holding B.V. Methods of forming silicon germanium structures
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
US11282698B2 (en) 2019-07-19 2022-03-22 Asm Ip Holding B.V. Method of forming topology-controlled amorphous carbon polymer film
US11443926B2 (en) 2019-07-30 2022-09-13 Asm Ip Holding B.V. Substrate processing apparatus
US11430640B2 (en) 2019-07-30 2022-08-30 Asm Ip Holding B.V. Substrate processing apparatus
US11876008B2 (en) 2019-07-31 2024-01-16 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11680839B2 (en) 2019-08-05 2023-06-20 Asm Ip Holding B.V. Liquid level sensor for a chemical source vessel
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
US11639548B2 (en) 2019-08-21 2023-05-02 Asm Ip Holding B.V. Film-forming material mixed-gas forming device and film forming device
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
US11898242B2 (en) 2019-08-23 2024-02-13 Asm Ip Holding B.V. Methods for forming a polycrystalline molybdenum film over a surface of a substrate and related structures including a polycrystalline molybdenum film
US11527400B2 (en) 2019-08-23 2022-12-13 Asm Ip Holding B.V. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
US11827978B2 (en) 2019-08-23 2023-11-28 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
US11495459B2 (en) 2019-09-04 2022-11-08 Asm Ip Holding B.V. Methods for selective deposition using a sacrificial capping layer
US11823876B2 (en) 2019-09-05 2023-11-21 Asm Ip Holding B.V. Substrate processing apparatus
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
US11610774B2 (en) 2019-10-02 2023-03-21 Asm Ip Holding B.V. Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process
US11339476B2 (en) 2019-10-08 2022-05-24 Asm Ip Holding B.V. Substrate processing device having connection plates, substrate processing method
US11735422B2 (en) 2019-10-10 2023-08-22 Asm Ip Holding B.V. Method of forming a photoresist underlayer and structure including same
US11637011B2 (en) 2019-10-16 2023-04-25 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
US11315794B2 (en) 2019-10-21 2022-04-26 Asm Ip Holding B.V. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
US11626316B2 (en) 2019-11-20 2023-04-11 Asm Ip Holding B.V. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
US11401605B2 (en) 2019-11-26 2022-08-02 Asm Ip Holding B.V. Substrate processing apparatus
US11915929B2 (en) 2019-11-26 2024-02-27 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
US11646184B2 (en) 2019-11-29 2023-05-09 Asm Ip Holding B.V. Substrate processing apparatus
US11923181B2 (en) 2019-11-29 2024-03-05 Asm Ip Holding B.V. Substrate processing apparatus for minimizing the effect of a filling gas during substrate processing
US11840761B2 (en) 2019-12-04 2023-12-12 Asm Ip Holding B.V. Substrate processing apparatus
US11885013B2 (en) 2019-12-17 2024-01-30 Asm Ip Holding B.V. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
US11551912B2 (en) 2020-01-20 2023-01-10 Asm Ip Holding B.V. Method of forming thin film and method of modifying surface of thin film
US11521851B2 (en) 2020-02-03 2022-12-06 Asm Ip Holding B.V. Method of forming structures including a vanadium or indium layer
US11828707B2 (en) 2020-02-04 2023-11-28 Asm Ip Holding B.V. Method and apparatus for transmittance measurements of large articles
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
US11837494B2 (en) 2020-03-11 2023-12-05 Asm Ip Holding B.V. Substrate handling device with adjustable joints
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
US11488854B2 (en) 2020-03-11 2022-11-01 Asm Ip Holding B.V. Substrate handling device with adjustable joints
US11823866B2 (en) 2020-04-02 2023-11-21 Asm Ip Holding B.V. Thin film forming method
US11830738B2 (en) 2020-04-03 2023-11-28 Asm Ip Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device
US11437241B2 (en) 2020-04-08 2022-09-06 Asm Ip Holding B.V. Apparatus and methods for selectively etching silicon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
US11530876B2 (en) 2020-04-24 2022-12-20 Asm Ip Holding B.V. Vertical batch furnace assembly comprising a cooling gas supply
US11898243B2 (en) 2020-04-24 2024-02-13 Asm Ip Holding B.V. Method of forming vanadium nitride-containing layer
US11887857B2 (en) 2020-04-24 2024-01-30 Asm Ip Holding B.V. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
US11515187B2 (en) 2020-05-01 2022-11-29 Asm Ip Holding B.V. Fast FOUP swapping with a FOUP handler
US11798830B2 (en) 2020-05-01 2023-10-24 Asm Ip Holding B.V. Fast FOUP swapping with a FOUP handler
US11626308B2 (en) 2020-05-13 2023-04-11 Asm Ip Holding B.V. Laser alignment fixture for a reactor system
US11804364B2 (en) 2020-05-19 2023-10-31 Asm Ip Holding B.V. Substrate processing apparatus
US11705333B2 (en) 2020-05-21 2023-07-18 Asm Ip Holding B.V. Structures including multiple carbon layers and methods of forming and using same
US11767589B2 (en) 2020-05-29 2023-09-26 Asm Ip Holding B.V. Substrate processing device
US11646204B2 (en) 2020-06-24 2023-05-09 Asm Ip Holding B.V. Method for forming a layer provided with silicon
US11658035B2 (en) 2020-06-30 2023-05-23 Asm Ip Holding B.V. Substrate processing method
US11644758B2 (en) 2020-07-17 2023-05-09 Asm Ip Holding B.V. Structures and methods for use in photolithography
US11674220B2 (en) 2020-07-20 2023-06-13 Asm Ip Holding B.V. Method for depositing molybdenum layers using an underlayer
US11725280B2 (en) 2020-08-26 2023-08-15 Asm Ip Holding B.V. Method for forming metal silicon oxide and metal silicon oxynitride layers
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
US11827981B2 (en) 2020-10-14 2023-11-28 Asm Ip Holding B.V. Method of depositing material on stepped structure
US11873557B2 (en) 2020-10-22 2024-01-16 Asm Ip Holding B.V. Method of depositing vanadium metal
US11901179B2 (en) 2020-10-28 2024-02-13 Asm Ip Holding B.V. Method and device for depositing silicon onto substrates
US11891696B2 (en) 2020-11-30 2024-02-06 Asm Ip Holding B.V. Injector configured for arrangement within a reaction chamber of a substrate processing apparatus
US11885020B2 (en) 2020-12-22 2024-01-30 Asm Ip Holding B.V. Transition metal deposition method
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Also Published As

Publication number Publication date
US8338959B2 (en) 2012-12-25
US9184159B2 (en) 2015-11-10
US20110316114A1 (en) 2011-12-29
CN101416278A (en) 2009-04-22
US8030217B2 (en) 2011-10-04
US7732343B2 (en) 2010-06-08
US20130105937A1 (en) 2013-05-02
US20100216307A1 (en) 2010-08-26
CN101416278B (en) 2011-04-06
US7902074B2 (en) 2011-03-08
WO2007117718A3 (en) 2007-11-29
US20070238308A1 (en) 2007-10-11
JP5229588B2 (en) 2013-07-03
EP2011141A2 (en) 2009-01-07
JP2010527138A (en) 2010-08-05
EP2011141B1 (en) 2014-10-29
US20070238299A1 (en) 2007-10-11

Similar Documents

Publication Publication Date Title
US8030217B2 (en) Simplified pitch doubling process flow
JP5719911B2 (en) Method and related structure for isolating a portion of a pitch-multiplied material loop
EP1864320B1 (en) Integrated circuit fabrication
US9412591B2 (en) Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
KR101003897B1 (en) Method of forming pitch multipled contacts
US7666578B2 (en) Efficient pitch multiplication process
US8980756B2 (en) Methods for device fabrication using pitch reduction
KR101368544B1 (en) Simplified pitch doubling process flow
JP5229588B6 (en) Simplified pitch doubling process

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2009504360

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 200780012525.5

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087027277

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2007794840

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07794840

Country of ref document: EP

Kind code of ref document: A2