WO2007109068A2 - Stacked non-volatile memory with silicon-carbige-based amorphous-silicon thin-film transistors and manufacturing method thereof - Google Patents

Stacked non-volatile memory with silicon-carbige-based amorphous-silicon thin-film transistors and manufacturing method thereof Download PDF

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Publication number
WO2007109068A2
WO2007109068A2 PCT/US2007/006468 US2007006468W WO2007109068A2 WO 2007109068 A2 WO2007109068 A2 WO 2007109068A2 US 2007006468 W US2007006468 W US 2007006468W WO 2007109068 A2 WO2007109068 A2 WO 2007109068A2
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layer
memory
channel region
dielectric stack
formed over
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PCT/US2007/006468
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French (fr)
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WO2007109068A3 (en
Inventor
Chandra Mouli
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Micron Technology, Inc.
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Priority to CN200780009375.2A priority Critical patent/CN101405849B/en
Priority to JP2009500464A priority patent/JP5051478B2/en
Publication of WO2007109068A2 publication Critical patent/WO2007109068A2/en
Publication of WO2007109068A3 publication Critical patent/WO2007109068A3/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory device architecture.
  • RAM random-access memory
  • ROM read only memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • flash memory flash memory
  • Flash memory devices have developed into a popular source of non- volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
  • BIOS basic input/output system
  • flash memory devices needs to increase as the performance of computer systems increase. For example, a flash memory transistor that can be erased faster with lower voltages and have longer retention times could increase system performance.
  • Amorphous silicon (a-Si)-based thin film transistors have been used to improve transistor performance.
  • these transistors have undesirable short channel effects and randomness in device characteristics. This is largely due to the randomness in polysilicon grain size and grain boundaries that exist in TFT devices. For example, in sub- 75nm feature sizes, this can result in a very large variation in device characteristics making the stacked cell approach extremely challenging for mass manufacture.
  • Silicon carbide (SiC) substrates have been used in power devices due to the higher bandgap over silicon. Wide bandgap material like SiC substrates have very low intrinsic carrier concentration and thermal generation scales directly with the intrinsic carrier concentration. Therefore, junction leakage currents in SiC substrate devices are very low.
  • SiC substrates suffer numerous problems. For example, wafer sizes in excess of four inches that have high quality and low cost are difficult to achieve. Additionally, the defect densities are unacceptable and the substrates suffer from poor carrier mobility for high speed switching.
  • the present invention encompasses a stacked non-volatile thin film memory device having a memory array comprising a plurality of layers of stacked, thin film memory cells stacked vertically on a substrate.
  • Each memory cell comprises an insulation layer formed over the substrate.
  • a channel region layer is formed over the insulation layer.
  • the channel region layer is comprised of amorphous silicon layer that has a predetermined concentration of carbon.
  • a dielectric stack is formed over the channel region layer.
  • a control gate is formed over the dielectric stack.
  • Figure 1 shows a cross-sectional view of one embodiment of one or more steps in a method for fabrication of a memory device of the present invention.
  • Figure 2 shows a cross-sectional view of one embodiment of one or more steps in the method for fabrication of the memory device of the present invention.
  • Figure 3 shows a cross-sectional view of one embodiment of one or more steps in the method for fabrication of the memory device of the present invention.
  • Figure 4 shows a cross-sectional view of one embodiment of a three dimensional transistor of the present invention.
  • Figure 5 shows a perspective view of a FinFET embodiment of the present invention.
  • Figure 6 shows a cross-sectional view of the embodiment of Figure 5.
  • Figure 7 shows a block diagram of an electronic memory system of the present invention.
  • Figure 8 shows a block diagram of one embodiment of a memory module of the present invention.
  • Figure 1 illustrates a cross-sectional view of one embodiment of one or more steps for fabricating a memory device of the present invention.
  • a substrate 100 undergoes standard CMOS processing for substrate isolation, well implants, and, if needed, threshold voltage adjustments. All periphery logic devices are preferably formed in starting silicon substrate - bulk or SOI.
  • the substrate 100 is a ⁇ -ty ⁇ e substrate with n- wells having p- type regions. Alternate embodiments may use other conductivity types.
  • An insulation layer 102 is formed over the substrate/well 100. In one embodiment, this is an oxide layer 102. Alternate embodiments may use other insulating materials for the insulation layer 102.
  • a silicon carbide (SiC) and/or carbon rich amorphous silicon (a-Si) layer 103 is formed over the insulation layer 102. This film 103 forms the channel region of the memory transistors of the present invention. The carbon concentration in the film 103 is tuned by controlling the Si:C growth temperature. In an alternate embodiment, the SiC thin film is formed by direct deposition to form the channel region. In yet another embodiment, the Si:C is formed after the a-Si deposition.
  • the Si: C is formed on silicon- germanium (a- SiGe) after deposition.
  • the mole fraction of SiGe is tuned along with the Si:C content to optimize carrier mobility.
  • the Si:C thin film is formed on hydrogenated a-Si (a- Si:H).
  • Another embodiment forms the Si:C thin film on deteuritated a-Si (a-Si:D) and/or fiuorinated a-Si (a-Si:F).
  • an optional thin a-Si cap layer (not shown) is deposited on the SiC layer 103.
  • the a-Si cap layer can act as a seed for gate oxidation.
  • this layer may be an oxide layer formed by an atomic layer deposition (ALD) process.
  • Figure 2 illustrates additional fabrication steps of the present invention. This figure shows that the oxide-nitride-oxide (ONO) dielectric stack 200 for each transistor is formed over the SiC channel region layer 103.
  • the ONO dielectric stack 200 is formed for conventional SONOS memory cells.
  • the nitride layer of the ONO dielectric 200 is the charge storage layer or floating gate. Alternate embodiments may use other dielectric stacks depending on the desired cell characteristics.
  • a control gate 205 is formed over the ONO stack 200.
  • the gate 205 can be polysilicon, metal, or some other suitable gate material.
  • the gate 205 is a ⁇ + poly. Alternate embodiments may use n+ poly.
  • a metal gate 205 can include metals such as TiN 5 TaN or some other suitable metal.
  • the spacers 201, 202 are formed adjacent the transistor stack 200, 205.
  • the spacers 201, 202 are an oxide. Alternate embodiments can use other materials.
  • Source and drain regions 210, 211 are formed in the channel region layer 103. In one embodiment, these are n+ doped regions in the SiC layer 103. An alternate embodiment can use p+ regions.
  • the source/drain regions 210, 211 can be formed by conventional implants, solid-source diffusion, plasma doping schemes, or some other suitable method. In another embodiment, the source/drain regions 210, 211 are formed utilizing gate-induced tunneling through Schottky barriers. In such devices, carrier injection is controlled by the modulation of the Schottky barrier width within a fully depleted source extension region.
  • the source/drain region implants are eliminated by forming source/drain contacts to the Si:C thin film using metals and/or suicides with suitable work function to form low Schottky barrier contacts.
  • each source/drain region 210, 211 is determined by the biasing of the transistor.
  • a first region 210 may act like a drain region 210 when it is biased with a positive voltage and the remaining region 211 is a source region when it is at ground potential or left floating.
  • An alternate embodiment can bias these regions 210, 211 such that the functions reverse.
  • a channel forms in the channel region layer 103 between the source/drain regions 210, 211.
  • Metal deposition and pattern steps can be used to form Schottky contacts for the source/drain regions 210, 211.
  • the contacts could be used to gain access to these regions 210, 211 , for example, if they were formed on the top layer of a multiple transistor stack and required contact to interface with external connections and/or other circuits of the integrated circuit.
  • Figure 3 illustrates another set of steps in fabricating the stacked non- volatile memory cells of the present invention.
  • An oxide or other spacer material 300 is formed over the just completed transistor from Figure 2.
  • An oxide or other insulating layer 316 is then formed over this and the above described process is repeated for as many transistor stacks as desired.
  • the illustrated embodiment includes forming the second transistor 301 over the transistor of Figure 2.
  • the second transistor stack is comprised of the SiC or carbon rich silicon layer 315 over the oxide layer 316.
  • the transistor stack 303 comprising the ONO layer 310 and the control gate 311 is formed over the channel region layer 315 and the spacer material 312, 313 is formed on either side of the transistor stack 303.
  • the carbon concentration is decreased in each subsequently formed transistor layer.
  • the lowest transistor layer 330 will experience the greatest thermal budget. Therefore, the lowest layer 330 will have the greatest carbon content.
  • the next layer of transistors 301 will experience somewhat less thermal processing and, thus, has less carbon concentration than the lower layer.
  • the decrease in carbon content continues for each subsequently formed transistor layer.
  • the carbon content can be tailored by changing the interstitial carbon concentration during Si:C growth. Such an embodiment provides a first channel layer with superior short channel effects at the cost of a slight mobility reduction.
  • One embodiment of the above described stacked memory transistors uses 4H-SiC in the SiC layer 103.
  • 4H SiC has a band gap energy of 3.26 eV, thermal conductivity of 3.0 - 3.8 W/cm K at 300K and a breakdown electric field of 2.2 x 10 6 V/cm.
  • Another embodiment uses 6H-SiC that has a band gap energy of 3.03 eV, thermal conductivity of 3.0 — 3.8 W/cm K at 300K and a breakdown electric field of 2.4 x 10 6 V/cm.
  • Figure 4 illustrates a cross-sectional view of one embodiment of a three dimensional transistor in accordance with the thin film channel region layer of the present invention.
  • the transistor is fabricated on an a-Si 400 layer on the substrate.
  • the channel region 420 between the source/drain regions 403, 404 is a U-shaped region 420 that is formed in a thin layer of carbon rich silicon (Si:C).
  • SiC may be used for the channel region layer 401.
  • the ONO dielectric stack 410 fills the U-shaped area.
  • a poly or metal gate 41 1 is formed over the ONO dielectric.
  • the nitride layer of the ONO stack 410 acts as the floating gate or charge storage layer.
  • FIG. 6 illustrates another non-planar embodiment of the present invention.
  • This embodiment is a FinFET memory cell that employs the SiC/Si:C thin film channel region layer of the present invention.
  • the FinFET embodiment is comprised of a substrate 500 that, in one embodiment, is comprised of silicon.
  • Two source/drain regions 501, 502 are formed in a three dimensional manner over the substrate 500.
  • a silicon "fin" 503 is formed between the source/drain regions 501 , 502.
  • a gate 504 is formed over the silicon "fin” 503.
  • the gate can be a poly or metal gate.
  • the gate is shown in dotted lines for purposes of clarity.
  • the "fin” 503 contains the Si:C/SiC channel region of the present invention.
  • the structure of the "fin” 503 is shown in Figure 6 and described subsequently.
  • the percentage of carbon added to the amorphous silicon decreases for each subsequently formed layer of vertically stacked FinFET memory cells.
  • the FinFET of Figure 5 is a double or triple gate transistor.
  • the transistor is a double gate if the gate oxide (601 of Figure 6) between the gate 504 and the "fin" is greater on the sidewalls of the "fin” than the top.
  • the transistor is a triple gate structure if the gate oxide is the same thickness on all three surfaces.
  • Figure 6 shows a cross-sectional view, along axis A-A', of the FinFET embodiment of Figure 5.
  • This view shows the substrate 500 over which the channel region 610, the ONO layer 611, and the Si:C or SiC thin film layer 503 is formed as shown in the three dimensional view of Figure 5.
  • This view additionally shows the gate oxide layer 601 that is formed over the "fin". While Figure 6 shows this layer 601 to be of equal thickness over each surface, as would be the case in a triple gate structure, alternate embodiments can vary the thickness as previously described. For example, for a double gate device, the top surface of the "fin" would not be as thick as the sidewalls.
  • the gate 504 is formed over the gate oxide layer 601.
  • the gate 504 can be comprised of polysilicon, metal, or some other suitable gate material.
  • Figure 7 illustrates a functional block diagram of a memory device 700 that can incorporate the stacked non- volatile memory cells of the present invention.
  • the memory device 700 is coupled to a processor 710.
  • the processor 710 may be a microprocessor or some other type of controlling circuitry.
  • the memory device 700 and the processor 710 form part of an electronic memory system 720.
  • the memory device 700 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
  • the memory device includes an array of non- volatile memory cells 730 that can be floating gate flash memory cells.
  • the memory array 730 is arranged in banks of rows and columns.
  • the control gates of each row of memory cells is coupled with a word line while the drain regions of the memory cells are coupled to bit lines.
  • the source regions of the memory cells are coupled to source lines.
  • the connection of the cells to the bit lines and source lines depends on whether the array is a NAND architecture, a NOR architecture, an AND architecture or some other memory array architecture.
  • the stacked nonvolatile memory cells of the present invention can operate in any memory array architecture.
  • An address buffer circuit 740 is provided to latch address signals provided on address input connections AO-Ax 742. Address signals are received and decoded by a row decoder 744 and a column decoder 746 to access the memory array 730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 730. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
  • the memory integrated circuit 700 reads data in the memory array 730 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 750.
  • the sense/buffer circuitry in one embodiment, is coupled to read and latch a row of data from the memory array 730.
  • Data input and output buffer circuitry 760 is included for bi-directional data communication over a plurality of data connections 762 with the controller 710.
  • Write circuitry 755 is provided to write data to the memory array.
  • Control circuitry 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write, and erase operations.
  • the control circuitry 770 may be a state machine, a sequencer, or some other type of controller.
  • Non-volatile memory device illustrated in Figure 7 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
  • FIG 8 is an illustration of an exemplary memory module 800.
  • Memory module 800 is illustrated as a memory card, although the concepts discussed with reference to memory module 800 are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of "memory module" as used herein.
  • memory module e.g., USB flash drives
  • memory module 800 will include a housing 805 (as depicted) to enclose one or more memory devices 810, though such a housing is not essential to all devices or device applications. At least one memory device 810 is a non- volatile memory [including or adapted to perform elements of the invention].
  • the housing 805 includes one or more contacts 815 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like.
  • the contacts 815 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 815 might be in the form of a USB Type- A male connector.
  • the contacts 815 are in the form of a semi-proprietary interface, such as might be found on COMPACTFLASH memory cards licensed by SANDISK Corporation, MEMORYSTICK memory cards licensed by SONY Corporation, SD SECURE DIGITAL memory cards licensed by TOSHIBA Corporation and the like. In general, however, contacts 815 provide an interface for passing control, address and/or data signals between the memory module 800 and a host having compatible receptors for the contacts 815.
  • the memory module 800 may optionally include additional circuitry 820 which may be one or more integrated circuits and/or discrete components.
  • the additional circuitry 820 may include a memory controller for controlling access across multiple memory devices 810 and/or for providing a translation layer between an external host and a memory device 810.
  • a memory controller could selectively couple an I/O connection (not shown in Figure 8) of a memory device 810 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 815 at the appropriate time.
  • the communication protocol between a host and the memory module 800 may be different than what is required for access of a memory device 810.
  • a memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 810. Such translation may further include changes in signal voltage levels in addition to command sequences.
  • the additional circuitry 820 may further include functionality unrelated to control of a memory device 810 such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry 820 may include circuitry to restrict read or write access to the memory module 800, such as password protection, biometrics or the like. The additional circuitry 820 may include circuitry to indicate a status of the memory module 800. For example, the additional circuitry 820 may include functionality to determine whether power is being supplied to the memory module 800 and whether the memory module 800 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 820 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 800. CONCLUSION
  • the non- volatile memory transistors of the present invention are fabricated on a silicon carbide or carbon rich silicon channel thin film. This provides reduced tunnel barrier and ease of erase with lower voltages and electric fields.
  • the cells of the present invention are stackable in order to greatly increase the density of a memory device.
  • the non- volatile memory cells of the present invention may be NAND-type cells, NOR-type cells, or any other type of non- volatile memory array architecture.

Abstract

A stacked non-volatile memory device uses amorphous silicon based thin film transistors (301) stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer (315) having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack (310) is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate (311) is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer. The thin film transistor can be a FinFET.

Description

STACKED NON- VOLATILE MEMORY WITH SILICON CARBIDE-BASED AMORPHOUS SILICON THIN FILM TRANSISTORS
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory device architecture.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non- volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
The performance of flash memory devices needs to increase as the performance of computer systems increase. For example, a flash memory transistor that can be erased faster with lower voltages and have longer retention times could increase system performance.
Amorphous silicon (a-Si)-based thin film transistors (TFT) have been used to improve transistor performance. However, these transistors have undesirable short channel effects and randomness in device characteristics. This is largely due to the randomness in polysilicon grain size and grain boundaries that exist in TFT devices. For example, in sub- 75nm feature sizes, this can result in a very large variation in device characteristics making the stacked cell approach extremely challenging for mass manufacture. Silicon carbide (SiC) substrates have been used in power devices due to the higher bandgap over silicon. Wide bandgap material like SiC substrates have very low intrinsic carrier concentration and thermal generation scales directly with the intrinsic carrier concentration. Therefore, junction leakage currents in SiC substrate devices are very low.
However, SiC substrates suffer numerous problems. For example, wafer sizes in excess of four inches that have high quality and low cost are difficult to achieve. Additionally, the defect densities are unacceptable and the substrates suffer from poor carrier mobility for high speed switching.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a higher performance flash memory transistor that does not have serious scaling issues.
SUMMARY
The above-mentioned problems with non-volatile memory performance and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The present invention encompasses a stacked non-volatile thin film memory device having a memory array comprising a plurality of layers of stacked, thin film memory cells stacked vertically on a substrate. Each memory cell comprises an insulation layer formed over the substrate. A channel region layer is formed over the insulation layer. The channel region layer is comprised of amorphous silicon layer that has a predetermined concentration of carbon. A dielectric stack is formed over the channel region layer. A control gate is formed over the dielectric stack.
Further embodiments of the invention include methods and apparatus of varying scope.
BRIEF DESCRIPTION OFTHE DRAWINGS
Figure 1 shows a cross-sectional view of one embodiment of one or more steps in a method for fabrication of a memory device of the present invention.
Figure 2 shows a cross-sectional view of one embodiment of one or more steps in the method for fabrication of the memory device of the present invention. Figure 3 shows a cross-sectional view of one embodiment of one or more steps in the method for fabrication of the memory device of the present invention.
Figure 4 shows a cross-sectional view of one embodiment of a three dimensional transistor of the present invention. Figure 5 shows a perspective view of a FinFET embodiment of the present invention.
Figure 6 shows a cross-sectional view of the embodiment of Figure 5.
Figure 7 shows a block diagram of an electronic memory system of the present invention. Figure 8 shows a block diagram of one embodiment of a memory module of the present invention.
DETAILED DESCRIPTION
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including bulk silicon, silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, silicon-on-nothing, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims and equivalents thereof. Figure 1 illustrates a cross-sectional view of one embodiment of one or more steps for fabricating a memory device of the present invention. A substrate 100 undergoes standard CMOS processing for substrate isolation, well implants, and, if needed, threshold voltage adjustments. All periphery logic devices are preferably formed in starting silicon substrate - bulk or SOI.
In one embodiment, the substrate 100 is a ρ-tyρe substrate with n- wells having p- type regions. Alternate embodiments may use other conductivity types.
The periphery regions are covered and hard mask and lithography steps used to open up the memory array. An insulation layer 102 is formed over the substrate/well 100. In one embodiment, this is an oxide layer 102. Alternate embodiments may use other insulating materials for the insulation layer 102. A silicon carbide (SiC) and/or carbon rich amorphous silicon (a-Si) layer 103 is formed over the insulation layer 102. This film 103 forms the channel region of the memory transistors of the present invention. The carbon concentration in the film 103 is tuned by controlling the Si:C growth temperature. In an alternate embodiment, the SiC thin film is formed by direct deposition to form the channel region. In yet another embodiment, the Si:C is formed after the a-Si deposition.
In still another alternate embodiment, the Si: C is formed on silicon- germanium (a- SiGe) after deposition. In one version of this embodiment, the mole fraction of SiGe is tuned along with the Si:C content to optimize carrier mobility.
In yet another embodiment, the Si:C thin film is formed on hydrogenated a-Si (a- Si:H). Another embodiment forms the Si:C thin film on deteuritated a-Si (a-Si:D) and/or fiuorinated a-Si (a-Si:F).
In one embodiment, an optional thin a-Si cap layer (not shown) is deposited on the SiC layer 103. The a-Si cap layer can act as a seed for gate oxidation. In another embodiment, this layer may be an oxide layer formed by an atomic layer deposition (ALD) process. Figure 2 illustrates additional fabrication steps of the present invention. This figure shows that the oxide-nitride-oxide (ONO) dielectric stack 200 for each transistor is formed over the SiC channel region layer 103. The ONO dielectric stack 200 is formed for conventional SONOS memory cells. The nitride layer of the ONO dielectric 200 is the charge storage layer or floating gate. Alternate embodiments may use other dielectric stacks depending on the desired cell characteristics. For example, AI2O3, Hfθ2, LaOs, LaAlC>3, and other suitable high dielectric constant (high-k) materials can be substituted for the nitride film. In another embodiment, the dielectric stack may have a graded stoichiometry, forming a "crested barrier" structure. A control gate 205 is formed over the ONO stack 200. The gate 205 can be polysilicon, metal, or some other suitable gate material. In one embodiment, the gate 205 is a ρ+ poly. Alternate embodiments may use n+ poly. A metal gate 205 can include metals such as TiN5 TaN or some other suitable metal.
The spacers 201, 202 are formed adjacent the transistor stack 200, 205. In one embodiment, the spacers 201, 202 are an oxide. Alternate embodiments can use other materials.
Source and drain regions 210, 211 are formed in the channel region layer 103. In one embodiment, these are n+ doped regions in the SiC layer 103. An alternate embodiment can use p+ regions. The source/drain regions 210, 211 can be formed by conventional implants, solid-source diffusion, plasma doping schemes, or some other suitable method. In another embodiment, the source/drain regions 210, 211 are formed utilizing gate-induced tunneling through Schottky barriers. In such devices, carrier injection is controlled by the modulation of the Schottky barrier width within a fully depleted source extension region.
In an alternate embodiment, the source/drain region implants are eliminated by forming source/drain contacts to the Si:C thin film using metals and/or suicides with suitable work function to form low Schottky barrier contacts.
The function of each source/drain region 210, 211 is determined by the biasing of the transistor. For example, a first region 210 may act like a drain region 210 when it is biased with a positive voltage and the remaining region 211 is a source region when it is at ground potential or left floating. An alternate embodiment can bias these regions 210, 211 such that the functions reverse. During transistor operation, a channel forms in the channel region layer 103 between the source/drain regions 210, 211.
Metal deposition and pattern steps can be used to form Schottky contacts for the source/drain regions 210, 211. The contacts could be used to gain access to these regions 210, 211 , for example, if they were formed on the top layer of a multiple transistor stack and required contact to interface with external connections and/or other circuits of the integrated circuit.
Figure 3 illustrates another set of steps in fabricating the stacked non- volatile memory cells of the present invention. An oxide or other spacer material 300 is formed over the just completed transistor from Figure 2. An oxide or other insulating layer 316 is then formed over this and the above described process is repeated for as many transistor stacks as desired.
The illustrated embodiment includes forming the second transistor 301 over the transistor of Figure 2. The second transistor stack is comprised of the SiC or carbon rich silicon layer 315 over the oxide layer 316. The source/drain regions 320, 321 formed in the
SiC channel region layer 315. The transistor stack 303 comprising the ONO layer 310 and the control gate 311 is formed over the channel region layer 315 and the spacer material 312, 313 is formed on either side of the transistor stack 303.
In one embodiment, the carbon concentration is decreased in each subsequently formed transistor layer. In other words, the lowest transistor layer 330 will experience the greatest thermal budget. Therefore, the lowest layer 330 will have the greatest carbon content. The next layer of transistors 301 will experience somewhat less thermal processing and, thus, has less carbon concentration than the lower layer. The decrease in carbon content continues for each subsequently formed transistor layer. The carbon content can be tailored by changing the interstitial carbon concentration during Si:C growth. Such an embodiment provides a first channel layer with superior short channel effects at the cost of a slight mobility reduction.
One embodiment of the above described stacked memory transistors uses 4H-SiC in the SiC layer 103. 4H SiC has a band gap energy of 3.26 eV, thermal conductivity of 3.0 - 3.8 W/cm K at 300K and a breakdown electric field of 2.2 x 106 V/cm. Another embodiment uses 6H-SiC that has a band gap energy of 3.03 eV, thermal conductivity of 3.0 — 3.8 W/cm K at 300K and a breakdown electric field of 2.4 x 106 V/cm. These properties make it clear that SiC is an excellent material compared to silicon due to its very low leakage, high temperature operating characteristics, sustaining high electric fields, and excellent heat dissipation. Figure 4 illustrates a cross-sectional view of one embodiment of a three dimensional transistor in accordance with the thin film channel region layer of the present invention. The transistor is fabricated on an a-Si 400 layer on the substrate. The channel region 420 between the source/drain regions 403, 404 is a U-shaped region 420 that is formed in a thin layer of carbon rich silicon (Si:C). In an alternate embodiment, SiC may be used for the channel region layer 401. The ONO dielectric stack 410 fills the U-shaped area. A poly or metal gate 41 1 is formed over the ONO dielectric. As in previous embodiments, the nitride layer of the ONO stack 410 acts as the floating gate or charge storage layer.
The fabrication of the embodiment of Figure 4 can be repeated multiple times to form a transistor stack of such non-planar transistors. This process has been discussed previously. The various alternate embodiments in fabrication and materials discussed previously can also be employed in these non-planar transistors.
Figure 6 illustrates another non-planar embodiment of the present invention. This embodiment is a FinFET memory cell that employs the SiC/Si:C thin film channel region layer of the present invention. The FinFET embodiment is comprised of a substrate 500 that, in one embodiment, is comprised of silicon. Two source/drain regions 501, 502 are formed in a three dimensional manner over the substrate 500. A silicon "fin" 503 is formed between the source/drain regions 501 , 502. A gate 504 is formed over the silicon "fin" 503. The gate can be a poly or metal gate. The gate is shown in dotted lines for purposes of clarity. The "fin" 503 contains the Si:C/SiC channel region of the present invention. The structure of the "fin" 503 is shown in Figure 6 and described subsequently. The percentage of carbon added to the amorphous silicon decreases for each subsequently formed layer of vertically stacked FinFET memory cells.
The FinFET of Figure 5 is a double or triple gate transistor. The transistor is a double gate if the gate oxide (601 of Figure 6) between the gate 504 and the "fin" is greater on the sidewalls of the "fin" than the top. The transistor is a triple gate structure if the gate oxide is the same thickness on all three surfaces.
Figure 6 shows a cross-sectional view, along axis A-A', of the FinFET embodiment of Figure 5. This view shows the substrate 500 over which the channel region 610, the ONO layer 611, and the Si:C or SiC thin film layer 503 is formed as shown in the three dimensional view of Figure 5. This view additionally shows the gate oxide layer 601 that is formed over the "fin". While Figure 6 shows this layer 601 to be of equal thickness over each surface, as would be the case in a triple gate structure, alternate embodiments can vary the thickness as previously described. For example, for a double gate device, the top surface of the "fin" would not be as thick as the sidewalls.
The gate 504 is formed over the gate oxide layer 601. The gate 504 can be comprised of polysilicon, metal, or some other suitable gate material.
The fabrication of the embodiment of Figures 5 and 6 can be repeated multiple times to form a three dimensional transistor stack, as illustrated in the embodiment of Figure 3, of such non-planar transistors. This process has been discussed previously. The various alternate embodiments in fabrication and materials discussed previously can also be employed in these non-planar transistors.
Figure 7 illustrates a functional block diagram of a memory device 700 that can incorporate the stacked non- volatile memory cells of the present invention. The memory device 700 is coupled to a processor 710. The processor 710 may be a microprocessor or some other type of controlling circuitry. The memory device 700 and the processor 710 form part of an electronic memory system 720. The memory device 700 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
The memory device includes an array of non- volatile memory cells 730 that can be floating gate flash memory cells. The memory array 730 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain regions of the memory cells are coupled to bit lines. The source regions of the memory cells are coupled to source lines. As is well known in the art, the connection of the cells to the bit lines and source lines depends on whether the array is a NAND architecture, a NOR architecture, an AND architecture or some other memory array architecture. The stacked nonvolatile memory cells of the present invention can operate in any memory array architecture.
An address buffer circuit 740 is provided to latch address signals provided on address input connections AO-Ax 742. Address signals are received and decoded by a row decoder 744 and a column decoder 746 to access the memory array 730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 730. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
The memory integrated circuit 700 reads data in the memory array 730 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 750. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 730. Data input and output buffer circuitry 760 is included for bi-directional data communication over a plurality of data connections 762 with the controller 710. Write circuitry 755 is provided to write data to the memory array.
Control circuitry 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write, and erase operations. The control circuitry 770 may be a state machine, a sequencer, or some other type of controller.
The non-volatile memory device illustrated in Figure 7 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
Figure 8 is an illustration of an exemplary memory module 800. Memory module 800 is illustrated as a memory card, although the concepts discussed with reference to memory module 800 are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of "memory module" as used herein. In addition, although one example form factor is depicted in Figure 8, these concepts are applicable to other form factors as well.
In some embodiments, memory module 800 will include a housing 805 (as depicted) to enclose one or more memory devices 810, though such a housing is not essential to all devices or device applications. At least one memory device 810 is a non- volatile memory [including or adapted to perform elements of the invention]. Where present, the housing 805 includes one or more contacts 815 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts 815 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 815 might be in the form of a USB Type- A male connector. For some embodiments, the contacts 815 are in the form of a semi-proprietary interface, such as might be found on COMPACTFLASH memory cards licensed by SANDISK Corporation, MEMORYSTICK memory cards licensed by SONY Corporation, SD SECURE DIGITAL memory cards licensed by TOSHIBA Corporation and the like. In general, however, contacts 815 provide an interface for passing control, address and/or data signals between the memory module 800 and a host having compatible receptors for the contacts 815.
The memory module 800 may optionally include additional circuitry 820 which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry 820 may include a memory controller for controlling access across multiple memory devices 810 and/or for providing a translation layer between an external host and a memory device 810. For example, there may not be a one-to-one correspondence between the number of contacts 815 and a number of I/O connections to the one or more memory devices 810. Thus, a memory controller could selectively couple an I/O connection (not shown in Figure 8) of a memory device 810 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 815 at the appropriate time. Similarly, the communication protocol between a host and the memory module 800 may be different than what is required for access of a memory device 810. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 810. Such translation may further include changes in signal voltage levels in addition to command sequences.
The additional circuitry 820 may further include functionality unrelated to control of a memory device 810 such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry 820 may include circuitry to restrict read or write access to the memory module 800, such as password protection, biometrics or the like. The additional circuitry 820 may include circuitry to indicate a status of the memory module 800. For example, the additional circuitry 820 may include functionality to determine whether power is being supplied to the memory module 800 and whether the memory module 800 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 820 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 800. CONCLUSION
In summary, the non- volatile memory transistors of the present invention are fabricated on a silicon carbide or carbon rich silicon channel thin film. This provides reduced tunnel barrier and ease of erase with lower voltages and electric fields. The cells of the present invention are stackable in order to greatly increase the density of a memory device.
The non- volatile memory cells of the present invention may be NAND-type cells, NOR-type cells, or any other type of non- volatile memory array architecture.
Although specific embodiments have been illustrated and described herein,- it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims

What is claimed is:
1. A stacked non-volatile thin film memory device comprising: a plurality of thin film memory cells stacked vertically on a substrate, each memory cell comprising: an insulation layer formed over the substrate; a channel region layer formed over the insulation layer, the channel region layer comprising amorphous silicon layer having a predetermined concentration of carbon; a dielectric stack formed over the channel region layer; and a control gate formed over the dielectric stack.
2. The device of claim 1 wherein the control gate is comprised of one of polysilicon or metal.
3. The device of claim 2 wherein the metal is one of TiN or TaN.
4. The device of claim 1 wherein the insulation layer is an oxide layer.
5. The device of claim 1 and further including an insulation material formed vertically between each memory cell.
6. The device of claim 1 wherein the predetermined concentration of carbon is such that the amorphous silicon layer is a silicon carbide layer.
7. The device of claim 1 and further including a pair of source/drain regions formed in the channel region layer on either side of the dielectric stack.
8. A stacked non-volatile thin film memory device comprising: a plurality of thin film memory cells stacked vertically on a silicon substrate, each memory cell layer comprising: an oxide layer formed over the substrate; an amorphous silicon layer formed over the oxide layer and having a predetermined concentration of carbon; a dielectric stack formed over the channel region layer; a pair of source/drain regions formed in the amorphous silicon layer on opposing sides of the dielectric stack; and a control gate formed over the dielectric stack.
9. The device of claim 8 wherein the non-volatile thin film memory device is a flash memory device.
10. The device of claim 8 wherein the predetermined concentration of carbon decreases with each layer of memory cells.
11. The device of claim 8 wherein the dielectric stack comprises an oxide-nitride-oxide structure.
12. The device of claim 8 and further including spacer material formed on opposing sides of the dielectric stack.
13. The device of claim 8 and further including a metal contact formed on each source/drain region in a top layer of the plurality of stack memory cells.
14. A method for fabricating a non- volatile memory device comprising a plurality of layers of vertically stacked thin film memory cells over a substrate, the method for fabricating each layer comprising: forming an insulation layer; forming an amorphous silicon film over the insulation layer; increasing a carbon content in the amorphous silicon film to form a carbon rich silicon film; forming a dielectric stack over the amorphous silicon layer; and forming a control gate over the dielectric stack.
15. The method of claim 14 wherein forming the dielectric layer comprises forming an oxide-nitride-oxide layer.
16. The method of claim 14 wherein forming the dielectric layer comprises forming an oxide-high-k dielectric-oxide layer.
17. The method of claim 16 wherein the high-k dielectric comprises one of AI2O3, HfO2, LaC»3, or LaAlθ3.
18. The method of claim 14 wherein forming the control gate comprises forming a metal layer over the dielectric stack.
19. The method of claim 18 wherein the metal layer is comprised of one of TiN or TaN.
20. The method of claim 14 and further including forming spacers on opposing sides of the dielectric stack.
21. The method of claim 14 wherein increasing the carbon content comprises tuning the carbon concentration by controlling Si:C growth temperature.
22. The method of claim 14 and further including forming an amorphous silicon cap layer between the carbon rich silicon film and the dielectric stack.
23. The method of claim 14 wherein increasing the carbon content comprises increasing the carbon content of the amorphous silicon film such that a lowest layer has a greater carbon content than a higher layer.
24. The method of claim 14 wherein increasing the carbon content comprises introducing less carbon in the amorphous silicon film of each layer as the layers increase.
25. The method of claim 14 and further including forming source/drain regions on opposing sides of the dielectric stack in the carbon rich film.
26. The method of claim 25 wherein the source/drain regions are formed by one of implantation, solid-source diffusion, or plasma doping.
27. The method of claim 14 and further including forming source/drain contacts on the . carbon rich silicon film with metal low Schottky barrier contacts.
28. The method of claim 14 and further including forming source/drain contacts in the carbon rich silicon film by gate-induced tunneling through Schottky barriers.
29. The method of claim 14 wherein the dielectric stack is comprised of graded stoichiometry.
30. The method of claim 14 and further including forming an oxide layer between each layer of thin film memory cells.
31. The method of claim 14 wherein the carbon rich silicon film comprises a channel region and the channel region is "U" shaped.
32. A stacked non-volatile thin film memory device comprising: a plurality of thin film FinFET memory cells stacked vertically on a substrate, each memory cell layer comprising: a pair of source/drain regions formed vertically on the substrate; a channel region formed vertically over the substrate and between the pair of vertical source/drain regions, the channel region layer comprising amorphous silicon having a predetermined concentration of carbon; a dielectric stack formed around the channel region; and a control gate formed around the dielectric stack.
33. The device of claim 32 and further including an oxide layer formed between the dielectric stack and the control gate.
34. The device of claim 32 wherein the control gate is formed as a double gate structure.
35. The device of claim 32 wherein the control gate is formed as a triple gate structure.
36. The device of claim 33 wherein a thickness of the oxide layer determines whether the control gate is a double control gate or a triple control gate.
37. The device of claim 36 wherein the oxide layer on the top of the channel region is thinner than the sidewalls for the double control gate.
38. The device of claim 36 wherein the oxide layer is substantially of equal thickness for the triple control gate.
39. A method for fabricating a stacked non-volatile thin film memory device, the method comprising: forming a plurality of thin film FinFET memory cell layers stacked vertically on a substrate, the method for forming each memory cell layer comprising: forming a pair of source/drain regions vertically on the substrate; forming a channel region of amorphous silicon film vertically over the substrate and between the pair of vertical source/drain regions; increasing a carbon content in the amorphous silicon film to form a carbon rich, silicon film; forming a dielectric stack around the channel region; and forming a control gate around the dielectric stack.
40. The method of claim 39 wherein increasing the carbon content comprises increasing the carbon content at a lesser percentage for each subsequently formed vertically stacked thin film FinFET memory cell layer.
41. An memory system comprising: a processor that generates control signals; and a memory device coupled to the processor, the device having a memory array comprising a plurality of layers of thin film memory cells formed over a substrate, each layer comprising: an insulation layer formed over the substrate; a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon; a dielectric stack formed over the channel region layer; and a control gate formed over the dielectric stack.
42. The system of claim 41 and further including a pair of source/drain regions formed in the channel region layer on opposing sides of the dielectric stack.
43. The system of claim 41 wherein the predetermined concentration of carbon decreases in each subsequently formed layer of thin film memory cells.
44. The system of claim 41 wherein the memory array is comprised of a NAND-type architecture.
45. The system of claim 41 wherein the memory array is comprised of a NOR-type architecture.
46. A memory module comprising: at least two memory devices, each comprising a memory array having a plurality of layers of thin film memory cells formed over a substrate, each layer comprising: an insulation layer formed over the substrate; a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon; a dielectric stack formed over the channel region layer; and a control gate formed over the dielectric stack; and a plurality of contacts configured to provide selective contact between the memory array and a host system.
47. The module of claim 46 and further including a memory controller coupled to the memory array for controlling operation of the memory device in response to the host system.
48. A memory module comprising: a memory device comprising a memory array having a plurality of layers of thin film memory cells formed over a substrate, each layer comprising: an insulation layer formed over the substrate; a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon; a dielectric stack formed over the channel region layer; and a control gate formed over the dielectric stack; a housing for enclosing the memory device; and a plurality of contacts coupled to the housing and configured to provide selective contact between the memory array and a host system.
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