WO2007087270A3 - Processor having a data mover engine that associates register addresses with memory addresses - Google Patents

Processor having a data mover engine that associates register addresses with memory addresses Download PDF

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Publication number
WO2007087270A3
WO2007087270A3 PCT/US2007/001702 US2007001702W WO2007087270A3 WO 2007087270 A3 WO2007087270 A3 WO 2007087270A3 US 2007001702 W US2007001702 W US 2007001702W WO 2007087270 A3 WO2007087270 A3 WO 2007087270A3
Authority
WO
WIPO (PCT)
Prior art keywords
addresses
tie
instructions
processor
data
Prior art date
Application number
PCT/US2007/001702
Other languages
French (fr)
Other versions
WO2007087270A2 (en
Inventor
Karagada Ramarao Kishore
Kevin D Kissell
Radhika Thekkath
Vidya Rajagopalan
Georgi Zlatkov Beloev
Original Assignee
Mips Tech Inc
Karagada Ramarao Kishore
Kevin D Kissell
Radhika Thekkath
Vidya Rajagopalan
Georgi Zlatkov Beloev
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/336,938 external-priority patent/US7721075B2/en
Priority claimed from US11/336,923 external-priority patent/US7721073B2/en
Priority claimed from US11/336,937 external-priority patent/US7721074B2/en
Application filed by Mips Tech Inc, Karagada Ramarao Kishore, Kevin D Kissell, Radhika Thekkath, Vidya Rajagopalan, Georgi Zlatkov Beloev filed Critical Mips Tech Inc
Publication of WO2007087270A2 publication Critical patent/WO2007087270A2/en
Publication of WO2007087270A3 publication Critical patent/WO2007087270A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Abstract

A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.
PCT/US2007/001702 2006-01-23 2007-01-22 Processor having a data mover engine that associates register addresses with memory addresses WO2007087270A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/336,938 US7721075B2 (en) 2006-01-23 2006-01-23 Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
US11/336,937 2006-01-23
US11/336,923 2006-01-23
US11/336,923 US7721073B2 (en) 2006-01-23 2006-01-23 Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses
US11/336,937 US7721074B2 (en) 2006-01-23 2006-01-23 Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses
US11/336,938 2006-01-23

Publications (2)

Publication Number Publication Date
WO2007087270A2 WO2007087270A2 (en) 2007-08-02
WO2007087270A3 true WO2007087270A3 (en) 2007-12-27

Family

ID=38057879

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/001702 WO2007087270A2 (en) 2006-01-23 2007-01-22 Processor having a data mover engine that associates register addresses with memory addresses

Country Status (1)

Country Link
WO (1) WO2007087270A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10346558B2 (en) 2017-06-22 2019-07-09 International Business Machines Corporation Integrated circuit buffering solutions considering sink delays

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067601A (en) * 1997-11-03 2000-05-23 Brecis Communications Cache memory based instruction execution
US6178182B1 (en) * 1996-08-29 2001-01-23 Siemens Aktiengesellschaft Method and communication system for the transmission of compressed voice information in a communication network

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6178182B1 (en) * 1996-08-29 2001-01-23 Siemens Aktiengesellschaft Method and communication system for the transmission of compressed voice information in a communication network
US6067601A (en) * 1997-11-03 2000-05-23 Brecis Communications Cache memory based instruction execution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
POSTIFF M ET AL: "The store-load address table and speculative register promotion", MICRO-33. PROCEEDINGS OF THE 33RD. ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE. MONTEREY, CA, DEC. 10 - 13, 2000, PROCEEDINGS OF THE ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, LOS ALAMITOS, CA : IEEE COMP. SOC, US, 10 December 2000 (2000-12-10), pages 235 - 244, XP010528891, ISBN: 0-7695-0924-X *

Also Published As

Publication number Publication date
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