WO2006118982A3 - Semiconductor substrate with exposed upper and lower sides - Google Patents

Semiconductor substrate with exposed upper and lower sides Download PDF

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Publication number
WO2006118982A3
WO2006118982A3 PCT/US2006/016143 US2006016143W WO2006118982A3 WO 2006118982 A3 WO2006118982 A3 WO 2006118982A3 US 2006016143 W US2006016143 W US 2006016143W WO 2006118982 A3 WO2006118982 A3 WO 2006118982A3
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WO
WIPO (PCT)
Prior art keywords
substrate
package
land
assembly
substrates
Prior art date
Application number
PCT/US2006/016143
Other languages
French (fr)
Other versions
WO2006118982A2 (en
Inventor
Marcos Karnezos
Flynn Carson
Original Assignee
Stats Chippac Ltd
Marcos Karnezos
Flynn Carson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd, Marcos Karnezos, Flynn Carson filed Critical Stats Chippac Ltd
Priority to JP2008509150A priority Critical patent/JP4503677B2/en
Priority to KR1020077027669A priority patent/KR101120122B1/en
Publication of WO2006118982A2 publication Critical patent/WO2006118982A2/en
Publication of WO2006118982A3 publication Critical patent/WO2006118982A3/en

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Abstract

Semiconductor package assemblies include a package subassembly, having at least one die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second ('land') side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the 'land' sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wir bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. Also, methods for making such package assemblies include steps of providing a substrate, preferably as a strip of ball grid array (BGA) or land grid array (LGA) substrates.
PCT/US2006/016143 2005-04-29 2006-04-27 Semiconductor substrate with exposed upper and lower sides WO2006118982A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008509150A JP4503677B2 (en) 2005-04-29 2006-04-27 Semiconductor package with upper and lower substrate surfaces exposed
KR1020077027669A KR101120122B1 (en) 2005-04-29 2006-04-27 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US59471105P 2005-04-29 2005-04-29
US60/594,711 2005-04-29
US69284205P 2005-06-20 2005-06-20
US60/692,842 2005-06-20
US11/394,635 2006-03-31
US11/394,635 US7429786B2 (en) 2005-04-29 2006-03-31 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides

Publications (2)

Publication Number Publication Date
WO2006118982A2 WO2006118982A2 (en) 2006-11-09
WO2006118982A3 true WO2006118982A3 (en) 2007-07-12

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JP (1) JP4503677B2 (en)
KR (1) KR101120122B1 (en)
TW (1) TWI322489B (en)
WO (1) WO2006118982A2 (en)

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