WO2006102667A3 - Enforcing strongly-ordered requests in a weakly-ordered processing system - Google Patents

Enforcing strongly-ordered requests in a weakly-ordered processing system Download PDF

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Publication number
WO2006102667A3
WO2006102667A3 PCT/US2006/011174 US2006011174W WO2006102667A3 WO 2006102667 A3 WO2006102667 A3 WO 2006102667A3 US 2006011174 W US2006011174 W US 2006011174W WO 2006102667 A3 WO2006102667 A3 WO 2006102667A3
Authority
WO
WIPO (PCT)
Prior art keywords
ordered
processing system
weakly
access requests
strongly
Prior art date
Application number
PCT/US2006/011174
Other languages
French (fr)
Other versions
WO2006102667A2 (en
Inventor
Richard Gerard Hofmann
Thomas Andrew Sartorius
Thomas Philip Speier
Jaya Prakash Subramani Ganasan
James Norris Dieffenderfer
James Edward Sullivan
Original Assignee
Qualcomm Inc
Richard Gerard Hofmann
Thomas Andrew Sartorius
Thomas Philip Speier
Jaya Prakash Subramani Ganasan
James Norris Dieffenderfer
James Edward Sullivan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Jaya Prakash Subramani Ganasan, James Norris Dieffenderfer, James Edward Sullivan filed Critical Qualcomm Inc
Priority to CN2006800166617A priority Critical patent/CN101176083B/en
Priority to CA2601639A priority patent/CA2601639C/en
Priority to EP06739776.0A priority patent/EP1861786B1/en
Priority to JP2008503288A priority patent/JP4824748B2/en
Priority to KR1020077024336A priority patent/KR101185623B1/en
Publication of WO2006102667A2 publication Critical patent/WO2006102667A2/en
Publication of WO2006102667A3 publication Critical patent/WO2006102667A3/en
Priority to IL186001A priority patent/IL186001A/en
Priority to HK08109405.2A priority patent/HK1114201A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead

Abstract

The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
PCT/US2006/011174 2005-03-23 2006-03-23 Enforcing strongly-ordered requests in a weakly-ordered processing system WO2006102667A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN2006800166617A CN101176083B (en) 2005-03-23 2006-03-23 Enforcing strongly-ordered requests in a weakly-ordered processing system
CA2601639A CA2601639C (en) 2005-03-23 2006-03-23 Enforcing strongly-ordered requests in a weakly-ordered processing system
EP06739776.0A EP1861786B1 (en) 2005-03-23 2006-03-23 Enforcing strongly-ordered requests in a weakly-ordered processing system
JP2008503288A JP4824748B2 (en) 2005-03-23 2006-03-23 Enforcing strongly ordered requests in weakly ordered processing systems
KR1020077024336A KR101185623B1 (en) 2005-03-23 2006-03-23 Enforcing strongly ordered requests in a weakly-ordered processing system
IL186001A IL186001A (en) 2005-03-23 2007-09-17 Enforcing strongly-ordered requests in a weakly-ordered processing system
HK08109405.2A HK1114201A1 (en) 2005-03-23 2008-08-25 Bus interconnect, weakly-ordered processing system and method for enforcing strongly-ordered requests in a weakly-ordered processing system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US66474905P 2005-03-23 2005-03-23
US60/664,749 2005-03-23
US11/253,307 2005-10-19
US11/253,307 US9026744B2 (en) 2005-03-23 2005-10-19 Enforcing strongly-ordered requests in a weakly-ordered processing

Publications (2)

Publication Number Publication Date
WO2006102667A2 WO2006102667A2 (en) 2006-09-28
WO2006102667A3 true WO2006102667A3 (en) 2007-02-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/011174 WO2006102667A2 (en) 2005-03-23 2006-03-23 Enforcing strongly-ordered requests in a weakly-ordered processing system

Country Status (11)

Country Link
US (1) US9026744B2 (en)
EP (1) EP1861786B1 (en)
JP (1) JP4824748B2 (en)
KR (2) KR101185623B1 (en)
CN (1) CN101176083B (en)
CA (1) CA2601639C (en)
HK (1) HK1114201A1 (en)
IL (1) IL186001A (en)
RU (1) RU2405194C2 (en)
TW (1) TWI401568B (en)
WO (1) WO2006102667A2 (en)

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US8782356B2 (en) * 2011-12-09 2014-07-15 Qualcomm Incorporated Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
US9383995B2 (en) 2013-01-25 2016-07-05 Apple Inc. Load ordering in a weakly-ordered processor
US9594713B2 (en) * 2014-09-12 2017-03-14 Qualcomm Incorporated Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
JP6356624B2 (en) * 2015-03-23 2018-07-11 東芝メモリ株式会社 Memory device and information processing apparatus
US10534540B2 (en) * 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
JP6944107B2 (en) * 2017-07-11 2021-10-06 富士通株式会社 Information processing equipment, information processing systems and programs
US10877888B2 (en) 2018-09-07 2020-12-29 Apple Inc. Systems and methods for providing distributed global ordering
US11055130B2 (en) 2019-09-15 2021-07-06 Mellanox Technologies, Ltd. Task completion system
US11822973B2 (en) 2019-09-16 2023-11-21 Mellanox Technologies, Ltd. Operation fencing system
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Also Published As

Publication number Publication date
KR101185623B1 (en) 2012-09-24
EP1861786B1 (en) 2015-12-02
JP4824748B2 (en) 2011-11-30
WO2006102667A2 (en) 2006-09-28
US9026744B2 (en) 2015-05-05
US20060218358A1 (en) 2006-09-28
KR20070116907A (en) 2007-12-11
KR20120107016A (en) 2012-09-27
RU2405194C2 (en) 2010-11-27
HK1114201A1 (en) 2008-10-24
CN101176083A (en) 2008-05-07
CA2601639C (en) 2015-12-15
JP2008535068A (en) 2008-08-28
IL186001A0 (en) 2008-01-20
CN101176083B (en) 2012-11-21
TW200703003A (en) 2007-01-16
TWI401568B (en) 2013-07-11
RU2007139101A (en) 2009-04-27
IL186001A (en) 2015-07-30
CA2601639A1 (en) 2006-09-28
EP1861786A2 (en) 2007-12-05

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