WO2006102667A3 - Enforcing strongly-ordered requests in a weakly-ordered processing system - Google Patents
Enforcing strongly-ordered requests in a weakly-ordered processing system Download PDFInfo
- Publication number
- WO2006102667A3 WO2006102667A3 PCT/US2006/011174 US2006011174W WO2006102667A3 WO 2006102667 A3 WO2006102667 A3 WO 2006102667A3 US 2006011174 W US2006011174 W US 2006011174W WO 2006102667 A3 WO2006102667 A3 WO 2006102667A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ordered
- processing system
- weakly
- access requests
- strongly
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
Abstract
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2006800166617A CN101176083B (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly-ordered requests in a weakly-ordered processing system |
CA2601639A CA2601639C (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly-ordered requests in a weakly-ordered processing system |
EP06739776.0A EP1861786B1 (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly-ordered requests in a weakly-ordered processing system |
JP2008503288A JP4824748B2 (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly ordered requests in weakly ordered processing systems |
KR1020077024336A KR101185623B1 (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly ordered requests in a weakly-ordered processing system |
IL186001A IL186001A (en) | 2005-03-23 | 2007-09-17 | Enforcing strongly-ordered requests in a weakly-ordered processing system |
HK08109405.2A HK1114201A1 (en) | 2005-03-23 | 2008-08-25 | Bus interconnect, weakly-ordered processing system and method for enforcing strongly-ordered requests in a weakly-ordered processing system |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US66474905P | 2005-03-23 | 2005-03-23 | |
US60/664,749 | 2005-03-23 | ||
US11/253,307 | 2005-10-19 | ||
US11/253,307 US9026744B2 (en) | 2005-03-23 | 2005-10-19 | Enforcing strongly-ordered requests in a weakly-ordered processing |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006102667A2 WO2006102667A2 (en) | 2006-09-28 |
WO2006102667A3 true WO2006102667A3 (en) | 2007-02-22 |
Family
ID=36754824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/011174 WO2006102667A2 (en) | 2005-03-23 | 2006-03-23 | Enforcing strongly-ordered requests in a weakly-ordered processing system |
Country Status (11)
Country | Link |
---|---|
US (1) | US9026744B2 (en) |
EP (1) | EP1861786B1 (en) |
JP (1) | JP4824748B2 (en) |
KR (2) | KR101185623B1 (en) |
CN (1) | CN101176083B (en) |
CA (1) | CA2601639C (en) |
HK (1) | HK1114201A1 (en) |
IL (1) | IL186001A (en) |
RU (1) | RU2405194C2 (en) |
TW (1) | TWI401568B (en) |
WO (1) | WO2006102667A2 (en) |
Families Citing this family (19)
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US7237098B2 (en) * | 2003-09-08 | 2007-06-26 | Ip-First, Llc | Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence |
US7500045B2 (en) * | 2005-03-23 | 2009-03-03 | Qualcomm Incorporated | Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system |
US7917676B2 (en) | 2006-03-10 | 2011-03-29 | Qualcomm, Incorporated | Efficient execution of memory barrier bus commands with order constrained memory accesses |
US7783817B2 (en) * | 2006-08-31 | 2010-08-24 | Qualcomm Incorporated | Method and apparatus for conditional broadcast of barrier operations |
US7984202B2 (en) * | 2007-06-01 | 2011-07-19 | Qualcomm Incorporated | Device directed memory barriers |
US8352682B2 (en) * | 2009-05-26 | 2013-01-08 | Qualcomm Incorporated | Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system |
GB2474446A (en) | 2009-10-13 | 2011-04-20 | Advanced Risc Mach Ltd | Barrier requests to maintain transaction order in an interconnect with multiple paths |
US8782356B2 (en) * | 2011-12-09 | 2014-07-15 | Qualcomm Incorporated | Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions |
US9383995B2 (en) | 2013-01-25 | 2016-07-05 | Apple Inc. | Load ordering in a weakly-ordered processor |
US9594713B2 (en) * | 2014-09-12 | 2017-03-14 | Qualcomm Incorporated | Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media |
JP6356624B2 (en) * | 2015-03-23 | 2018-07-11 | 東芝メモリ株式会社 | Memory device and information processing apparatus |
US10534540B2 (en) * | 2016-06-06 | 2020-01-14 | Micron Technology, Inc. | Memory protocol |
JP6944107B2 (en) * | 2017-07-11 | 2021-10-06 | 富士通株式会社 | Information processing equipment, information processing systems and programs |
US10877888B2 (en) | 2018-09-07 | 2020-12-29 | Apple Inc. | Systems and methods for providing distributed global ordering |
US11055130B2 (en) | 2019-09-15 | 2021-07-06 | Mellanox Technologies, Ltd. | Task completion system |
US11822973B2 (en) | 2019-09-16 | 2023-11-21 | Mellanox Technologies, Ltd. | Operation fencing system |
US11054998B1 (en) * | 2019-12-12 | 2021-07-06 | Facebook, Inc. | High bandwidth memory system with distributed request broadcasting masters |
EP4310683A1 (en) * | 2021-03-31 | 2024-01-24 | Huawei Technologies Co., Ltd. | Method for executing read-write operation, and soc chip |
JP7349045B1 (en) | 2023-07-05 | 2023-09-21 | 正美 柏田 | Retrofit roll cutter |
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-
2005
- 2005-10-19 US US11/253,307 patent/US9026744B2/en active Active
-
2006
- 2006-03-17 TW TW095109110A patent/TWI401568B/en not_active IP Right Cessation
- 2006-03-23 KR KR1020077024336A patent/KR101185623B1/en not_active IP Right Cessation
- 2006-03-23 EP EP06739776.0A patent/EP1861786B1/en active Active
- 2006-03-23 RU RU2007139101/08A patent/RU2405194C2/en not_active IP Right Cessation
- 2006-03-23 CN CN2006800166617A patent/CN101176083B/en active Active
- 2006-03-23 WO PCT/US2006/011174 patent/WO2006102667A2/en active Application Filing
- 2006-03-23 CA CA2601639A patent/CA2601639C/en not_active Expired - Fee Related
- 2006-03-23 KR KR1020127021776A patent/KR20120107016A/en not_active Application Discontinuation
- 2006-03-23 JP JP2008503288A patent/JP4824748B2/en not_active Expired - Fee Related
-
2007
- 2007-09-17 IL IL186001A patent/IL186001A/en active IP Right Grant
-
2008
- 2008-08-25 HK HK08109405.2A patent/HK1114201A1/en not_active IP Right Cessation
Patent Citations (6)
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JPH04190435A (en) * | 1990-11-26 | 1992-07-08 | Hitachi Ltd | Memory access order guarantee method for multiprocessor system |
US6088771A (en) * | 1997-10-24 | 2000-07-11 | Digital Equipment Corporation | Mechanism for reducing latency of memory barrier operations on a multiprocessor system |
US6038646A (en) * | 1998-01-23 | 2000-03-14 | Sun Microsystems, Inc. | Method and apparatus for enforcing ordered execution of reads and writes across a memory interface |
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Non-Patent Citations (1)
Title |
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PATENT ABSTRACTS OF JAPAN vol. 016, no. 516 (P - 1443) 23 October 1992 (1992-10-23) * |
Also Published As
Publication number | Publication date |
---|---|
KR101185623B1 (en) | 2012-09-24 |
EP1861786B1 (en) | 2015-12-02 |
JP4824748B2 (en) | 2011-11-30 |
WO2006102667A2 (en) | 2006-09-28 |
US9026744B2 (en) | 2015-05-05 |
US20060218358A1 (en) | 2006-09-28 |
KR20070116907A (en) | 2007-12-11 |
KR20120107016A (en) | 2012-09-27 |
RU2405194C2 (en) | 2010-11-27 |
HK1114201A1 (en) | 2008-10-24 |
CN101176083A (en) | 2008-05-07 |
CA2601639C (en) | 2015-12-15 |
JP2008535068A (en) | 2008-08-28 |
IL186001A0 (en) | 2008-01-20 |
CN101176083B (en) | 2012-11-21 |
TW200703003A (en) | 2007-01-16 |
TWI401568B (en) | 2013-07-11 |
RU2007139101A (en) | 2009-04-27 |
IL186001A (en) | 2015-07-30 |
CA2601639A1 (en) | 2006-09-28 |
EP1861786A2 (en) | 2007-12-05 |
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