WO2006078740A3 - Structure and method to optimize strain in cmosfets - Google Patents

Structure and method to optimize strain in cmosfets Download PDF

Info

Publication number
WO2006078740A3
WO2006078740A3 PCT/US2006/001768 US2006001768W WO2006078740A3 WO 2006078740 A3 WO2006078740 A3 WO 2006078740A3 US 2006001768 W US2006001768 W US 2006001768W WO 2006078740 A3 WO2006078740 A3 WO 2006078740A3
Authority
WO
WIPO (PCT)
Prior art keywords
strain
mosfets
coating
inducing
pmosfets
Prior art date
Application number
PCT/US2006/001768
Other languages
French (fr)
Other versions
WO2006078740A2 (en
Inventor
Xiangdong Chen
Haining S Yang
Original Assignee
Ibm
Xiangdong Chen
Haining S Yang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Xiangdong Chen, Haining S Yang filed Critical Ibm
Priority to EP06718789A priority Critical patent/EP1842239A4/en
Priority to JP2007552237A priority patent/JP4884397B2/en
Publication of WO2006078740A2 publication Critical patent/WO2006078740A2/en
Publication of WO2006078740A3 publication Critical patent/WO2006078740A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.
PCT/US2006/001768 2005-01-19 2006-01-19 Structure and method to optimize strain in cmosfets WO2006078740A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06718789A EP1842239A4 (en) 2005-01-19 2006-01-19 Structure and method to optimize strain in cmosfets
JP2007552237A JP4884397B2 (en) 2005-01-19 2006-01-19 Method for optimizing distortion in a CMOSFET

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,745 2005-01-19
US10/905,745 US7432553B2 (en) 2005-01-19 2005-01-19 Structure and method to optimize strain in CMOSFETs

Publications (2)

Publication Number Publication Date
WO2006078740A2 WO2006078740A2 (en) 2006-07-27
WO2006078740A3 true WO2006078740A3 (en) 2007-11-01

Family

ID=36683015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/001768 WO2006078740A2 (en) 2005-01-19 2006-01-19 Structure and method to optimize strain in cmosfets

Country Status (6)

Country Link
US (3) US7432553B2 (en)
EP (1) EP1842239A4 (en)
JP (1) JP4884397B2 (en)
CN (1) CN101496176A (en)
TW (1) TW200634926A (en)
WO (1) WO2006078740A2 (en)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585704B2 (en) * 2005-04-01 2009-09-08 International Business Machines Corporation Method of producing highly strained PECVD silicon nitride thin films at low temperature
US7858458B2 (en) * 2005-06-14 2010-12-28 Micron Technology, Inc. CMOS fabrication
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US20070013070A1 (en) * 2005-06-23 2007-01-18 Liang Mong S Semiconductor devices and methods of manufacture thereof
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7589385B2 (en) * 2005-07-26 2009-09-15 United Microelectronics Corp. Semiconductor CMOS transistors and method of manufacturing the same
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7297584B2 (en) * 2005-10-07 2007-11-20 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having a dual stress liner
KR100651603B1 (en) * 2005-12-13 2006-11-30 동부일렉트로닉스 주식회사 Mathode of manufacturing semiconductor device
US7378308B2 (en) * 2006-03-30 2008-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS devices with improved gap-filling
US7790540B2 (en) * 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
JP2008066484A (en) * 2006-09-06 2008-03-21 Fujitsu Ltd Cmos semiconductor device and its manufacturing method
JP2008131023A (en) * 2006-11-27 2008-06-05 Nec Electronics Corp Semiconductor device and its manufacturing method
JP2008192686A (en) * 2007-02-01 2008-08-21 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US20080185655A1 (en) * 2007-02-02 2008-08-07 United Microelectronics Corp. Smiconductor device, method for fabricating thereof and method for increasing film stress
US20080203485A1 (en) * 2007-02-28 2008-08-28 International Business Machines Corporation Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same
US20080277726A1 (en) * 2007-05-08 2008-11-13 Doris Bruce B Devices with Metal Gate, High-k Dielectric, and Butted Electrodes
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US20080315317A1 (en) * 2007-06-22 2008-12-25 Chartered Semiconductor Manufacturing Ltd. Semiconductor system having complementary strained channels
US20090068824A1 (en) * 2007-09-11 2009-03-12 United Microelectronics Corp. Fabricating method of semiconductor device
US20090095991A1 (en) * 2007-10-11 2009-04-16 International Business Machines Corporation Method of forming strained mosfet devices using phase transformable materials
JP5268385B2 (en) 2008-02-13 2013-08-21 パナソニック株式会社 Semiconductor device
US7727834B2 (en) * 2008-02-14 2010-06-01 Toshiba America Electronic Components, Inc. Contact configuration and method in dual-stress liner semiconductor device
JP2009200155A (en) * 2008-02-20 2009-09-03 Nec Electronics Corp Semiconductor device and method for manufacturing the same
US8999863B2 (en) * 2008-06-05 2015-04-07 Globalfoundries Singapore Pte. Ltd. Stress liner for stress engineering
US7795679B2 (en) * 2008-07-24 2010-09-14 International Business Machines Corporation Device structures with a self-aligned damage layer and methods for forming such device structures
US8298876B2 (en) 2009-03-27 2012-10-30 International Business Machines Corporation Methods for normalizing strain in semiconductor devices and strain normalized semiconductor devices
US8389300B2 (en) * 2010-04-02 2013-03-05 Centre National De La Recherche Scientifique Controlling ferroelectricity in dielectric films by process induced uniaxial strain
US8673757B2 (en) 2010-10-28 2014-03-18 International Business Machines Corporation Structure and method for using high-k material as an etch stop layer in dual stress layer process
US9159633B2 (en) 2013-09-13 2015-10-13 Globalfoundries Inc. Test macro for use with a multi-patterning lithography process
KR102231205B1 (en) * 2014-11-19 2021-03-25 삼성전자주식회사 Semiconductor device and method for fabricating the same
FR3076077B1 (en) * 2017-12-22 2020-02-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives CONSTRUCTION OF CONSTRAINED CHANNEL TRANSISTORS

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US20040195623A1 (en) * 2003-04-03 2004-10-07 Chung-Hu Ge Strained channel on insulator device

Family Cites Families (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
DE3419392C1 (en) 1984-05-24 1985-12-05 Deutsche Texaco Ag, 2000 Hamburg Process for the continuous production of isopropyl alcohol or sec. Butyl alcohol
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
EP0219641B1 (en) * 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrated circuit comprising bipolar and complementary mos transistors on a common substrate, and method of making the same
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) * 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) * 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) * 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
WO1994027317A1 (en) 1993-05-06 1994-11-24 Siemens Aktiengesellschaft Process for producing components on an soi substrate
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (en) * 1997-10-15 2001-02-26 日本電気株式会社 Semiconductor device
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (en) * 1998-03-02 2000-12-15 윤종용 Method of fabricating trench isolation in an integrated circuit
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US6165383A (en) * 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US6074903A (en) 1998-06-16 2000-06-13 Siemens Aktiengesellschaft Method for forming electrical isolation for semiconductor devices
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (en) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6319794B1 (en) * 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
JP2000216377A (en) * 1999-01-20 2000-08-04 Nec Corp Method for manufacturing semiconductor device
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
JP4521542B2 (en) 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor substrate
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
KR100332108B1 (en) * 1999-06-29 2002-04-10 박종섭 Transistor in a semiconductor device and method of manufacuring the same
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
US6493497B1 (en) * 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) * 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
US7115954B2 (en) * 2000-11-22 2006-10-03 Renesas Technology Corp. Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same
JP2003086708A (en) * 2000-12-08 2003-03-20 Hitachi Ltd Semiconductor device and manufacturing method thereof
US6563152B2 (en) * 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
KR100390567B1 (en) 2000-12-30 2003-07-07 주식회사 동진쎄미켐 method of controlling photoresist stripping process and method of regenerating photoresist stripping composition using near infrared spectrometer
US20020086497A1 (en) * 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
US6809014B2 (en) * 2001-03-14 2004-10-26 Micron Technology, Inc. Method to fabricate surface p-channel CMOS
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) * 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6908810B2 (en) * 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (en) * 2001-08-21 2003-02-28 Nec Corp Semiconductor device and manufacturing method therefor
US20030057184A1 (en) * 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) * 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
JP4173672B2 (en) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US6689676B1 (en) * 2002-07-26 2004-02-10 Motorola, Inc. Method for forming a semiconductor device structure in a semiconductor layer
JP4030383B2 (en) * 2002-08-26 2008-01-09 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US7316950B2 (en) * 2003-04-22 2008-01-08 National University Of Singapore Method of fabricating a CMOS device with dual metal gate electrodes
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US7183221B2 (en) * 2003-11-06 2007-02-27 Texas Instruments Incorporated Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer
US7052946B2 (en) * 2004-03-10 2006-05-30 Taiwan Semiconductor Manufacturing Co. Ltd. Method for selectively stressing MOSFETs to improve charge carrier mobility
US20050214998A1 (en) * 2004-03-26 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Local stress control for CMOS performance enhancement
US7018883B2 (en) * 2004-05-05 2006-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Dual work function gate electrodes
US7053400B2 (en) * 2004-05-05 2006-05-30 Advanced Micro Devices, Inc. Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
US7220630B2 (en) * 2004-05-21 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for selectively forming strained etch stop layers to improve FET charge carrier mobility
DE102004052578B4 (en) * 2004-10-29 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale A method of creating a different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified internal stress
US7193254B2 (en) * 2004-11-30 2007-03-20 International Business Machines Corporation Structure and method of applying stresses to PFET and NFET transistor channels for improved performance
JP4361886B2 (en) * 2005-02-24 2009-11-11 富士通マイクロエレクトロニクス株式会社 Semiconductor integrated circuit device and manufacturing method thereof
JP2006324278A (en) * 2005-05-17 2006-11-30 Sony Corp Semiconductor device and manufacturing method thereof
DE102005052054B4 (en) * 2005-10-31 2010-08-19 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device with shaped channel region transistors and method of making the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US20040195623A1 (en) * 2003-04-03 2004-10-07 Chung-Hu Ge Strained channel on insulator device

Also Published As

Publication number Publication date
US20080070357A1 (en) 2008-03-20
JP4884397B2 (en) 2012-02-29
JP2008527755A (en) 2008-07-24
EP1842239A4 (en) 2009-07-01
WO2006078740A2 (en) 2006-07-27
US20060157795A1 (en) 2006-07-20
US7432553B2 (en) 2008-10-07
CN101496176A (en) 2009-07-29
EP1842239A2 (en) 2007-10-10
US20080251853A1 (en) 2008-10-16
TW200634926A (en) 2006-10-01

Similar Documents

Publication Publication Date Title
WO2006078740A3 (en) Structure and method to optimize strain in cmosfets
TW200735345A (en) Direct channel stress
WO2004114383A3 (en) Strained-silicon-on-insulator single- and double-gate mosfet and method for forming the same
CA2501580A1 (en) Method of forming strained silicon on insulator (ssoi) and structures formed thereby
SG137760A1 (en) Method of fabricating a transistor structure
WO2007053339A3 (en) Method for forming a semiconductor structure and structure thereof
WO2006065759A3 (en) Dual stressed soi substrates
SG153815A1 (en) Selective stress relaxation of contact etch stop layer through layout design
WO2005043591A8 (en) HIGH PERFORMANCE STRESS-ENHANCED MOSFETs USING Si:C AND SiGe EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE
WO2005081748A3 (en) Semiconductor structure having strained semiconductor and method therefor
WO2008135013A3 (en) Semiconductor chip and method for producing a semiconductor chip
WO2010151604A3 (en) Methods for fabricating passivated silicon nanowires and devices thus obtained
WO2002047168A3 (en) Cmos inverter circuits utilizing strained silicon surface channel mosfets
TWI371782B (en) Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same
WO2004051708A3 (en) Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer
TW200707632A (en) Semiconductor device and forming method thereof
WO2006014783A3 (en) Method for manufacturing a semiconductor device having silicided regions
WO2006105452A3 (en) Semiconductor device based on a scr
WO2008120335A1 (en) Semiconductor device, and its manufacturing method
WO2007124209A3 (en) Stressor integration and method thereof
WO2010018162A3 (en) Thermoelectric device
SG139657A1 (en) Structure and method to implement dual stressor layers with improved silicide control
TW200610005A (en) Improved strained-silicon CMOS device and method
TW200625603A (en) Semiconductor devices having faceted channels and methods of fabricating such devices
WO2007133870A3 (en) Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680002466.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007552237

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2006718789

Country of ref document: EP

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)