WO2006065523A3 - Apparatus and method for memory operations using address-dependent conditions - Google Patents
Apparatus and method for memory operations using address-dependent conditions Download PDFInfo
- Publication number
- WO2006065523A3 WO2006065523A3 PCT/US2005/043074 US2005043074W WO2006065523A3 WO 2006065523 A3 WO2006065523 A3 WO 2006065523A3 US 2005043074 W US2005043074 W US 2005043074W WO 2006065523 A3 WO2006065523 A3 WO 2006065523A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- address
- memory cell
- memory operations
- bit
- lines
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1677—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Abstract
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT05852375T ATE496372T1 (en) | 2004-12-17 | 2005-11-29 | APPARATUS AND METHOD FOR STORAGE OPERATIONS USING ADDRESS DEPENDENT CONDITIONS |
KR1020077013751A KR101100805B1 (en) | 2004-12-17 | 2005-11-29 | Apparatus and method for memory operations using address-dependent conditions |
JP2007546708A JP5285277B2 (en) | 2004-12-17 | 2005-11-29 | Apparatus and method for memory operation using address dependent conditions |
CN200580042742XA CN101208751B (en) | 2004-12-17 | 2005-11-29 | Apparatus and method for memory operations using address-dependent conditions |
EP05852375A EP1825475B1 (en) | 2004-12-17 | 2005-11-29 | Apparatus and method for memory operations using address-dependent conditions |
DE602005026052T DE602005026052D1 (en) | 2004-12-17 | 2005-11-29 | DEVICE AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-RELATED CONDITIONS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/015,440 | 2004-12-17 | ||
US11/015,440 US7218570B2 (en) | 2004-12-17 | 2004-12-17 | Apparatus and method for memory operations using address-dependent conditions |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006065523A2 WO2006065523A2 (en) | 2006-06-22 |
WO2006065523A3 true WO2006065523A3 (en) | 2006-10-05 |
Family
ID=36588354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/043074 WO2006065523A2 (en) | 2004-12-17 | 2005-11-29 | Apparatus and method for memory operations using address-dependent conditions |
Country Status (8)
Country | Link |
---|---|
US (1) | US7218570B2 (en) |
EP (1) | EP1825475B1 (en) |
JP (1) | JP5285277B2 (en) |
KR (1) | KR101100805B1 (en) |
CN (1) | CN101208751B (en) |
AT (1) | ATE496372T1 (en) |
DE (1) | DE602005026052D1 (en) |
WO (1) | WO2006065523A2 (en) |
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US7701797B2 (en) * | 2006-05-15 | 2010-04-20 | Apple Inc. | Two levels of voltage regulation supplied for logic and data programming voltage of a memory device |
US7639542B2 (en) * | 2006-05-15 | 2009-12-29 | Apple Inc. | Maintenance operations for multi-level data storage cells |
US7551486B2 (en) * | 2006-05-15 | 2009-06-23 | Apple Inc. | Iterative memory cell charging based on reference cell value |
US8000134B2 (en) | 2006-05-15 | 2011-08-16 | Apple Inc. | Off-die charge pump that supplies multiple flash devices |
US7639531B2 (en) * | 2006-05-15 | 2009-12-29 | Apple Inc. | Dynamic cell bit resolution |
US7568135B2 (en) | 2006-05-15 | 2009-07-28 | Apple Inc. | Use of alternative value in cell detection |
US7852690B2 (en) * | 2006-05-15 | 2010-12-14 | Apple Inc. | Multi-chip package for a flash memory |
US7911834B2 (en) * | 2006-05-15 | 2011-03-22 | Apple Inc. | Analog interface for a flash memory die |
US7283414B1 (en) | 2006-05-24 | 2007-10-16 | Sandisk 3D Llc | Method for improving the precision of a temperature-sensor circuit |
US20080135087A1 (en) | 2007-05-10 | 2008-06-12 | Rangappan Anikara | Thin solar concentrator |
US8358526B2 (en) * | 2008-02-28 | 2013-01-22 | Contour Semiconductor, Inc. | Diagonal connection storage array |
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US8885400B2 (en) * | 2013-02-21 | 2014-11-11 | Sandisk 3D Llc | Compensation scheme for non-volatile memory |
US10175906B2 (en) * | 2014-07-31 | 2019-01-08 | Hewlett Packard Enterprise Development Lp | Encoding data within a crossbar memory array |
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US20160379707A1 (en) * | 2015-06-25 | 2016-12-29 | Research & Business Foundation Sungkyunkwan University | Cross point memory device |
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JP2018160295A (en) | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | Semiconductor memory |
CN108492844B (en) * | 2018-03-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Double-split gate flash memory array and programming method thereof |
US11081151B2 (en) * | 2019-09-26 | 2021-08-03 | Intel Corporation | Techniques to improve a read operation to a memory array |
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2004
- 2004-12-17 US US11/015,440 patent/US7218570B2/en active Active
-
2005
- 2005-11-29 AT AT05852375T patent/ATE496372T1/en not_active IP Right Cessation
- 2005-11-29 DE DE602005026052T patent/DE602005026052D1/en active Active
- 2005-11-29 KR KR1020077013751A patent/KR101100805B1/en active IP Right Grant
- 2005-11-29 WO PCT/US2005/043074 patent/WO2006065523A2/en active Application Filing
- 2005-11-29 CN CN200580042742XA patent/CN101208751B/en active Active
- 2005-11-29 EP EP05852375A patent/EP1825475B1/en active Active
- 2005-11-29 JP JP2007546708A patent/JP5285277B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
EP1825475A4 (en) | 2009-01-07 |
CN101208751A (en) | 2008-06-25 |
ATE496372T1 (en) | 2011-02-15 |
KR20070104526A (en) | 2007-10-26 |
US7218570B2 (en) | 2007-05-15 |
US20060133125A1 (en) | 2006-06-22 |
JP5285277B2 (en) | 2013-09-11 |
EP1825475A2 (en) | 2007-08-29 |
CN101208751B (en) | 2010-09-15 |
DE602005026052D1 (en) | 2011-03-03 |
WO2006065523A2 (en) | 2006-06-22 |
EP1825475B1 (en) | 2011-01-19 |
JP2008524772A (en) | 2008-07-10 |
KR101100805B1 (en) | 2012-01-02 |
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